Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13649917

1

T1

10228

T4

11912

T5

770

full_word

52546352

1

T1

102729

T2

9162

T3

6142

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	66196019	1			T1	112957		T2	9162		T3	6142
auto[TlIntgErrCmd]	87	1			T52	3		T51	7		T53	7
auto[TlIntgErrData]	71	1			T52	2		T51	1		T53	6
auto[TlIntgErrBoth]	92	1			T52	5		T51	2		T53	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30237794

1

T1

56372

T2

4577

T3

2048

auto[1]

35958475

1

T1

56585

T2

4585

T3

4094

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6510598	1			T1	5136		T4	5847		T5	380
auto[TlIntgErrNone]	partial	auto[1]	7139091	1			T1	5092		T4	6065		T5	390
auto[TlIntgErrNone]	full_word	auto[0]	23727089	1			T1	51236		T2	4577		T3	2048
auto[TlIntgErrNone]	full_word	auto[1]	28819241	1			T1	51493		T2	4585		T3	4094
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T52	1		T51	2		T53	4
auto[TlIntgErrCmd]	partial	auto[1]	43	1			T52	2		T51	5		T53	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T123	2		T128	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T126	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	24	1			T52	2		T53	3		T59	1
auto[TlIntgErrData]	partial	auto[1]	39	1			T53	3		T59	2		T126	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T51	1		T124	1		T130	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T59	1		T131	1		T132	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T52	2		T53	1		T59	3
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T52	2		T51	1		T53	6
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T59	1		T124	1		T127	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T52	1		T51	1		T125	1