Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	472052	1			T4	3718		T9	801		T13	987
auto[1]	10522716	1			T1	23177		T2	4576		T4	2513
auto[2]	392371	1			T4	2345		T9	648		T13	855
auto[3]	10457319	1			T1	22985		T2	4584		T4	1287

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14137326	1			T1	38225		T2	9160		T4	7578
auto[1]	2093177	1			T1	3804		T4	938		T5	4
auto[2]	2084789	1			T1	3782		T4	1205		T5	9
auto[3]	3529166	1			T1	351		T4	142		T5	26

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8055769

1

T1

46107

T2

9153

T4

9855

auto[1]

13788689

1

T1

55

T2

7

T4

8

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	170161	1			T4	3087		T9	22		T13	819
auto[0]	auto[0]	auto[1]	18010	1			T4	311		T9	106		T13	71
auto[0]	auto[0]	auto[2]	17980	1			T4	283		T9	136		T13	84
auto[0]	auto[0]	auto[3]	8401	1			T4	35		T9	534		T13	13
auto[0]	auto[1]	auto[0]	3143011	1			T1	19158		T2	4574		T4	1909
auto[0]	auto[1]	auto[1]	321038	1			T1	1911		T4	361		T5	3
auto[0]	auto[1]	auto[2]	313409	1			T1	1899		T4	202		T5	7
auto[0]	auto[1]	auto[3]	67475	1			T1	178		T4	39		T5	11
auto[0]	auto[2]	auto[0]	142816	1			T4	1812		T9	29		T13	731
auto[0]	auto[2]	auto[1]	15436	1			T4	174		T9	120		T13	62
auto[0]	auto[2]	auto[2]	14874	1			T4	327		T9	88		T13	57
auto[0]	auto[2]	auto[3]	6406	1			T4	29		T9	410		T13	2
auto[0]	auto[3]	auto[0]	3115599	1			T1	19023		T2	4579		T4	767
auto[0]	auto[3]	auto[1]	311360	1			T1	1888		T4	88		T5	1
auto[0]	auto[3]	auto[2]	320449	1			T1	1878		T4	392		T5	2
auto[0]	auto[3]	auto[3]	69344	1			T1	172		T4	39		T5	15
auto[1]	auto[0]	auto[0]	8666	1			T4	1		T7	1		T112	699
auto[1]	auto[0]	auto[1]	38190	1			T4	1		T9	1		T112	3120
auto[1]	auto[0]	auto[2]	38302	1			T112	3230		T140	4523		T46	1
auto[1]	auto[0]	auto[3]	172342	1			T9	2		T142	1		T112	14067
auto[1]	auto[1]	auto[0]	3773780	1			T1	27		T2	2		T4	1
auto[1]	auto[1]	auto[1]	692947	1			T1	2		T4	1		T13	1
auto[1]	auto[1]	auto[2]	662466	1			T1	2		T19	2		T77	588
auto[1]	auto[1]	auto[3]	1548590	1			T9	2		T77	7255		T111	547
auto[1]	auto[2]	auto[0]	7831	1			T4	1		T13	3		T112	624
auto[1]	auto[2]	auto[1]	35009	1			T4	2		T112	2887		T140	4075
auto[1]	auto[2]	auto[2]	30843	1			T112	2675		T140	3744		T50	1
auto[1]	auto[2]	auto[3]	139156	1			T9	1		T112	11871		T140	16963
auto[1]	auto[3]	auto[0]	3775462	1			T1	17		T2	5		T16	3
auto[1]	auto[3]	auto[1]	661187	1			T1	3		T16	1		T19	1
auto[1]	auto[3]	auto[2]	686466	1			T1	3		T4	1		T77	1593
auto[1]	auto[3]	auto[3]	1517452	1			T1	1		T77	7189		T143	3