Unified Coverage Report :: Module :: prim_subst_perm

Module : prim_subst_perm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_subst_perm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_ram_1p_scr.gen_addr_scr.u_prim_subst_perm	100.00	100.00
tb.dut.u_prim_ram_1p_scr.gen_diffuse_data[0].u_prim_subst_perm_enc	100.00	100.00
tb.dut.u_prim_ram_1p_scr.gen_diffuse_data[0].u_prim_subst_perm_dec	100.00	100.00

---

Module Instance : tb.dut.u_prim_ram_1p_scr.gen_addr_scr.u_prim_subst_perm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.87	100.00	91.49			100.00	100.00	u_prim_ram_1p_scr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_ram_1p_scr.gen_diffuse_data[0].u_prim_subst_perm_enc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.87	100.00	91.49			100.00	100.00	u_prim_ram_1p_scr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_ram_1p_scr.gen_diffuse_data[0].u_prim_subst_perm_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.87	100.00	91.49			100.00	100.00	u_prim_ram_1p_scr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_subst_perm ( parameter DataWidth=10,NumRounds=2,Decrypt=0 + DataWidth=39,NumRounds=2,Decrypt=0 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_prim_ram_1p_scr.gen_addr_scr.u_prim_subst_perm

SCORE	LINE
100.00	100.00

tb.dut.u_prim_ram_1p_scr.gen_diffuse_data[0].u_prim_subst_perm_enc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	35	1	1	100.00
ALWAYS	64	10	10	100.00
ALWAYS	64	10	10	100.00
CONT_ASSIGN	90	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_subst_perm.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_subst_perm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
35	1	1
64	1	1
68	1	1
69	1	1
72	1	1
73	1	1
78	1	1
79	1	1
80	1	1
81	1	1
83	1	1
64	1	1
68	1	1
69	1	1
72	1	1
73	1	1
78	1	1
79	1	1
80	1	1
81	1	1
83	1	1
90	1	1

---

Line Coverage for Module : prim_subst_perm ( parameter DataWidth=39,NumRounds=2,Decrypt=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_prim_ram_1p_scr.gen_diffuse_data[0].u_prim_subst_perm_dec

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	35	1	1	100.00
ALWAYS	43	10	10	100.00
ALWAYS	43	10	10	100.00
CONT_ASSIGN	90	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_subst_perm.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_subst_perm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
35	1	1
43	1	1
45	1	1
46	1	1
47	1	1
48	1	1
51	1	1
52	1	1
55	1	1
56	1	1
58	1	1
43	1	1
45	1	1
46	1	1
47	1	1
48	1	1
51	1	1
52	1	1
55	1	1
56	1	1
58	1	1
90	1	1

Line Coverage for Instance : tb.dut.u_prim_ram_1p_scr.gen_addr_scr.u_prim_subst_perm

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	35	1	1	100.00
ALWAYS	64	10	10	100.00
ALWAYS	64	10	10	100.00
CONT_ASSIGN	90	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_subst_perm.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_subst_perm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
35	1	1
64	1	1
68	1	1
69	1	1
72	1	1
73	1	1
78	1	1
79	1	1
80	1	1
81	1	1
83	1	1
64	1	1
68	1	1
69	1	1
72	1	1
73	1	1
78	1	1
79	1	1
80	1	1
81	1	1
83	1	1
90	1	1

Line Coverage for Instance : tb.dut.u_prim_ram_1p_scr.gen_diffuse_data[0].u_prim_subst_perm_enc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	35	1	1	100.00
ALWAYS	64	10	10	100.00
ALWAYS	64	10	10	100.00
CONT_ASSIGN	90	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_subst_perm.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_subst_perm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
35	1	1
64	1	1
68	1	1
69	1	1
72	1	1
73	1	1
78	1	1
79	1	1
80	1	1
81	1	1
83	1	1
64	1	1
68	1	1
69	1	1
72	1	1
73	1	1
78	1	1
79	1	1
80	1	1
81	1	1
83	1	1
90	1	1

Line Coverage for Instance : tb.dut.u_prim_ram_1p_scr.gen_diffuse_data[0].u_prim_subst_perm_dec

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	35	1	1	100.00
ALWAYS	43	10	10	100.00
ALWAYS	43	10	10	100.00
CONT_ASSIGN	90	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_subst_perm.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_subst_perm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
35	1	1
43	1	1
45	1	1
46	1	1
47	1	1
48	1	1
51	1	1
52	1	1
55	1	1
56	1	1
58	1	1
43	1	1
45	1	1
46	1	1
47	1	1
48	1	1
51	1	1
52	1	1
55	1	1
56	1	1
58	1	1
90	1	1