Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.85	100.00	97.56	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	305805941	164038	0	0
ctrl_regwen_rd_A	305805941	8917	0	0
exec_rd_A	305805941	7929	0	0
exec_regwen_rd_A	305805941	8761	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305805941	164038	0	0
T18	97995	4113	0	0
T19	167553	0	0	0
T24	847	0	0	0
T34	72856	1159	0	0
T35	3598	84	0	0
T51	0	2	0	0
T52	11316	4	0	0
T53	0	5	0	0
T54	0	152	0	0
T55	0	15	0	0
T56	0	17	0	0
T57	0	7	0	0
T62	174390	0	0	0
T63	1474	0	0	0
T64	2482	0	0	0
T65	7819	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305805941	8917	0	0
T57	2789	9	0	0
T58	13531	0	0	0
T59	0	73	0	0
T68	14382	432	0	0
T69	44732	86	0	0
T71	1221	11	0	0
T72	2516	25	0	0
T73	39732	40	0	0
T74	1090	0	0	0
T75	38064	0	0	0
T76	860	0	0	0
T80	0	17	0	0
T88	0	39	0	0
T121	0	2	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305805941	7929	0	0
T57	2789	9	0	0
T58	13531	0	0	0
T59	0	107	0	0
T68	14382	429	0	0
T69	44732	69	0	0
T71	1221	14	0	0
T72	2516	10	0	0
T73	39732	44	0	0
T74	1090	0	0	0
T75	38064	0	0	0
T76	860	0	0	0
T80	0	16	0	0
T88	0	40	0	0
T121	0	3	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305805941	8761	0	0
T57	2789	5	0	0
T58	13531	0	0	0
T59	0	75	0	0
T68	14382	465	0	0
T69	44732	72	0	0
T71	1221	15	0	0
T72	2516	48	0	0
T73	39732	31	0	0
T74	1090	6	0	0
T75	38064	0	0	0
T76	860	0	0	0
T80	0	32	0	0
T121	0	6	0	0