Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14591874	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

61041843

1

T1

357

T2

613438

T4

183621

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	37697422	1			T1	940		T2	336870		T4	100962
values[0x0]	17504298	1			T1	325		T2	162751		T4	48641
values[0x1]	20431997	1			T1	653		T2	175157		T4	52471

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7269814	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

68363903

1

T1

1135

T2

644179

T4

192866

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	343837	1			T1	10		T2	2694		T4	763
valid_sources[0x01]	283463	1			T1	14		T2	2579		T4	778
valid_sources[0x02]	287184	1			T1	13		T2	2638		T4	826
valid_sources[0x03]	273499	1			T1	11		T2	2580		T4	775
valid_sources[0x04]	380124	1			T1	8		T2	2696		T4	867
valid_sources[0x05]	286505	1			T1	10		T2	2601		T4	816
valid_sources[0x06]	259934	1			T1	6		T2	2635		T4	754
valid_sources[0x07]	256862	1			T1	10		T2	2370		T4	748
valid_sources[0x08]	297946	1			T1	6		T2	2782		T4	763
valid_sources[0x09]	337028	1			T1	3		T2	2580		T4	772
valid_sources[0x0a]	315810	1			T1	8		T2	2572		T4	804
valid_sources[0x0b]	267881	1			T1	5		T2	2568		T4	813
valid_sources[0x0c]	346336	1			T1	12		T2	2780		T4	751
valid_sources[0x0d]	261937	1			T1	8		T2	2813		T4	809
valid_sources[0x0e]	278011	1			T1	10		T2	2614		T4	815
valid_sources[0x0f]	282344	1			T1	4		T2	2649		T4	773
valid_sources[0x10]	266868	1			T2	2604		T4	797		T8	313
valid_sources[0x11]	331764	1			T1	8		T2	2432		T4	751
valid_sources[0x12]	275426	1			T1	2		T2	2673		T4	768
valid_sources[0x13]	266984	1			T1	16		T2	2712		T4	787
valid_sources[0x14]	274073	1			T1	8		T2	2741		T4	863
valid_sources[0x15]	260907	1			T1	6		T2	2656		T4	763
valid_sources[0x16]	314651	1			T1	9		T2	2525		T4	765
valid_sources[0x17]	258041	1			T1	11		T2	2713		T4	730
valid_sources[0x18]	334062	1			T1	6		T2	2717		T4	746
valid_sources[0x19]	345327	1			T1	5		T2	2728		T4	741
valid_sources[0x1a]	253884	1			T1	10		T2	2743		T4	826
valid_sources[0x1b]	296548	1			T1	9		T2	2687		T4	851
valid_sources[0x1c]	271893	1			T1	6		T2	2690		T4	763
valid_sources[0x1d]	296667	1			T1	3		T2	2754		T4	777
valid_sources[0x1e]	253776	1			T1	6		T2	2538		T4	863
valid_sources[0x1f]	298784	1			T1	3		T2	2700		T4	804
valid_sources[0x20]	246082	1			T1	2		T2	2636		T4	744
valid_sources[0x21]	333025	1			T1	9		T2	2617		T4	743
valid_sources[0x22]	304773	1			T1	5		T2	2754		T4	759
valid_sources[0x23]	278013	1			T1	7		T2	2567		T4	806
valid_sources[0x24]	281657	1			T1	9		T2	2681		T4	801
valid_sources[0x25]	274806	1			T1	4		T2	2524		T4	672
valid_sources[0x26]	253379	1			T1	8		T2	2419		T4	803
valid_sources[0x27]	268862	1			T1	10		T2	2666		T4	751
valid_sources[0x28]	320544	1			T1	13		T2	2366		T4	797
valid_sources[0x29]	296025	1			T1	8		T2	2519		T4	769
valid_sources[0x2a]	268048	1			T1	14		T2	2593		T4	813
valid_sources[0x2b]	316034	1			T1	7		T2	2698		T4	773
valid_sources[0x2c]	305449	1			T1	2		T2	2717		T4	800
valid_sources[0x2d]	330463	1			T1	8		T2	2677		T4	920
valid_sources[0x2e]	254335	1			T1	12		T2	2750		T4	717
valid_sources[0x2f]	268598	1			T1	8		T2	2742		T4	785
valid_sources[0x30]	329802	1			T1	3		T2	2620		T4	911
valid_sources[0x31]	287885	1			T1	5		T2	2584		T4	772
valid_sources[0x32]	254640	1			T1	3		T2	2643		T4	799
valid_sources[0x33]	380032	1			T1	8		T2	2879		T4	808
valid_sources[0x34]	254872	1			T1	9		T2	2603		T4	772
valid_sources[0x35]	357024	1			T1	15		T2	2559		T4	810
valid_sources[0x36]	264029	1			T1	6		T2	2671		T4	776
valid_sources[0x37]	301380	1			T1	9		T2	2813		T4	766
valid_sources[0x38]	299900	1			T1	6		T2	2751		T4	742
valid_sources[0x39]	313635	1			T1	6		T2	2637		T4	856
valid_sources[0x3a]	315966	1			T1	10		T2	2537		T4	797
valid_sources[0x3b]	278592	1			T1	9		T2	2629		T4	766
valid_sources[0x3c]	262685	1			T1	12		T2	2687		T4	732
valid_sources[0x3d]	264949	1			T1	4		T2	2482		T4	793
valid_sources[0x3e]	267580	1			T1	12		T2	2561		T4	764
valid_sources[0x3f]	273709	1			T1	3		T2	2746		T4	750
valid_sources[0x40]	306004	1			T1	5		T2	2534		T4	740
valid_sources[0x41]	363787	1			T1	6		T2	2434		T4	766
valid_sources[0x42]	291350	1			T1	8		T2	2655		T4	818
valid_sources[0x43]	277598	1			T1	14		T2	2622		T4	825
valid_sources[0x44]	280795	1			T1	13		T2	2581		T4	774
valid_sources[0x45]	292883	1			T1	5		T2	2676		T4	769
valid_sources[0x46]	263452	1			T1	11		T2	2617		T4	815
valid_sources[0x47]	300201	1			T1	7		T2	2550		T4	765
valid_sources[0x48]	328636	1			T1	9		T2	2799		T4	735
valid_sources[0x49]	319314	1			T1	14		T2	2720		T4	735
valid_sources[0x4a]	311945	1			T1	12		T2	2542		T4	814
valid_sources[0x4b]	274283	1			T1	7		T2	2604		T4	811
valid_sources[0x4c]	310601	1			T1	5		T2	2518		T4	767
valid_sources[0x4d]	268994	1			T1	8		T2	2769		T4	755
valid_sources[0x4e]	330150	1			T1	6		T2	2507		T4	841
valid_sources[0x4f]	253368	1			T1	11		T2	2599		T4	865
valid_sources[0x50]	319821	1			T1	4		T2	2498		T4	758
valid_sources[0x51]	282467	1			T1	9		T2	2656		T4	760
valid_sources[0x52]	266738	1			T1	2		T2	2673		T4	782
valid_sources[0x53]	267080	1			T1	5		T2	2773		T4	807
valid_sources[0x54]	288262	1			T1	6		T2	2640		T4	767
valid_sources[0x55]	275811	1			T1	2		T2	2721		T4	795
valid_sources[0x56]	263089	1			T1	3		T2	2754		T4	787
valid_sources[0x57]	308608	1			T1	4		T2	2663		T4	735
valid_sources[0x58]	258566	1			T1	9		T2	2727		T4	759
valid_sources[0x59]	287119	1			T1	5		T2	2572		T4	710
valid_sources[0x5a]	287460	1			T1	4		T2	2694		T4	824
valid_sources[0x5b]	289834	1			T1	6		T2	2864		T4	842
valid_sources[0x5c]	281243	1			T1	9		T2	2536		T4	716
valid_sources[0x5d]	329837	1			T1	6		T2	2608		T4	857
valid_sources[0x5e]	321598	1			T1	8		T2	2677		T4	858
valid_sources[0x5f]	284974	1			T1	6		T2	2752		T4	756
valid_sources[0x60]	342434	1			T1	9		T2	2788		T4	851
valid_sources[0x61]	262561	1			T1	10		T2	2526		T4	785
valid_sources[0x62]	296534	1			T1	7		T2	2683		T4	811
valid_sources[0x63]	253995	1			T1	3		T2	2559		T4	782
valid_sources[0x64]	399361	1			T1	5		T2	2463		T4	668
valid_sources[0x65]	256526	1			T1	5		T2	2685		T4	851
valid_sources[0x66]	304648	1			T1	3		T2	2587		T4	718
valid_sources[0x67]	270777	1			T1	9		T2	2658		T4	833
valid_sources[0x68]	328594	1			T1	8		T2	2716		T4	841
valid_sources[0x69]	353287	1			T1	16		T2	2581		T4	788
valid_sources[0x6a]	295617	1			T1	4		T2	2565		T4	759
valid_sources[0x6b]	277177	1			T1	10		T2	2757		T4	823
valid_sources[0x6c]	337514	1			T1	8		T2	2804		T4	807
valid_sources[0x6d]	320340	1			T1	5		T2	2687		T4	803
valid_sources[0x6e]	401839	1			T1	5		T2	2608		T4	759
valid_sources[0x6f]	269863	1			T1	7		T2	2594		T4	831
valid_sources[0x70]	272188	1			T1	7		T2	2620		T4	751
valid_sources[0x71]	308879	1			T1	6		T2	2792		T4	726
valid_sources[0x72]	278841	1			T1	3		T2	2459		T4	787
valid_sources[0x73]	315252	1			T1	5		T2	2620		T4	805
valid_sources[0x74]	311771	1			T1	5		T2	2631		T4	746
valid_sources[0x75]	275120	1			T1	4		T2	2468		T4	836
valid_sources[0x76]	306026	1			T1	8		T2	2570		T4	819
valid_sources[0x77]	295940	1			T1	7		T2	2607		T4	840
valid_sources[0x78]	291837	1			T1	6		T2	2477		T4	805
valid_sources[0x79]	272531	1			T1	14		T2	2587		T4	808
valid_sources[0x7a]	316418	1			T1	6		T2	2655		T4	818
valid_sources[0x7b]	271077	1			T1	10		T2	2621		T4	848
valid_sources[0x7c]	308568	1			T1	8		T2	2493		T4	754
valid_sources[0x7d]	262418	1			T1	10		T2	2478		T4	852
valid_sources[0x7e]	300649	1			T1	3		T2	2649		T4	794
valid_sources[0x7f]	265282	1			T1	10		T2	2834		T4	781
valid_sources[0x80]	282060	1			T1	4		T2	2666		T4	793

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

30406222

1

T1

171

T2

306546

T4

91723

values[0x0]

all_enables

biggest_size

15315254

1

T1

96

T2

153503

T4

45897

values[0x1]

all_enables

biggest_size

15320367

1

T1

90

T2

153389

T4

46001

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2249088	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

145816

1

T2

59

T4

3

T8

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2268053	1			T1	178		T2	8560		T3	153
values[0x0]	61614	1			T2	59		T3	1		T4	3
values[0x1]	65237	1			T1	1		T2	66		T4	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1501464	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

893440

1

T1

53

T2

2911

T3

49

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7509	1			T3	1		T4	9		T8	19
valid_sources[0x01]	7480	1			T3	1		T4	7		T8	13
valid_sources[0x02]	7904	1			T4	16		T8	21		T16	12
valid_sources[0x03]	9958	1			T3	1		T4	7		T8	8
valid_sources[0x04]	8908	1			T3	1		T4	13		T8	19
valid_sources[0x05]	7615	1			T3	1		T4	13		T8	11
valid_sources[0x06]	7415	1			T3	2		T4	14		T8	20
valid_sources[0x07]	7433	1			T4	11		T8	15		T16	32
valid_sources[0x08]	8323	1			T4	17		T8	17		T16	4
valid_sources[0x09]	12358	1			T4	12		T8	15		T16	30
valid_sources[0x0a]	9294	1			T1	179		T3	1		T4	13
valid_sources[0x0b]	7764	1			T4	10		T8	4		T15	1
valid_sources[0x0c]	7609	1			T4	19		T8	20		T16	13
valid_sources[0x0d]	13102	1			T4	13		T8	20		T16	4
valid_sources[0x0e]	6973	1			T4	17		T8	5		T16	3
valid_sources[0x0f]	7374	1			T3	1		T4	5		T8	25
valid_sources[0x10]	7583	1			T3	1		T4	16		T8	18
valid_sources[0x11]	12725	1			T4	13		T8	15		T16	26
valid_sources[0x12]	14471	1			T4	18		T8	9		T16	8
valid_sources[0x13]	7000	1			T4	5		T8	23		T16	14
valid_sources[0x14]	8031	1			T3	1		T4	7		T8	13
valid_sources[0x15]	8660	1			T3	1		T4	13		T8	15
valid_sources[0x16]	10001	1			T4	14		T8	18		T16	4
valid_sources[0x17]	8194	1			T4	11		T8	14		T15	1
valid_sources[0x18]	7713	1			T3	2		T4	22		T8	16
valid_sources[0x19]	8448	1			T3	2		T4	13		T8	21
valid_sources[0x1a]	21687	1			T3	3		T4	12		T8	8
valid_sources[0x1b]	7569	1			T4	11		T8	15		T16	11
valid_sources[0x1c]	8442	1			T4	22		T8	14		T16	7
valid_sources[0x1d]	7893	1			T4	17		T8	12		T16	16
valid_sources[0x1e]	8754	1			T3	1		T4	14		T8	24
valid_sources[0x1f]	15864	1			T3	1		T4	22		T8	19
valid_sources[0x20]	7485	1			T3	1		T4	7		T8	17
valid_sources[0x21]	7531	1			T3	1		T4	3		T8	10
valid_sources[0x22]	7134	1			T4	17		T8	8		T16	14
valid_sources[0x23]	9503	1			T4	16		T8	7		T17	22
valid_sources[0x24]	6919	1			T4	7		T8	18		T15	1
valid_sources[0x25]	7900	1			T4	12		T8	12		T16	10
valid_sources[0x26]	18151	1			T3	1		T4	11		T8	15
valid_sources[0x27]	8181	1			T3	1		T4	8		T8	16
valid_sources[0x28]	9498	1			T3	1		T4	10		T8	34
valid_sources[0x29]	7344	1			T4	15		T8	7		T16	4
valid_sources[0x2a]	7590	1			T4	6		T8	20		T16	23
valid_sources[0x2b]	7792	1			T3	2		T4	13		T8	10
valid_sources[0x2c]	7800	1			T4	22		T8	20		T16	13
valid_sources[0x2d]	11355	1			T4	7		T8	15		T16	28
valid_sources[0x2e]	7462	1			T4	26		T8	13		T16	1
valid_sources[0x2f]	7240	1			T3	1		T4	5		T8	14
valid_sources[0x30]	16163	1			T3	1		T4	16		T8	18
valid_sources[0x31]	8864	1			T4	11		T8	11		T15	1
valid_sources[0x32]	7648	1			T4	12		T8	12		T16	17
valid_sources[0x33]	7244	1			T3	1		T4	13		T8	14
valid_sources[0x34]	7098	1			T3	1		T4	13		T8	25
valid_sources[0x35]	7261	1			T4	11		T8	13		T15	5
valid_sources[0x36]	10608	1			T4	11		T8	11		T16	15
valid_sources[0x37]	8524	1			T4	8		T8	9		T16	19
valid_sources[0x38]	9094	1			T4	9		T8	13		T16	7
valid_sources[0x39]	10519	1			T3	1		T4	14		T8	4
valid_sources[0x3a]	7264	1			T3	1		T4	14		T8	10
valid_sources[0x3b]	7608	1			T4	14		T8	11		T15	1
valid_sources[0x3c]	7768	1			T4	9		T8	16		T15	2
valid_sources[0x3d]	7351	1			T4	10		T8	21		T16	2
valid_sources[0x3e]	10441	1			T4	6		T8	14		T16	15
valid_sources[0x3f]	7910	1			T3	2		T4	5		T8	9
valid_sources[0x40]	7663	1			T4	3		T8	21		T16	10
valid_sources[0x41]	15753	1			T4	26		T8	16		T16	6
valid_sources[0x42]	12313	1			T4	12		T8	11		T15	5
valid_sources[0x43]	7660	1			T4	3		T8	14		T16	15
valid_sources[0x44]	7742	1			T3	1		T4	18		T8	13
valid_sources[0x45]	6971	1			T4	22		T8	21		T16	22
valid_sources[0x46]	22557	1			T4	15		T8	14		T15	2
valid_sources[0x47]	8300	1			T4	16		T8	14		T16	9
valid_sources[0x48]	12767	1			T3	1		T4	14		T8	10
valid_sources[0x49]	10436	1			T3	1		T4	6		T8	10
valid_sources[0x4a]	7923	1			T3	1		T4	2		T8	12
valid_sources[0x4b]	8116	1			T3	2		T4	18		T8	19
valid_sources[0x4c]	8013	1			T4	6		T8	12		T16	5
valid_sources[0x4d]	16348	1			T3	2		T4	12		T8	22
valid_sources[0x4e]	7677	1			T3	1		T4	3		T8	18
valid_sources[0x4f]	12530	1			T4	16		T8	11		T16	5
valid_sources[0x50]	10690	1			T3	1		T4	11		T8	13
valid_sources[0x51]	7344	1			T4	8		T8	18		T16	8
valid_sources[0x52]	7553	1			T4	10		T8	26		T15	1
valid_sources[0x53]	7592	1			T4	9		T8	10		T16	16
valid_sources[0x54]	12363	1			T3	1		T4	21		T8	8
valid_sources[0x55]	7727	1			T4	8		T8	21		T15	1
valid_sources[0x56]	7436	1			T3	1		T4	5		T8	18
valid_sources[0x57]	7659	1			T3	1		T4	9		T8	17
valid_sources[0x58]	8636	1			T4	12		T8	14		T15	1
valid_sources[0x59]	13448	1			T3	4		T4	24		T8	27
valid_sources[0x5a]	7741	1			T4	14		T8	15		T15	2
valid_sources[0x5b]	7560	1			T4	5		T8	13		T15	2
valid_sources[0x5c]	7381	1			T4	11		T8	19		T16	20
valid_sources[0x5d]	7792	1			T4	12		T8	21		T16	10
valid_sources[0x5e]	6921	1			T4	6		T8	6		T15	4
valid_sources[0x5f]	7612	1			T3	2		T4	7		T8	19
valid_sources[0x60]	8171	1			T4	13		T8	5		T16	7
valid_sources[0x61]	7275	1			T4	15		T8	10		T16	3
valid_sources[0x62]	7168	1			T3	1		T4	14		T8	18
valid_sources[0x63]	8260	1			T4	6		T8	15		T16	31
valid_sources[0x64]	7847	1			T3	1		T4	19		T8	16
valid_sources[0x65]	7603	1			T3	1		T4	9		T8	17
valid_sources[0x66]	7933	1			T3	3		T4	11		T8	13
valid_sources[0x67]	7640	1			T3	3		T4	9		T8	22
valid_sources[0x68]	10196	1			T4	12		T8	13		T17	38
valid_sources[0x69]	15280	1			T4	13		T8	19		T16	29
valid_sources[0x6a]	8340	1			T4	14		T8	15		T16	17
valid_sources[0x6b]	11088	1			T4	8		T8	11		T15	1
valid_sources[0x6c]	10053	1			T4	2		T8	18		T15	1
valid_sources[0x6d]	8323	1			T4	15		T8	9		T16	25
valid_sources[0x6e]	13730	1			T4	11		T8	14		T16	2
valid_sources[0x6f]	10691	1			T4	12		T8	29		T15	1
valid_sources[0x70]	7415	1			T3	3		T4	8		T8	20
valid_sources[0x71]	22715	1			T4	11		T8	14		T15	3
valid_sources[0x72]	7318	1			T3	1		T4	14		T8	12
valid_sources[0x73]	7414	1			T3	2		T4	17		T8	12
valid_sources[0x74]	9067	1			T4	22		T8	7		T16	1
valid_sources[0x75]	7713	1			T4	21		T8	10		T15	5
valid_sources[0x76]	10977	1			T4	25		T8	28		T5	3832
valid_sources[0x77]	7907	1			T3	1		T4	16		T8	5
valid_sources[0x78]	8383	1			T4	17		T8	7		T16	10
valid_sources[0x79]	7426	1			T4	8		T8	16		T15	2
valid_sources[0x7a]	7797	1			T4	6		T8	18		T16	7
valid_sources[0x7b]	7467	1			T3	2		T4	8		T8	9
valid_sources[0x7c]	7504	1			T4	9		T8	14		T16	3
valid_sources[0x7d]	10561	1			T4	1		T8	12		T16	6
valid_sources[0x7e]	17403	1			T3	1		T4	18		T8	7
valid_sources[0x7f]	7384	1			T3	2		T4	13		T8	19
valid_sources[0x80]	10760	1			T4	6		T8	18		T16	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

39193

1

T2

23

T5

4

T13

758

values[0x0]

all_enables

biggest_size

54259

1

T2

24

T4

2

T8

3

values[0x1]

all_enables

biggest_size

52364

1

T2

12

T4

1

T5

1