Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14277666

1

T1

1561

T2

53424

T4

18453

full_word

55658052

1

T1

357

T2

531885

T4

183621

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	69935428	1			T1	1918		T2	585309		T4	202074
auto[TlIntgErrCmd]	103	1			T44	2		T45	3		T49	8
auto[TlIntgErrData]	93	1			T44	3		T45	5		T49	4
auto[TlIntgErrBoth]	94	1			T44	5		T45	2		T49	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31872877

1

T1

940

T2

249099

T4

100962

auto[1]

38062841

1

T1

978

T2

336210

T4

101112

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6803419	1			T1	769		T2	22558		T4	9239
auto[TlIntgErrNone]	partial	auto[1]	7473981	1			T1	792		T2	30866		T4	9214
auto[TlIntgErrNone]	full_word	auto[0]	25069322	1			T1	171		T2	226541		T4	91723
auto[TlIntgErrNone]	full_word	auto[1]	30588706	1			T1	186		T2	305344		T4	91898
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T44	1		T45	1		T49	3
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T44	1		T45	2		T49	5
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T112	1		T117	1		T118	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T112	2		T108	1		T113	2
auto[TlIntgErrData]	partial	auto[0]	38	1			T44	1		T45	4		T49	2
auto[TlIntgErrData]	partial	auto[1]	45	1			T44	2		T45	1		T49	1
auto[TlIntgErrData]	full_word	auto[0]	7	1			T49	1		T111	1		T113	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T61	1		T112	1		T114	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T44	3		T45	1		T49	1
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T44	2		T45	1		T49	7
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T119	1		T120	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T109	1		T118	1		T120	1