Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	590344	1			T1	117		T13	79		T14	1892
auto[1]	10354174	1			T1	125		T2	5408		T4	84457
auto[2]	493854	1			T1	120		T2	1		T13	64
auto[3]	10272140	1			T1	131		T2	5443		T4	84245

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14815718	1			T1	10		T2	7800		T4	140585
auto[1]	2001939	1			T1	53		T2	1448		T4	13431
auto[2]	1999902	1			T1	72		T2	1392		T4	13391
auto[3]	2892953	1			T1	358		T2	212		T4	1295

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9185734

1

T1

493

T2

10839

T4

37

auto[1]

12524778

1

T2

13

T4

168665

T8

46

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	230876	1			T1	3		T13	65		T14	1558
auto[0]	auto[0]	auto[1]	23201	1			T1	16		T13	5		T14	163
auto[0]	auto[0]	auto[2]	23321	1			T1	23		T13	8		T14	152
auto[0]	auto[0]	auto[3]	5972	1			T1	75		T14	16		T43	70
auto[0]	auto[1]	auto[0]	3556690	1			T1	2		T2	3888		T4	12
auto[0]	auto[1]	auto[1]	363283	1			T1	19		T2	1035		T4	6
auto[0]	auto[1]	auto[2]	356157	1			T1	9		T2	375		T4	2
auto[0]	auto[1]	auto[3]	66340	1			T1	95		T2	104		T4	1
auto[0]	auto[2]	auto[0]	201257	1			T1	3		T2	1		T13	57
auto[0]	auto[2]	auto[1]	20695	1			T1	11		T13	5		T14	170
auto[0]	auto[2]	auto[2]	19029	1			T1	21		T13	1		T14	113
auto[0]	auto[2]	auto[3]	4694	1			T1	85		T14	12		T43	55
auto[0]	auto[3]	auto[0]	3530681	1			T1	2		T2	3902		T4	12
auto[0]	auto[3]	auto[1]	353249	1			T1	7		T2	410		T4	2
auto[0]	auto[3]	auto[2]	360795	1			T1	19		T2	1016		T4	2
auto[0]	auto[3]	auto[3]	69494	1			T1	103		T2	108		T8	225
auto[1]	auto[0]	auto[0]	10438	1			T13	1		T14	2		T43	7
auto[1]	auto[0]	auto[1]	45732	1			T43	1		T26	1		T125	2
auto[1]	auto[0]	auto[2]	45729	1			T14	1		T43	1		T121	1
auto[1]	auto[0]	auto[3]	205075	1			T75	1		T76	1		T124	20455
auto[1]	auto[1]	auto[0]	3638587	1			T2	3		T4	70328		T8	21
auto[1]	auto[1]	auto[1]	600328	1			T2	3		T4	6408		T8	3
auto[1]	auto[1]	auto[2]	566251	1			T4	7061		T8	1		T16	8967
auto[1]	auto[1]	auto[3]	1206538	1			T4	639		T16	839		T18	84061
auto[1]	auto[2]	auto[0]	8436	1			T13	1		T43	5		T126	1
auto[1]	auto[2]	auto[1]	37373	1			T121	1		T26	1		T127	1
auto[1]	auto[2]	auto[2]	36877	1			T26	2		T124	3116		T128	1
auto[1]	auto[2]	auto[3]	165493	1			T124	13940		T129	10598		T130	12092
auto[1]	auto[3]	auto[0]	3638753	1			T2	6		T4	70233		T8	15
auto[1]	auto[3]	auto[1]	558078	1			T4	7015		T8	1		T16	8960
auto[1]	auto[3]	auto[2]	591743	1			T2	1		T4	6326		T8	5
auto[1]	auto[3]	auto[3]	1169347	1			T4	655		T16	859		T18	84418