Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.85	100.00	97.56	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	329313662	176428	0	0
ctrl_regwen_rd_A	329313662	11038	0	0
exec_rd_A	329313662	9986	0	0
exec_regwen_rd_A	329313662	10946	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329313662	176428	0	0
T13	122039	4122	0	0
T22	1219	0	0	0
T30	57496	2593	0	0
T31	0	1601	0	0
T32	1949	0	0	0
T44	0	2	0	0
T45	0	3	0	0
T46	0	270	0	0
T47	0	912	0	0
T48	0	73	0	0
T49	0	2	0	0
T50	0	808	0	0
T52	62497	0	0	0
T53	415976	0	0	0
T54	33840	0	0	0
T55	4353	0	0	0
T56	494408	0	0	0
T57	10260	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329313662	11038	0	0
T50	12016	0	0	0
T51	2089	0	0	0
T58	3602	0	0	0
T59	3085	0	0	0
T60	9168	31	0	0
T61	19266	30	0	0
T64	14572	415	0	0
T68	40305	83	0	0
T69	1078	0	0	0
T70	20608	0	0	0
T72	0	24	0	0
T84	0	50	0	0
T89	0	412	0	0
T102	0	15	0	0
T103	0	55	0	0
T104	0	39	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329313662	9986	0	0
T50	12016	0	0	0
T51	2089	0	0	0
T58	3602	0	0	0
T59	3085	0	0	0
T60	9168	3	0	0
T61	19266	42	0	0
T64	14572	437	0	0
T68	40305	53	0	0
T69	1078	0	0	0
T70	20608	0	0	0
T72	0	7	0	0
T84	0	42	0	0
T89	0	447	0	0
T102	0	8	0	0
T103	0	17	0	0
T104	0	26	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329313662	10946	0	0
T50	12016	0	0	0
T51	2089	0	0	0
T58	3602	0	0	0
T59	3085	0	0	0
T60	9168	21	0	0
T61	19266	60	0	0
T64	14572	483	0	0
T68	40305	64	0	0
T69	1078	0	0	0
T70	20608	0	0	0
T72	0	21	0	0
T89	0	492	0	0
T102	0	2	0	0
T103	0	71	0	0
T104	0	53	0	0
T105	0	1	0	0