| T267 |
/workspace/coverage/default/35.sram_ctrl_access_during_key_req.3500385542 |
|
|
Feb 04 03:14:57 PM PST 24 |
Feb 04 03:25:45 PM PST 24 |
2703261896 ps |
| T268 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.3988511049 |
|
|
Feb 04 03:18:13 PM PST 24 |
Feb 04 03:19:43 PM PST 24 |
902809475 ps |
| T269 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.4180558611 |
|
|
Feb 04 03:13:30 PM PST 24 |
Feb 04 03:13:34 PM PST 24 |
97753527 ps |
| T270 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.3800404310 |
|
|
Feb 04 03:17:06 PM PST 24 |
Feb 04 03:17:13 PM PST 24 |
98864133 ps |
| T271 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.225435601 |
|
|
Feb 04 03:13:52 PM PST 24 |
Feb 04 03:23:02 PM PST 24 |
8477417325 ps |
| T272 |
/workspace/coverage/default/32.sram_ctrl_lc_escalation.4022181854 |
|
|
Feb 04 03:14:05 PM PST 24 |
Feb 04 03:14:25 PM PST 24 |
571410419 ps |
| T273 |
/workspace/coverage/default/39.sram_ctrl_max_throughput.3817916657 |
|
|
Feb 04 03:16:23 PM PST 24 |
Feb 04 03:16:53 PM PST 24 |
98370045 ps |
| T274 |
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.2730346924 |
|
|
Feb 04 03:12:05 PM PST 24 |
Feb 04 03:43:05 PM PST 24 |
11762744314 ps |
| T275 |
/workspace/coverage/default/40.sram_ctrl_bijection.4189239219 |
|
|
Feb 04 03:16:24 PM PST 24 |
Feb 04 03:16:53 PM PST 24 |
2302990849 ps |
| T276 |
/workspace/coverage/default/12.sram_ctrl_ram_cfg.2935603776 |
|
|
Feb 04 03:07:12 PM PST 24 |
Feb 04 03:07:14 PM PST 24 |
131869289 ps |
| T277 |
/workspace/coverage/default/33.sram_ctrl_mem_walk.688931786 |
|
|
Feb 04 03:14:28 PM PST 24 |
Feb 04 03:14:39 PM PST 24 |
2569604767 ps |
| T278 |
/workspace/coverage/default/34.sram_ctrl_smoke.599222881 |
|
|
Feb 04 03:14:37 PM PST 24 |
Feb 04 03:14:46 PM PST 24 |
981103489 ps |
| T279 |
/workspace/coverage/default/31.sram_ctrl_smoke.4070476414 |
|
|
Feb 04 03:13:49 PM PST 24 |
Feb 04 03:13:53 PM PST 24 |
111244490 ps |
| T18 |
/workspace/coverage/default/1.sram_ctrl_sec_cm.3670059471 |
|
|
Feb 04 03:02:11 PM PST 24 |
Feb 04 03:02:17 PM PST 24 |
1562442373 ps |
| T34 |
/workspace/coverage/default/3.sram_ctrl_multiple_keys.273504582 |
|
|
Feb 04 03:02:47 PM PST 24 |
Feb 04 03:33:08 PM PST 24 |
97044217974 ps |
| T35 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.4135954934 |
|
|
Feb 04 03:07:57 PM PST 24 |
Feb 04 03:23:21 PM PST 24 |
4270186837 ps |
| T36 |
/workspace/coverage/default/40.sram_ctrl_multiple_keys.1412603961 |
|
|
Feb 04 03:16:28 PM PST 24 |
Feb 04 03:37:22 PM PST 24 |
18466696858 ps |
| T37 |
/workspace/coverage/default/44.sram_ctrl_stress_all.2666049615 |
|
|
Feb 04 03:18:00 PM PST 24 |
Feb 04 04:17:36 PM PST 24 |
72743604856 ps |
| T38 |
/workspace/coverage/default/30.sram_ctrl_partial_access.461896870 |
|
|
Feb 04 03:13:19 PM PST 24 |
Feb 04 03:13:29 PM PST 24 |
498170231 ps |
| T39 |
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.1207561508 |
|
|
Feb 04 03:09:55 PM PST 24 |
Feb 04 04:14:08 PM PST 24 |
716747528 ps |
| T40 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3395491598 |
|
|
Feb 04 03:00:54 PM PST 24 |
Feb 04 03:01:25 PM PST 24 |
180371109 ps |
| T280 |
/workspace/coverage/default/5.sram_ctrl_partial_access.3144376928 |
|
|
Feb 04 03:03:48 PM PST 24 |
Feb 04 03:04:47 PM PST 24 |
252857783 ps |
| T281 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.677413496 |
|
|
Feb 04 03:01:53 PM PST 24 |
Feb 04 03:01:56 PM PST 24 |
97373091 ps |
| T282 |
/workspace/coverage/default/0.sram_ctrl_smoke.687024129 |
|
|
Feb 04 03:00:44 PM PST 24 |
Feb 04 03:02:58 PM PST 24 |
1307489518 ps |
| T283 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.562157693 |
|
|
Feb 04 03:04:41 PM PST 24 |
Feb 04 03:05:03 PM PST 24 |
380066017 ps |
| T284 |
/workspace/coverage/default/17.sram_ctrl_ram_cfg.277782007 |
|
|
Feb 04 03:09:11 PM PST 24 |
Feb 04 03:09:14 PM PST 24 |
156281698 ps |
| T285 |
/workspace/coverage/default/7.sram_ctrl_partial_access.933004921 |
|
|
Feb 04 03:04:56 PM PST 24 |
Feb 04 03:06:01 PM PST 24 |
1887926163 ps |
| T286 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.3191283768 |
|
|
Feb 04 03:09:16 PM PST 24 |
Feb 04 03:12:17 PM PST 24 |
7450381659 ps |
| T287 |
/workspace/coverage/default/37.sram_ctrl_smoke.211099216 |
|
|
Feb 04 03:15:37 PM PST 24 |
Feb 04 03:16:22 PM PST 24 |
189506773 ps |
| T288 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.2450552035 |
|
|
Feb 04 03:08:10 PM PST 24 |
Feb 04 03:08:12 PM PST 24 |
27180243 ps |
| T289 |
/workspace/coverage/default/24.sram_ctrl_mem_walk.4011170504 |
|
|
Feb 04 03:11:44 PM PST 24 |
Feb 04 03:11:55 PM PST 24 |
1552884496 ps |
| T290 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.3191709949 |
|
|
Feb 04 03:11:56 PM PST 24 |
Feb 04 03:12:03 PM PST 24 |
291839130 ps |
| T291 |
/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.3597661672 |
|
|
Feb 04 03:14:16 PM PST 24 |
Feb 04 03:50:58 PM PST 24 |
1107882582 ps |
| T292 |
/workspace/coverage/default/4.sram_ctrl_stress_pipeline.3582380404 |
|
|
Feb 04 03:03:17 PM PST 24 |
Feb 04 03:09:03 PM PST 24 |
7056494658 ps |
| T293 |
/workspace/coverage/default/24.sram_ctrl_max_throughput.1806341836 |
|
|
Feb 04 03:11:42 PM PST 24 |
Feb 04 03:11:50 PM PST 24 |
47920448 ps |
| T294 |
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.1154914199 |
|
|
Feb 04 03:16:33 PM PST 24 |
Feb 04 03:20:42 PM PST 24 |
14957443881 ps |
| T295 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.1274670072 |
|
|
Feb 04 03:03:47 PM PST 24 |
Feb 04 03:03:53 PM PST 24 |
468082022 ps |
| T296 |
/workspace/coverage/default/9.sram_ctrl_partial_access.467301897 |
|
|
Feb 04 03:06:01 PM PST 24 |
Feb 04 03:06:25 PM PST 24 |
985573109 ps |
| T132 |
/workspace/coverage/default/15.sram_ctrl_stress_all.3399868122 |
|
|
Feb 04 03:08:29 PM PST 24 |
Feb 04 03:55:05 PM PST 24 |
25492889853 ps |
| T297 |
/workspace/coverage/default/44.sram_ctrl_max_throughput.2511504690 |
|
|
Feb 04 03:17:53 PM PST 24 |
Feb 04 03:19:00 PM PST 24 |
106638060 ps |
| T298 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2910032572 |
|
|
Feb 04 03:07:10 PM PST 24 |
Feb 04 04:14:02 PM PST 24 |
2968776616 ps |
| T299 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.3559614250 |
|
|
Feb 04 03:19:14 PM PST 24 |
Feb 04 03:22:06 PM PST 24 |
7332515262 ps |
| T300 |
/workspace/coverage/default/32.sram_ctrl_executable.1305502609 |
|
|
Feb 04 03:14:05 PM PST 24 |
Feb 04 03:36:50 PM PST 24 |
8004744761 ps |
| T301 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.793310136 |
|
|
Feb 04 03:18:56 PM PST 24 |
Feb 04 03:23:32 PM PST 24 |
31378669033 ps |
| T302 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.1647904204 |
|
|
Feb 04 03:12:14 PM PST 24 |
Feb 04 03:14:57 PM PST 24 |
5237857151 ps |
| T303 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.534765465 |
|
|
Feb 04 03:19:34 PM PST 24 |
Feb 04 03:19:44 PM PST 24 |
539446396 ps |
| T304 |
/workspace/coverage/default/0.sram_ctrl_executable.3799542551 |
|
|
Feb 04 03:01:27 PM PST 24 |
Feb 04 03:22:41 PM PST 24 |
13002007371 ps |
| T305 |
/workspace/coverage/default/2.sram_ctrl_lc_escalation.3514188553 |
|
|
Feb 04 03:02:21 PM PST 24 |
Feb 04 03:02:30 PM PST 24 |
2998233273 ps |
| T306 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.539248932 |
|
|
Feb 04 03:06:12 PM PST 24 |
Feb 04 03:06:23 PM PST 24 |
2555793056 ps |
| T307 |
/workspace/coverage/default/28.sram_ctrl_multiple_keys.3802848954 |
|
|
Feb 04 03:12:35 PM PST 24 |
Feb 04 03:21:05 PM PST 24 |
9818818908 ps |
| T308 |
/workspace/coverage/default/48.sram_ctrl_regwen.2895633114 |
|
|
Feb 04 03:19:02 PM PST 24 |
Feb 04 03:19:48 PM PST 24 |
702335097 ps |
| T309 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.3902970759 |
|
|
Feb 04 03:17:26 PM PST 24 |
Feb 04 03:17:43 PM PST 24 |
71708665 ps |
| T310 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.2745983543 |
|
|
Feb 04 03:12:23 PM PST 24 |
Feb 04 03:12:27 PM PST 24 |
88229015 ps |
| T311 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.2978644855 |
|
|
Feb 04 03:10:47 PM PST 24 |
Feb 04 03:11:51 PM PST 24 |
211976743 ps |
| T312 |
/workspace/coverage/default/0.sram_ctrl_mem_walk.1890897208 |
|
|
Feb 04 03:01:21 PM PST 24 |
Feb 04 03:01:27 PM PST 24 |
349239732 ps |
| T313 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.2255082324 |
|
|
Feb 04 03:16:34 PM PST 24 |
Feb 04 03:16:59 PM PST 24 |
421177880 ps |
| T314 |
/workspace/coverage/default/48.sram_ctrl_executable.3521737225 |
|
|
Feb 04 03:19:02 PM PST 24 |
Feb 04 04:01:27 PM PST 24 |
22809915234 ps |
| T315 |
/workspace/coverage/default/32.sram_ctrl_bijection.4177623727 |
|
|
Feb 04 03:14:08 PM PST 24 |
Feb 04 03:14:56 PM PST 24 |
875555240 ps |
| T316 |
/workspace/coverage/default/22.sram_ctrl_alert_test.2310426122 |
|
|
Feb 04 03:11:19 PM PST 24 |
Feb 04 03:11:22 PM PST 24 |
16613610 ps |
| T19 |
/workspace/coverage/default/0.sram_ctrl_sec_cm.4073705636 |
|
|
Feb 04 03:01:27 PM PST 24 |
Feb 04 03:01:31 PM PST 24 |
492443941 ps |
| T41 |
/workspace/coverage/default/19.sram_ctrl_lc_escalation.3164393560 |
|
|
Feb 04 03:09:54 PM PST 24 |
Feb 04 03:09:59 PM PST 24 |
615090367 ps |
| T317 |
/workspace/coverage/default/42.sram_ctrl_stress_all.355485488 |
|
|
Feb 04 03:17:13 PM PST 24 |
Feb 04 03:40:12 PM PST 24 |
18232308454 ps |
| T318 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.2139731568 |
|
|
Feb 04 03:00:51 PM PST 24 |
Feb 04 03:04:53 PM PST 24 |
2518973896 ps |
| T319 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.910736190 |
|
|
Feb 04 03:09:27 PM PST 24 |
Feb 04 03:09:29 PM PST 24 |
96678068 ps |
| T320 |
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.2429335014 |
|
|
Feb 04 03:11:41 PM PST 24 |
Feb 04 03:13:00 PM PST 24 |
1761951771 ps |
| T321 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.4140278991 |
|
|
Feb 04 03:10:38 PM PST 24 |
Feb 04 03:10:45 PM PST 24 |
90196008 ps |
| T322 |
/workspace/coverage/default/44.sram_ctrl_partial_access.4294522375 |
|
|
Feb 04 03:18:00 PM PST 24 |
Feb 04 03:18:02 PM PST 24 |
269723521 ps |
| T323 |
/workspace/coverage/default/30.sram_ctrl_bijection.519513015 |
|
|
Feb 04 03:13:19 PM PST 24 |
Feb 04 03:13:42 PM PST 24 |
2205783360 ps |
| T324 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.1118542471 |
|
|
Feb 04 03:04:40 PM PST 24 |
Feb 04 03:04:45 PM PST 24 |
55588273 ps |
| T325 |
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.2189424896 |
|
|
Feb 04 03:15:40 PM PST 24 |
Feb 04 03:15:43 PM PST 24 |
49200124 ps |
| T326 |
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.1708987301 |
|
|
Feb 04 03:19:02 PM PST 24 |
Feb 04 03:39:29 PM PST 24 |
8310703675 ps |
| T137 |
/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.2772278766 |
|
|
Feb 04 03:13:08 PM PST 24 |
Feb 04 03:18:41 PM PST 24 |
51671244333 ps |
| T327 |
/workspace/coverage/default/15.sram_ctrl_ram_cfg.3065794542 |
|
|
Feb 04 03:08:22 PM PST 24 |
Feb 04 03:08:23 PM PST 24 |
28565137 ps |
| T328 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.2915705590 |
|
|
Feb 04 03:08:50 PM PST 24 |
Feb 04 03:22:20 PM PST 24 |
5602398978 ps |
| T329 |
/workspace/coverage/default/26.sram_ctrl_smoke.649638658 |
|
|
Feb 04 03:12:05 PM PST 24 |
Feb 04 03:15:11 PM PST 24 |
2861024892 ps |
| T330 |
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.2024299597 |
|
|
Feb 04 03:10:53 PM PST 24 |
Feb 04 03:11:44 PM PST 24 |
455344930 ps |
| T331 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.403285047 |
|
|
Feb 04 03:09:54 PM PST 24 |
Feb 04 03:33:37 PM PST 24 |
26489056318 ps |
| T332 |
/workspace/coverage/default/20.sram_ctrl_lc_escalation.478382728 |
|
|
Feb 04 03:10:14 PM PST 24 |
Feb 04 03:10:30 PM PST 24 |
2257507143 ps |
| T333 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2066278147 |
|
|
Feb 04 03:06:55 PM PST 24 |
Feb 04 03:29:22 PM PST 24 |
221215290 ps |
| T334 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.1770647629 |
|
|
Feb 04 03:04:46 PM PST 24 |
Feb 04 03:04:51 PM PST 24 |
195956579 ps |
| T335 |
/workspace/coverage/default/37.sram_ctrl_stress_all.1560549681 |
|
|
Feb 04 03:15:32 PM PST 24 |
Feb 04 04:14:54 PM PST 24 |
87265490522 ps |
| T336 |
/workspace/coverage/default/30.sram_ctrl_lc_escalation.840211429 |
|
|
Feb 04 03:13:19 PM PST 24 |
Feb 04 03:13:29 PM PST 24 |
603471815 ps |
| T337 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.103372656 |
|
|
Feb 04 03:19:02 PM PST 24 |
Feb 04 03:19:05 PM PST 24 |
86162857 ps |
| T338 |
/workspace/coverage/default/35.sram_ctrl_bijection.2910215150 |
|
|
Feb 04 03:14:59 PM PST 24 |
Feb 04 03:15:47 PM PST 24 |
772976339 ps |
| T339 |
/workspace/coverage/default/31.sram_ctrl_executable.2890256678 |
|
|
Feb 04 03:13:53 PM PST 24 |
Feb 04 03:31:10 PM PST 24 |
20990061930 ps |
| T340 |
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1209820299 |
|
|
Feb 04 03:04:49 PM PST 24 |
Feb 04 04:07:52 PM PST 24 |
4387627295 ps |
| T341 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.1406670871 |
|
|
Feb 04 03:07:56 PM PST 24 |
Feb 04 03:08:07 PM PST 24 |
229544782 ps |
| T342 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.1192127281 |
|
|
Feb 04 03:05:26 PM PST 24 |
Feb 04 03:05:31 PM PST 24 |
74485700 ps |
| T343 |
/workspace/coverage/default/21.sram_ctrl_regwen.2102484468 |
|
|
Feb 04 03:10:40 PM PST 24 |
Feb 04 03:14:59 PM PST 24 |
747398562 ps |
| T344 |
/workspace/coverage/default/6.sram_ctrl_stress_all.2014372446 |
|
|
Feb 04 03:04:48 PM PST 24 |
Feb 04 04:28:13 PM PST 24 |
237598142410 ps |
| T345 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.597823557 |
|
|
Feb 04 03:08:42 PM PST 24 |
Feb 04 03:08:55 PM PST 24 |
519671487 ps |
| T346 |
/workspace/coverage/default/37.sram_ctrl_executable.4095826063 |
|
|
Feb 04 03:15:50 PM PST 24 |
Feb 04 03:28:34 PM PST 24 |
13239505846 ps |
| T347 |
/workspace/coverage/default/3.sram_ctrl_mem_walk.4097919310 |
|
|
Feb 04 03:03:09 PM PST 24 |
Feb 04 03:03:17 PM PST 24 |
830184455 ps |
| T348 |
/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.2648088909 |
|
|
Feb 04 03:15:18 PM PST 24 |
Feb 04 03:17:19 PM PST 24 |
161705878 ps |
| T349 |
/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.1018048891 |
|
|
Feb 04 03:09:13 PM PST 24 |
Feb 04 03:15:29 PM PST 24 |
11231520184 ps |
| T350 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.1014073938 |
|
|
Feb 04 03:00:58 PM PST 24 |
Feb 04 03:01:12 PM PST 24 |
397617944 ps |
| T351 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.2316059951 |
|
|
Feb 04 03:15:41 PM PST 24 |
Feb 04 03:15:57 PM PST 24 |
258209001 ps |
| T352 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.218744799 |
|
|
Feb 04 03:01:26 PM PST 24 |
Feb 04 03:22:19 PM PST 24 |
1129499027 ps |
| T353 |
/workspace/coverage/default/26.sram_ctrl_partial_access.841720297 |
|
|
Feb 04 03:12:12 PM PST 24 |
Feb 04 03:12:26 PM PST 24 |
845903242 ps |
| T354 |
/workspace/coverage/default/27.sram_ctrl_ram_cfg.1303927215 |
|
|
Feb 04 03:12:34 PM PST 24 |
Feb 04 03:12:40 PM PST 24 |
97015751 ps |
| T355 |
/workspace/coverage/default/34.sram_ctrl_access_during_key_req.1379744348 |
|
|
Feb 04 03:14:48 PM PST 24 |
Feb 04 03:25:22 PM PST 24 |
4053234707 ps |
| T356 |
/workspace/coverage/default/39.sram_ctrl_bijection.518282444 |
|
|
Feb 04 03:16:13 PM PST 24 |
Feb 04 03:16:59 PM PST 24 |
2699242695 ps |
| T357 |
/workspace/coverage/default/27.sram_ctrl_alert_test.3452156698 |
|
|
Feb 04 03:12:34 PM PST 24 |
Feb 04 03:12:40 PM PST 24 |
11385926 ps |
| T358 |
/workspace/coverage/default/29.sram_ctrl_partial_access.114606276 |
|
|
Feb 04 03:13:09 PM PST 24 |
Feb 04 03:13:53 PM PST 24 |
748994152 ps |
| T359 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.314732979 |
|
|
Feb 04 03:06:42 PM PST 24 |
Feb 04 03:11:03 PM PST 24 |
11019102344 ps |
| T360 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.3005238986 |
|
|
Feb 04 03:14:49 PM PST 24 |
Feb 04 03:14:55 PM PST 24 |
148055045 ps |
| T361 |
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.2968220778 |
|
|
Feb 04 03:17:53 PM PST 24 |
Feb 04 03:33:56 PM PST 24 |
19980499334 ps |
| T362 |
/workspace/coverage/default/1.sram_ctrl_max_throughput.1192416767 |
|
|
Feb 04 03:01:38 PM PST 24 |
Feb 04 03:01:48 PM PST 24 |
229994874 ps |
| T363 |
/workspace/coverage/default/18.sram_ctrl_smoke.2620981417 |
|
|
Feb 04 03:09:14 PM PST 24 |
Feb 04 03:11:07 PM PST 24 |
133794801 ps |
| T364 |
/workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.2181098179 |
|
|
Feb 04 03:14:37 PM PST 24 |
Feb 04 03:15:36 PM PST 24 |
251579890 ps |
| T365 |
/workspace/coverage/default/41.sram_ctrl_stress_all.556862455 |
|
|
Feb 04 03:16:49 PM PST 24 |
Feb 04 04:03:30 PM PST 24 |
159841631177 ps |
| T366 |
/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.3166519009 |
|
|
Feb 04 03:14:02 PM PST 24 |
Feb 04 03:14:15 PM PST 24 |
224730316 ps |
| T367 |
/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.3873667215 |
|
|
Feb 04 03:14:57 PM PST 24 |
Feb 04 04:39:18 PM PST 24 |
697439561 ps |
| T368 |
/workspace/coverage/default/26.sram_ctrl_lc_escalation.3595964213 |
|
|
Feb 04 03:12:14 PM PST 24 |
Feb 04 03:12:23 PM PST 24 |
1533760446 ps |
| T369 |
/workspace/coverage/default/38.sram_ctrl_partial_access.2697858071 |
|
|
Feb 04 03:15:48 PM PST 24 |
Feb 04 03:16:11 PM PST 24 |
120227495 ps |
| T138 |
/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.2011690091 |
|
|
Feb 04 03:03:02 PM PST 24 |
Feb 04 03:06:47 PM PST 24 |
42628839037 ps |
| T370 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.348471284 |
|
|
Feb 04 03:07:07 PM PST 24 |
Feb 04 03:12:09 PM PST 24 |
6515200029 ps |
| T371 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.1456732501 |
|
|
Feb 04 03:03:10 PM PST 24 |
Feb 04 03:03:17 PM PST 24 |
64062734 ps |
| T372 |
/workspace/coverage/default/23.sram_ctrl_multiple_keys.4180128960 |
|
|
Feb 04 03:11:11 PM PST 24 |
Feb 04 03:22:15 PM PST 24 |
16611183382 ps |
| T373 |
/workspace/coverage/default/23.sram_ctrl_regwen.255237949 |
|
|
Feb 04 03:11:24 PM PST 24 |
Feb 04 03:20:34 PM PST 24 |
1431638929 ps |
| T374 |
/workspace/coverage/default/19.sram_ctrl_stress_all.654423135 |
|
|
Feb 04 03:09:54 PM PST 24 |
Feb 04 03:42:41 PM PST 24 |
7649252304 ps |
| T375 |
/workspace/coverage/default/26.sram_ctrl_mem_partial_access.2976139618 |
|
|
Feb 04 03:12:22 PM PST 24 |
Feb 04 03:12:27 PM PST 24 |
43733967 ps |
| T376 |
/workspace/coverage/default/31.sram_ctrl_lc_escalation.4123744430 |
|
|
Feb 04 03:13:52 PM PST 24 |
Feb 04 03:14:02 PM PST 24 |
2319530656 ps |
| T377 |
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.1046785201 |
|
|
Feb 04 03:10:31 PM PST 24 |
Feb 04 03:16:02 PM PST 24 |
6829212818 ps |
| T378 |
/workspace/coverage/default/47.sram_ctrl_alert_test.3251752617 |
|
|
Feb 04 03:18:54 PM PST 24 |
Feb 04 03:18:56 PM PST 24 |
37766804 ps |
| T379 |
/workspace/coverage/default/42.sram_ctrl_ram_cfg.3001998753 |
|
|
Feb 04 03:17:09 PM PST 24 |
Feb 04 03:17:16 PM PST 24 |
44534855 ps |
| T380 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.3540450080 |
|
|
Feb 04 03:09:59 PM PST 24 |
Feb 04 03:13:21 PM PST 24 |
22546526774 ps |
| T381 |
/workspace/coverage/default/32.sram_ctrl_max_throughput.2812224504 |
|
|
Feb 04 03:14:04 PM PST 24 |
Feb 04 03:16:50 PM PST 24 |
138515326 ps |
| T382 |
/workspace/coverage/default/38.sram_ctrl_bijection.3632853416 |
|
|
Feb 04 03:15:41 PM PST 24 |
Feb 04 03:16:06 PM PST 24 |
619022874 ps |
| T383 |
/workspace/coverage/default/29.sram_ctrl_executable.1221041971 |
|
|
Feb 04 03:13:10 PM PST 24 |
Feb 04 03:32:00 PM PST 24 |
35297891732 ps |
| T384 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.1656331653 |
|
|
Feb 04 03:11:42 PM PST 24 |
Feb 04 03:11:46 PM PST 24 |
69218647 ps |
| T385 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.611735969 |
|
|
Feb 04 03:18:41 PM PST 24 |
Feb 04 03:20:10 PM PST 24 |
260021645 ps |
| T386 |
/workspace/coverage/default/42.sram_ctrl_lc_escalation.1416328352 |
|
|
Feb 04 03:17:05 PM PST 24 |
Feb 04 03:17:11 PM PST 24 |
974991939 ps |
| T387 |
/workspace/coverage/default/41.sram_ctrl_stress_pipeline.3154844512 |
|
|
Feb 04 03:16:36 PM PST 24 |
Feb 04 03:20:07 PM PST 24 |
8854391589 ps |
| T388 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.614051176 |
|
|
Feb 04 03:12:24 PM PST 24 |
Feb 04 03:12:35 PM PST 24 |
2588627137 ps |
| T389 |
/workspace/coverage/default/29.sram_ctrl_ram_cfg.3076976570 |
|
|
Feb 04 03:13:11 PM PST 24 |
Feb 04 03:13:12 PM PST 24 |
71045279 ps |
| T390 |
/workspace/coverage/default/35.sram_ctrl_executable.458213456 |
|
|
Feb 04 03:15:00 PM PST 24 |
Feb 04 03:34:25 PM PST 24 |
16191287124 ps |
| T391 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.1868240530 |
|
|
Feb 04 03:10:00 PM PST 24 |
Feb 04 03:13:58 PM PST 24 |
40879599555 ps |
| T392 |
/workspace/coverage/default/13.sram_ctrl_stress_all.1739545943 |
|
|
Feb 04 03:07:31 PM PST 24 |
Feb 04 04:28:22 PM PST 24 |
89238427476 ps |
| T393 |
/workspace/coverage/default/37.sram_ctrl_partial_access.2228672265 |
|
|
Feb 04 03:15:32 PM PST 24 |
Feb 04 03:17:03 PM PST 24 |
480317817 ps |
| T394 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.2793234623 |
|
|
Feb 04 03:07:06 PM PST 24 |
Feb 04 03:09:30 PM PST 24 |
133077336 ps |
| T395 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.1377299751 |
|
|
Feb 04 03:10:20 PM PST 24 |
Feb 04 03:16:54 PM PST 24 |
1571515996 ps |
| T396 |
/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.2807271947 |
|
|
Feb 04 03:11:28 PM PST 24 |
Feb 04 03:11:56 PM PST 24 |
485015843 ps |
| T397 |
/workspace/coverage/default/29.sram_ctrl_alert_test.4133205713 |
|
|
Feb 04 03:13:30 PM PST 24 |
Feb 04 03:13:31 PM PST 24 |
11767236 ps |
| T398 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2735371300 |
|
|
Feb 04 03:04:02 PM PST 24 |
Feb 04 03:41:42 PM PST 24 |
360807171 ps |
| T399 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.3241475829 |
|
|
Feb 04 03:16:34 PM PST 24 |
Feb 04 03:25:57 PM PST 24 |
15298025600 ps |
| T400 |
/workspace/coverage/default/36.sram_ctrl_alert_test.3115788321 |
|
|
Feb 04 03:15:37 PM PST 24 |
Feb 04 03:15:39 PM PST 24 |
45516741 ps |
| T401 |
/workspace/coverage/default/16.sram_ctrl_mem_walk.1347381284 |
|
|
Feb 04 03:08:49 PM PST 24 |
Feb 04 03:08:55 PM PST 24 |
75314218 ps |
| T402 |
/workspace/coverage/default/18.sram_ctrl_lc_escalation.3784435712 |
|
|
Feb 04 03:09:13 PM PST 24 |
Feb 04 03:09:22 PM PST 24 |
583726746 ps |
| T403 |
/workspace/coverage/default/26.sram_ctrl_multiple_keys.404908408 |
|
|
Feb 04 03:12:04 PM PST 24 |
Feb 04 03:12:38 PM PST 24 |
6703433675 ps |
| T404 |
/workspace/coverage/default/32.sram_ctrl_mem_partial_access.54332538 |
|
|
Feb 04 03:14:05 PM PST 24 |
Feb 04 03:14:11 PM PST 24 |
163874081 ps |
| T405 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.148611750 |
|
|
Feb 04 03:18:01 PM PST 24 |
Feb 04 03:18:06 PM PST 24 |
46325753 ps |
| T406 |
/workspace/coverage/default/36.sram_ctrl_regwen.4111666714 |
|
|
Feb 04 03:15:38 PM PST 24 |
Feb 04 03:22:42 PM PST 24 |
2140750295 ps |
| T407 |
/workspace/coverage/default/41.sram_ctrl_regwen.4112286991 |
|
|
Feb 04 03:16:55 PM PST 24 |
Feb 04 03:32:07 PM PST 24 |
38514117632 ps |
| T408 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.1998086154 |
|
|
Feb 04 03:10:47 PM PST 24 |
Feb 04 03:15:53 PM PST 24 |
42260533678 ps |
| T409 |
/workspace/coverage/default/46.sram_ctrl_stress_all.3592327455 |
|
|
Feb 04 03:18:29 PM PST 24 |
Feb 04 03:55:11 PM PST 24 |
51687016431 ps |
| T410 |
/workspace/coverage/default/42.sram_ctrl_mem_walk.3318044429 |
|
|
Feb 04 03:17:13 PM PST 24 |
Feb 04 03:17:20 PM PST 24 |
348360188 ps |
| T411 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.1576251970 |
|
|
Feb 04 03:07:11 PM PST 24 |
Feb 04 03:07:13 PM PST 24 |
218116186 ps |
| T412 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.133361617 |
|
|
Feb 04 03:06:21 PM PST 24 |
Feb 04 03:07:11 PM PST 24 |
104395556 ps |
| T413 |
/workspace/coverage/default/34.sram_ctrl_partial_access.1337176129 |
|
|
Feb 04 03:14:38 PM PST 24 |
Feb 04 03:14:47 PM PST 24 |
6940566722 ps |
| T414 |
/workspace/coverage/default/39.sram_ctrl_lc_escalation.2044401140 |
|
|
Feb 04 03:16:14 PM PST 24 |
Feb 04 03:16:20 PM PST 24 |
189495097 ps |
| T415 |
/workspace/coverage/default/48.sram_ctrl_bijection.2349167056 |
|
|
Feb 04 03:18:55 PM PST 24 |
Feb 04 03:19:45 PM PST 24 |
818199984 ps |
| T416 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.3176592698 |
|
|
Feb 04 03:08:55 PM PST 24 |
Feb 04 03:34:15 PM PST 24 |
15754937431 ps |
| T417 |
/workspace/coverage/default/20.sram_ctrl_regwen.3689398038 |
|
|
Feb 04 03:10:15 PM PST 24 |
Feb 04 03:10:50 PM PST 24 |
1700580303 ps |
| T418 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.1026572326 |
|
|
Feb 04 03:04:34 PM PST 24 |
Feb 04 03:07:40 PM PST 24 |
1941396712 ps |
| T419 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.493365759 |
|
|
Feb 04 03:19:02 PM PST 24 |
Feb 04 03:26:27 PM PST 24 |
16115845236 ps |
| T420 |
/workspace/coverage/default/1.sram_ctrl_executable.1755793134 |
|
|
Feb 04 03:01:38 PM PST 24 |
Feb 04 03:27:21 PM PST 24 |
76706042231 ps |
| T421 |
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.2837687726 |
|
|
Feb 04 03:01:38 PM PST 24 |
Feb 04 03:09:23 PM PST 24 |
1683426064 ps |
| T422 |
/workspace/coverage/default/44.sram_ctrl_alert_test.3811003217 |
|
|
Feb 04 03:17:56 PM PST 24 |
Feb 04 03:17:57 PM PST 24 |
13385602 ps |
| T423 |
/workspace/coverage/default/22.sram_ctrl_executable.1813379494 |
|
|
Feb 04 03:10:47 PM PST 24 |
Feb 04 03:17:07 PM PST 24 |
8417251573 ps |
| T424 |
/workspace/coverage/default/12.sram_ctrl_partial_access.801687270 |
|
|
Feb 04 03:07:05 PM PST 24 |
Feb 04 03:07:27 PM PST 24 |
319527470 ps |
| T425 |
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.289101693 |
|
|
Feb 04 03:07:04 PM PST 24 |
Feb 04 03:07:12 PM PST 24 |
759372517 ps |
| T426 |
/workspace/coverage/default/40.sram_ctrl_lc_escalation.3742316009 |
|
|
Feb 04 03:16:24 PM PST 24 |
Feb 04 03:16:36 PM PST 24 |
1911604033 ps |
| T427 |
/workspace/coverage/default/45.sram_ctrl_executable.4061708011 |
|
|
Feb 04 03:18:01 PM PST 24 |
Feb 04 03:26:31 PM PST 24 |
5357988493 ps |
| T428 |
/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1247446771 |
|
|
Feb 04 03:09:29 PM PST 24 |
Feb 04 03:38:08 PM PST 24 |
614120177 ps |
| T429 |
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.1079736017 |
|
|
Feb 04 03:17:21 PM PST 24 |
Feb 04 03:40:04 PM PST 24 |
12988647208 ps |
| T430 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.657083573 |
|
|
Feb 04 03:08:11 PM PST 24 |
Feb 04 03:25:08 PM PST 24 |
6846304341 ps |
| T431 |
/workspace/coverage/default/15.sram_ctrl_alert_test.2475568671 |
|
|
Feb 04 03:08:30 PM PST 24 |
Feb 04 03:08:33 PM PST 24 |
38869479 ps |
| T432 |
/workspace/coverage/default/35.sram_ctrl_regwen.27237744 |
|
|
Feb 04 03:15:02 PM PST 24 |
Feb 04 03:28:47 PM PST 24 |
12073377414 ps |
| T433 |
/workspace/coverage/default/12.sram_ctrl_regwen.2835149610 |
|
|
Feb 04 03:07:11 PM PST 24 |
Feb 04 03:22:45 PM PST 24 |
13989534532 ps |
| T434 |
/workspace/coverage/default/17.sram_ctrl_mem_walk.236734767 |
|
|
Feb 04 03:09:10 PM PST 24 |
Feb 04 03:09:16 PM PST 24 |
144344695 ps |
| T435 |
/workspace/coverage/default/2.sram_ctrl_executable.2544149903 |
|
|
Feb 04 03:02:19 PM PST 24 |
Feb 04 03:22:21 PM PST 24 |
14663283092 ps |
| T436 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.1698732916 |
|
|
Feb 04 03:10:12 PM PST 24 |
Feb 04 03:10:13 PM PST 24 |
84219882 ps |
| T437 |
/workspace/coverage/default/34.sram_ctrl_executable.4274514203 |
|
|
Feb 04 03:14:47 PM PST 24 |
Feb 04 03:15:39 PM PST 24 |
283070930 ps |
| T438 |
/workspace/coverage/default/27.sram_ctrl_stress_all.2778412746 |
|
|
Feb 04 03:12:35 PM PST 24 |
Feb 04 04:54:10 PM PST 24 |
199331477163 ps |
| T439 |
/workspace/coverage/default/1.sram_ctrl_partial_access.1839348578 |
|
|
Feb 04 03:01:31 PM PST 24 |
Feb 04 03:02:48 PM PST 24 |
6953842580 ps |
| T440 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.2857699096 |
|
|
Feb 04 03:16:25 PM PST 24 |
Feb 04 03:16:31 PM PST 24 |
336729654 ps |
| T441 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.1195316746 |
|
|
Feb 04 03:07:49 PM PST 24 |
Feb 04 03:15:51 PM PST 24 |
21270075404 ps |
| T442 |
/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.1061393307 |
|
|
Feb 04 03:12:02 PM PST 24 |
Feb 04 03:20:22 PM PST 24 |
42663456670 ps |
| T443 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.935023295 |
|
|
Feb 04 03:13:09 PM PST 24 |
Feb 04 03:13:20 PM PST 24 |
438423212 ps |
| T444 |
/workspace/coverage/default/48.sram_ctrl_partial_access.436554543 |
|
|
Feb 04 03:18:53 PM PST 24 |
Feb 04 03:18:57 PM PST 24 |
78719537 ps |
| T445 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.2532451005 |
|
|
Feb 04 03:16:21 PM PST 24 |
Feb 04 03:16:27 PM PST 24 |
226892304 ps |
| T446 |
/workspace/coverage/default/33.sram_ctrl_max_throughput.3798405058 |
|
|
Feb 04 03:14:18 PM PST 24 |
Feb 04 03:14:22 PM PST 24 |
115531307 ps |
| T447 |
/workspace/coverage/default/19.sram_ctrl_regwen.4064843038 |
|
|
Feb 04 03:09:53 PM PST 24 |
Feb 04 03:36:05 PM PST 24 |
17556960851 ps |
| T448 |
/workspace/coverage/default/23.sram_ctrl_mem_walk.1519617041 |
|
|
Feb 04 03:11:25 PM PST 24 |
Feb 04 03:11:34 PM PST 24 |
238360132 ps |
| T449 |
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.2436156514 |
|
|
Feb 04 03:18:03 PM PST 24 |
Feb 04 03:21:23 PM PST 24 |
997322008 ps |
| T450 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.16753828 |
|
|
Feb 04 03:18:13 PM PST 24 |
Feb 04 03:23:01 PM PST 24 |
96111522910 ps |
| T451 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.152538061 |
|
|
Feb 04 03:10:00 PM PST 24 |
Feb 04 03:11:52 PM PST 24 |
878848136 ps |
| T452 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.241662816 |
|
|
Feb 04 03:12:23 PM PST 24 |
Feb 04 03:17:10 PM PST 24 |
2667531677 ps |
| T453 |
/workspace/coverage/default/41.sram_ctrl_bijection.434670411 |
|
|
Feb 04 03:16:36 PM PST 24 |
Feb 04 03:17:49 PM PST 24 |
20950292764 ps |
| T454 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.494097023 |
|
|
Feb 04 03:17:32 PM PST 24 |
Feb 04 03:17:38 PM PST 24 |
550265603 ps |
| T455 |
/workspace/coverage/default/24.sram_ctrl_stress_all.3454028787 |
|
|
Feb 04 03:11:42 PM PST 24 |
Feb 04 04:03:07 PM PST 24 |
160887260702 ps |
| T456 |
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.1808634357 |
|
|
Feb 04 03:06:23 PM PST 24 |
Feb 04 03:22:57 PM PST 24 |
2641142215 ps |
| T457 |
/workspace/coverage/default/23.sram_ctrl_smoke.3495312689 |
|
|
Feb 04 03:11:12 PM PST 24 |
Feb 04 03:11:22 PM PST 24 |
2280912384 ps |
| T458 |
/workspace/coverage/default/22.sram_ctrl_multiple_keys.874288414 |
|
|
Feb 04 03:10:47 PM PST 24 |
Feb 04 03:36:58 PM PST 24 |
121418466559 ps |
| T459 |
/workspace/coverage/default/17.sram_ctrl_executable.1000711312 |
|
|
Feb 04 03:09:12 PM PST 24 |
Feb 04 03:23:54 PM PST 24 |
70500242338 ps |
| T460 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.2767984588 |
|
|
Feb 04 03:19:39 PM PST 24 |
Feb 04 03:19:50 PM PST 24 |
169518033 ps |
| T461 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.3525463396 |
|
|
Feb 04 03:16:15 PM PST 24 |
Feb 04 03:23:30 PM PST 24 |
20410181416 ps |
| T462 |
/workspace/coverage/default/10.sram_ctrl_bijection.1750366494 |
|
|
Feb 04 03:06:18 PM PST 24 |
Feb 04 03:06:55 PM PST 24 |
2216059100 ps |
| T463 |
/workspace/coverage/default/2.sram_ctrl_bijection.1923153933 |
|
|
Feb 04 03:02:11 PM PST 24 |
Feb 04 03:02:53 PM PST 24 |
2478395828 ps |
| T464 |
/workspace/coverage/default/6.sram_ctrl_regwen.1470883764 |
|
|
Feb 04 03:04:40 PM PST 24 |
Feb 04 03:07:47 PM PST 24 |
8938085408 ps |
| T465 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.1837833155 |
|
|
Feb 04 03:07:30 PM PST 24 |
Feb 04 03:07:45 PM PST 24 |
76429060 ps |
| T466 |
/workspace/coverage/default/17.sram_ctrl_alert_test.591658227 |
|
|
Feb 04 03:09:13 PM PST 24 |
Feb 04 03:09:15 PM PST 24 |
73738369 ps |
| T467 |
/workspace/coverage/default/39.sram_ctrl_stress_pipeline.1222119170 |
|
|
Feb 04 03:16:15 PM PST 24 |
Feb 04 03:20:01 PM PST 24 |
9971592236 ps |
| T468 |
/workspace/coverage/default/30.sram_ctrl_alert_test.2242928382 |
|
|
Feb 04 03:13:51 PM PST 24 |
Feb 04 03:13:52 PM PST 24 |
38838876 ps |
| T469 |
/workspace/coverage/default/35.sram_ctrl_multiple_keys.2459260724 |
|
|
Feb 04 03:14:48 PM PST 24 |
Feb 04 03:20:49 PM PST 24 |
2035994990 ps |
| T470 |
/workspace/coverage/default/47.sram_ctrl_smoke.2636801121 |
|
|
Feb 04 03:18:32 PM PST 24 |
Feb 04 03:20:14 PM PST 24 |
495220961 ps |
| T471 |
/workspace/coverage/default/5.sram_ctrl_smoke.2441884415 |
|
|
Feb 04 03:03:49 PM PST 24 |
Feb 04 03:06:44 PM PST 24 |
209126924 ps |
| T472 |
/workspace/coverage/default/20.sram_ctrl_alert_test.2032765881 |
|
|
Feb 04 03:10:20 PM PST 24 |
Feb 04 03:10:22 PM PST 24 |
83750975 ps |
| T473 |
/workspace/coverage/default/21.sram_ctrl_partial_access.2505550252 |
|
|
Feb 04 03:10:35 PM PST 24 |
Feb 04 03:10:47 PM PST 24 |
484082164 ps |
| T474 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.2354485900 |
|
|
Feb 04 03:01:00 PM PST 24 |
Feb 04 03:23:58 PM PST 24 |
3623314515 ps |
| T475 |
/workspace/coverage/default/25.sram_ctrl_multiple_keys.1898163003 |
|
|
Feb 04 03:11:43 PM PST 24 |
Feb 04 03:25:48 PM PST 24 |
9536778491 ps |
| T476 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.2164362504 |
|
|
Feb 04 03:18:00 PM PST 24 |
Feb 04 03:18:53 PM PST 24 |
976000072 ps |
| T477 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.157762535 |
|
|
Feb 04 03:07:30 PM PST 24 |
Feb 04 04:15:13 PM PST 24 |
1717883608 ps |
| T478 |
/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.62576039 |
|
|
Feb 04 03:16:13 PM PST 24 |
Feb 04 03:21:41 PM PST 24 |
8428568922 ps |
| T479 |
/workspace/coverage/default/5.sram_ctrl_executable.2978670894 |
|
|
Feb 04 03:04:03 PM PST 24 |
Feb 04 03:33:04 PM PST 24 |
60909826451 ps |
| T480 |
/workspace/coverage/default/40.sram_ctrl_mem_partial_access.3265944751 |
|
|
Feb 04 03:16:35 PM PST 24 |
Feb 04 03:16:41 PM PST 24 |
65914325 ps |
| T481 |
/workspace/coverage/default/34.sram_ctrl_regwen.2681561274 |
|
|
Feb 04 03:14:48 PM PST 24 |
Feb 04 03:19:41 PM PST 24 |
12202526754 ps |
| T482 |
/workspace/coverage/default/20.sram_ctrl_executable.1436727584 |
|
|
Feb 04 03:10:11 PM PST 24 |
Feb 04 03:16:18 PM PST 24 |
31146618284 ps |
| T483 |
/workspace/coverage/default/39.sram_ctrl_regwen.2114328813 |
|
|
Feb 04 03:16:24 PM PST 24 |
Feb 04 03:33:20 PM PST 24 |
35010732184 ps |
| T484 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.2718658966 |
|
|
Feb 04 03:15:20 PM PST 24 |
Feb 04 03:17:10 PM PST 24 |
888951188 ps |
| T485 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.2013711170 |
|
|
Feb 04 03:09:55 PM PST 24 |
Feb 04 03:10:27 PM PST 24 |
345901303 ps |
| T486 |
/workspace/coverage/default/1.sram_ctrl_alert_test.763187379 |
|
|
Feb 04 03:02:09 PM PST 24 |
Feb 04 03:02:14 PM PST 24 |
38843755 ps |
| T487 |
/workspace/coverage/default/7.sram_ctrl_smoke.2985220328 |
|
|
Feb 04 03:04:56 PM PST 24 |
Feb 04 03:06:26 PM PST 24 |
149035963 ps |
| T488 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.2857292253 |
|
|
Feb 04 03:15:20 PM PST 24 |
Feb 04 03:19:03 PM PST 24 |
3103548461 ps |
| T489 |
/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.2564109610 |
|
|
Feb 04 03:15:43 PM PST 24 |
Feb 04 03:21:18 PM PST 24 |
19609532273 ps |
| T490 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.2948109888 |
|
|
Feb 04 03:08:10 PM PST 24 |
Feb 04 04:25:38 PM PST 24 |
14811818601 ps |
| T491 |
/workspace/coverage/default/38.sram_ctrl_alert_test.828860802 |
|
|
Feb 04 03:15:50 PM PST 24 |
Feb 04 03:15:52 PM PST 24 |
27581364 ps |
| T492 |
/workspace/coverage/default/19.sram_ctrl_stress_pipeline.3333806522 |
|
|
Feb 04 03:09:38 PM PST 24 |
Feb 04 03:12:46 PM PST 24 |
3428355466 ps |
| T493 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.3746786889 |
|
|
Feb 04 03:17:00 PM PST 24 |
Feb 04 03:18:29 PM PST 24 |
168269039 ps |
| T494 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.2467294700 |
|
|
Feb 04 03:05:33 PM PST 24 |
Feb 04 03:07:20 PM PST 24 |
248453576 ps |
| T495 |
/workspace/coverage/default/18.sram_ctrl_alert_test.1778871198 |
|
|
Feb 04 03:09:35 PM PST 24 |
Feb 04 03:09:42 PM PST 24 |
115407302 ps |
| T496 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.1323817892 |
|
|
Feb 04 03:07:31 PM PST 24 |
Feb 04 03:07:41 PM PST 24 |
2334235990 ps |
| T497 |
/workspace/coverage/default/27.sram_ctrl_mem_partial_access.1925177538 |
|
|
Feb 04 03:12:35 PM PST 24 |
Feb 04 03:12:45 PM PST 24 |
1445343588 ps |
| T498 |
/workspace/coverage/default/23.sram_ctrl_stress_all.1045959204 |
|
|
Feb 04 03:11:23 PM PST 24 |
Feb 04 03:13:17 PM PST 24 |
30038718266 ps |
| T499 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.1933616439 |
|
|
Feb 04 03:07:11 PM PST 24 |
Feb 04 03:07:15 PM PST 24 |
84730188 ps |
| T500 |
/workspace/coverage/default/4.sram_ctrl_executable.773622093 |
|
|
Feb 04 03:03:28 PM PST 24 |
Feb 04 03:21:24 PM PST 24 |
12317119981 ps |
| T501 |
/workspace/coverage/default/10.sram_ctrl_ram_cfg.1532067918 |
|
|
Feb 04 03:06:35 PM PST 24 |
Feb 04 03:06:37 PM PST 24 |
52235209 ps |
| T502 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2474644494 |
|
|
Feb 04 03:06:18 PM PST 24 |
Feb 04 03:15:27 PM PST 24 |
41379431030 ps |
| T503 |
/workspace/coverage/default/11.sram_ctrl_regwen.1615324965 |
|
|
Feb 04 03:07:05 PM PST 24 |
Feb 04 03:31:36 PM PST 24 |
9667720110 ps |