Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	12290542	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

47896324

1

T1

177647

T2

34828

T3

8725

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	29988664	1			T1	97708		T2	95964		T3	4336
values[0x0]	13862913	1			T1	46907		T2	32109		T3	2221
values[0x1]	16335289	1			T1	50734		T2	62880		T3	2168

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6124794	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

54062072

1

T1

186523

T2

113155

T3

8725

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	261978	1			T1	828		T2	760		T3	34
valid_sources[0x01]	227774	1			T1	735		T2	710		T3	28
valid_sources[0x02]	233828	1			T1	795		T2	733		T3	28
valid_sources[0x03]	231483	1			T1	716		T2	794		T3	32
valid_sources[0x04]	274499	1			T1	815		T2	752		T3	46
valid_sources[0x05]	241743	1			T1	742		T2	731		T3	52
valid_sources[0x06]	224780	1			T1	732		T2	734		T3	28
valid_sources[0x07]	265900	1			T1	747		T2	753		T3	23
valid_sources[0x08]	288996	1			T1	821		T2	764		T3	31
valid_sources[0x09]	273330	1			T1	766		T2	769		T3	41
valid_sources[0x0a]	214535	1			T1	834		T2	831		T3	36
valid_sources[0x0b]	212432	1			T1	816		T2	743		T3	38
valid_sources[0x0c]	224727	1			T1	695		T2	673		T3	38
valid_sources[0x0d]	214221	1			T1	885		T2	709		T3	33
valid_sources[0x0e]	206117	1			T1	740		T2	728		T3	34
valid_sources[0x0f]	319754	1			T1	688		T2	750		T3	33
valid_sources[0x10]	306938	1			T1	756		T2	726		T3	38
valid_sources[0x11]	279846	1			T1	540		T2	786		T3	45
valid_sources[0x12]	238431	1			T1	749		T2	698		T3	30
valid_sources[0x13]	215843	1			T1	807		T2	759		T3	28
valid_sources[0x14]	288830	1			T1	855		T2	741		T3	33
valid_sources[0x15]	210739	1			T1	853		T2	696		T3	41
valid_sources[0x16]	274753	1			T1	827		T2	798		T3	29
valid_sources[0x17]	247999	1			T1	773		T2	777		T3	31
valid_sources[0x18]	203736	1			T1	754		T2	676		T3	32
valid_sources[0x19]	227710	1			T1	642		T2	785		T3	35
valid_sources[0x1a]	205690	1			T1	787		T2	723		T3	32
valid_sources[0x1b]	235446	1			T1	740		T2	700		T3	40
valid_sources[0x1c]	227927	1			T1	868		T2	694		T3	40
valid_sources[0x1d]	252376	1			T1	705		T2	720		T3	31
valid_sources[0x1e]	219986	1			T1	653		T2	752		T3	29
valid_sources[0x1f]	208403	1			T1	847		T2	779		T3	38
valid_sources[0x20]	206180	1			T1	830		T2	775		T3	28
valid_sources[0x21]	207265	1			T1	761		T2	708		T3	34
valid_sources[0x22]	209126	1			T1	776		T2	681		T3	23
valid_sources[0x23]	233244	1			T1	810		T2	725		T3	37
valid_sources[0x24]	229880	1			T1	654		T2	685		T3	23
valid_sources[0x25]	216219	1			T1	741		T2	760		T3	32
valid_sources[0x26]	244463	1			T1	738		T2	736		T3	36
valid_sources[0x27]	366932	1			T1	729		T2	761		T3	31
valid_sources[0x28]	227354	1			T1	725		T2	777		T3	40
valid_sources[0x29]	229631	1			T1	703		T2	734		T3	29
valid_sources[0x2a]	386279	1			T1	800		T2	761		T3	37
valid_sources[0x2b]	233470	1			T1	742		T2	806		T3	36
valid_sources[0x2c]	218144	1			T1	805		T2	735		T3	21
valid_sources[0x2d]	270466	1			T1	785		T2	695		T3	40
valid_sources[0x2e]	205196	1			T1	633		T2	756		T3	34
valid_sources[0x2f]	229815	1			T1	757		T2	777		T3	32
valid_sources[0x30]	248720	1			T1	643		T2	735		T3	28
valid_sources[0x31]	250935	1			T1	913		T2	701		T3	37
valid_sources[0x32]	198136	1			T1	748		T2	711		T3	43
valid_sources[0x33]	200310	1			T1	702		T2	740		T3	35
valid_sources[0x34]	204058	1			T1	839		T2	769		T3	30
valid_sources[0x35]	239995	1			T1	764		T2	724		T3	44
valid_sources[0x36]	214282	1			T1	735		T2	766		T3	37
valid_sources[0x37]	203128	1			T1	760		T2	813		T3	33
valid_sources[0x38]	249456	1			T1	728		T2	765		T3	42
valid_sources[0x39]	282015	1			T1	806		T2	751		T3	36
valid_sources[0x3a]	263266	1			T1	839		T2	773		T3	32
valid_sources[0x3b]	204611	1			T1	692		T2	767		T3	30
valid_sources[0x3c]	206336	1			T1	728		T2	763		T3	28
valid_sources[0x3d]	210399	1			T1	801		T2	811		T3	30
valid_sources[0x3e]	247374	1			T1	818		T2	784		T3	39
valid_sources[0x3f]	271468	1			T1	753		T2	725		T3	41
valid_sources[0x40]	210419	1			T1	756		T2	775		T3	35
valid_sources[0x41]	217046	1			T1	932		T2	721		T3	47
valid_sources[0x42]	291898	1			T1	744		T2	742		T3	35
valid_sources[0x43]	262055	1			T1	753		T2	763		T3	39
valid_sources[0x44]	320635	1			T1	757		T2	741		T3	40
valid_sources[0x45]	251588	1			T1	864		T2	765		T3	34
valid_sources[0x46]	210738	1			T1	855		T2	842		T3	28
valid_sources[0x47]	214044	1			T1	667		T2	761		T3	36
valid_sources[0x48]	209445	1			T1	735		T2	691		T3	31
valid_sources[0x49]	209997	1			T1	826		T2	741		T3	24
valid_sources[0x4a]	202641	1			T1	713		T2	672		T3	30
valid_sources[0x4b]	234716	1			T1	716		T2	707		T3	26
valid_sources[0x4c]	206913	1			T1	760		T2	743		T3	28
valid_sources[0x4d]	211340	1			T1	813		T2	717		T3	37
valid_sources[0x4e]	230342	1			T1	798		T2	779		T3	39
valid_sources[0x4f]	286238	1			T1	794		T2	768		T3	29
valid_sources[0x50]	322838	1			T1	732		T2	740		T3	39
valid_sources[0x51]	199862	1			T1	785		T2	786		T3	43
valid_sources[0x52]	211903	1			T1	619		T2	767		T3	40
valid_sources[0x53]	241006	1			T1	668		T2	759		T3	51
valid_sources[0x54]	203583	1			T1	842		T2	755		T3	39
valid_sources[0x55]	205100	1			T1	777		T2	805		T3	37
valid_sources[0x56]	212373	1			T1	771		T2	701		T3	29
valid_sources[0x57]	214144	1			T1	892		T2	673		T3	34
valid_sources[0x58]	290150	1			T1	751		T2	801		T3	36
valid_sources[0x59]	219549	1			T1	823		T2	686		T3	36
valid_sources[0x5a]	205049	1			T1	886		T2	714		T3	36
valid_sources[0x5b]	207191	1			T1	781		T2	755		T3	22
valid_sources[0x5c]	239775	1			T1	781		T2	779		T3	37
valid_sources[0x5d]	213011	1			T1	774		T2	725		T3	22
valid_sources[0x5e]	215496	1			T1	702		T2	723		T3	40
valid_sources[0x5f]	247052	1			T1	848		T2	808		T3	48
valid_sources[0x60]	253293	1			T1	714		T2	705		T3	45
valid_sources[0x61]	279826	1			T1	799		T2	719		T3	39
valid_sources[0x62]	229586	1			T1	634		T2	769		T3	41
valid_sources[0x63]	236471	1			T1	659		T2	830		T3	34
valid_sources[0x64]	220126	1			T1	826		T2	839		T3	42
valid_sources[0x65]	221507	1			T1	712		T2	721		T3	30
valid_sources[0x66]	325566	1			T1	651		T2	813		T3	32
valid_sources[0x67]	214210	1			T1	812		T2	754		T3	35
valid_sources[0x68]	217282	1			T1	890		T2	717		T3	37
valid_sources[0x69]	222737	1			T1	732		T2	710		T3	38
valid_sources[0x6a]	229977	1			T1	782		T2	765		T3	46
valid_sources[0x6b]	224851	1			T1	866		T2	729		T3	34
valid_sources[0x6c]	234436	1			T1	733		T2	810		T3	43
valid_sources[0x6d]	204933	1			T1	734		T2	736		T3	27
valid_sources[0x6e]	218598	1			T1	799		T2	780		T3	49
valid_sources[0x6f]	217734	1			T1	782		T2	752		T3	40
valid_sources[0x70]	287321	1			T1	784		T2	749		T3	31
valid_sources[0x71]	232525	1			T1	808		T2	778		T3	42
valid_sources[0x72]	209226	1			T1	715		T2	696		T3	41
valid_sources[0x73]	211446	1			T1	675		T2	790		T3	31
valid_sources[0x74]	242350	1			T1	869		T2	762		T3	37
valid_sources[0x75]	211627	1			T1	748		T2	739		T3	21
valid_sources[0x76]	229874	1			T1	786		T2	756		T3	39
valid_sources[0x77]	215870	1			T1	712		T2	725		T3	25
valid_sources[0x78]	244429	1			T1	756		T2	788		T3	35
valid_sources[0x79]	205895	1			T1	661		T2	702		T3	40
valid_sources[0x7a]	200689	1			T1	640		T2	737		T3	41
valid_sources[0x7b]	252489	1			T1	769		T2	820		T3	34
valid_sources[0x7c]	217011	1			T1	836		T2	765		T3	30
valid_sources[0x7d]	271747	1			T1	839		T2	758		T3	52
valid_sources[0x7e]	213472	1			T1	910		T2	738		T3	28
valid_sources[0x7f]	254474	1			T1	895		T2	743		T3	37
valid_sources[0x80]	202536	1			T1	937		T2	752		T3	38

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

23844311

1

T1

88847

T2

17573

T3

4336

values[0x0]

all_enables

biggest_size

12019629

1

T1

44248

T2

8682

T3

2221

values[0x1]

all_enables

biggest_size

12032384

1

T1

44552

T2

8573

T3

2168

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	31189	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

132694

1

T1

7

T2

2

T4

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	48086	1			T5	33		T9	15		T6	20
values[0x0]	55853	1			T1	18		T2	3		T3	1
values[0x1]	59944	1			T1	10		T2	2		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	23598	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

140285

1

T1

8

T2

2

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	526	1			T5	2		T7	3		T35	10
valid_sources[0x01]	727	1			T35	4		T36	16		T29	1
valid_sources[0x02]	657	1			T35	6		T36	2		T144	1
valid_sources[0x03]	866	1			T35	7		T64	3		T36	8
valid_sources[0x04]	558	1			T77	11		T35	8		T145	2
valid_sources[0x05]	652	1			T5	1		T62	1		T35	3
valid_sources[0x06]	648	1			T35	3		T36	3		T49	20
valid_sources[0x07]	550	1			T35	8		T21	56		T146	1
valid_sources[0x08]	583	1			T5	1		T9	1		T35	5
valid_sources[0x09]	513	1			T5	3		T11	1		T147	1
valid_sources[0x0a]	551	1			T9	2		T62	1		T75	1
valid_sources[0x0b]	751	1			T62	1		T35	12		T58	1
valid_sources[0x0c]	773	1			T35	8		T36	6		T30	2
valid_sources[0x0d]	505	1			T24	2		T7	3		T35	8
valid_sources[0x0e]	488	1			T35	3		T36	3		T49	10
valid_sources[0x0f]	673	1			T62	2		T35	10		T36	12
valid_sources[0x10]	551	1			T9	4		T35	6		T36	6
valid_sources[0x11]	504	1			T35	4		T58	1		T36	8
valid_sources[0x12]	626	1			T62	1		T7	1		T35	2
valid_sources[0x13]	520	1			T28	2		T35	5		T57	3
valid_sources[0x14]	410	1			T62	4		T7	3		T35	4
valid_sources[0x15]	599	1			T5	3		T35	7		T36	2
valid_sources[0x16]	699	1			T9	1		T62	2		T27	2
valid_sources[0x17]	447	1			T62	3		T35	3		T21	3
valid_sources[0x18]	889	1			T35	6		T36	4		T49	8
valid_sources[0x19]	555	1			T5	1		T35	5		T26	1
valid_sources[0x1a]	803	1			T7	6		T35	7		T58	1
valid_sources[0x1b]	538	1			T9	3		T62	1		T35	6
valid_sources[0x1c]	586	1			T9	1		T35	11		T142	75
valid_sources[0x1d]	481	1			T35	7		T36	2		T49	7
valid_sources[0x1e]	593	1			T5	1		T148	1		T35	7
valid_sources[0x1f]	609	1			T35	12		T57	5		T58	2
valid_sources[0x20]	514	1			T75	1		T7	2		T35	3
valid_sources[0x21]	536	1			T35	3		T36	3		T49	16
valid_sources[0x22]	553	1			T5	1		T9	1		T27	2
valid_sources[0x23]	524	1			T5	1		T75	1		T35	6
valid_sources[0x24]	997	1			T28	10		T35	7		T21	149
valid_sources[0x25]	634	1			T24	2		T35	5		T57	2
valid_sources[0x26]	621	1			T62	2		T7	1		T35	4
valid_sources[0x27]	540	1			T5	1		T35	15		T36	2
valid_sources[0x28]	539	1			T9	1		T75	1		T35	8
valid_sources[0x29]	536	1			T62	1		T35	6		T26	4
valid_sources[0x2a]	727	1			T35	14		T63	38		T36	10
valid_sources[0x2b]	609	1			T35	8		T36	5		T149	1
valid_sources[0x2c]	493	1			T9	2		T62	2		T35	7
valid_sources[0x2d]	759	1			T35	7		T57	1		T36	1
valid_sources[0x2e]	522	1			T28	11		T35	17		T36	7
valid_sources[0x2f]	649	1			T5	1		T27	1		T35	5
valid_sources[0x30]	815	1			T75	1		T7	1		T35	8
valid_sources[0x31]	947	1			T5	2		T62	3		T35	6
valid_sources[0x32]	950	1			T62	1		T35	9		T58	2
valid_sources[0x33]	640	1			T9	3		T7	1		T35	5
valid_sources[0x34]	602	1			T9	1		T147	1		T35	8
valid_sources[0x35]	982	1			T35	11		T26	2		T141	1
valid_sources[0x36]	551	1			T5	2		T9	3		T35	9
valid_sources[0x37]	499	1			T35	7		T58	2		T36	3
valid_sources[0x38]	594	1			T35	9		T36	6		T49	18
valid_sources[0x39]	493	1			T35	5		T36	4		T29	1
valid_sources[0x3a]	678	1			T27	6		T35	8		T36	9
valid_sources[0x3b]	888	1			T5	1		T36	7		T49	9
valid_sources[0x3c]	695	1			T75	1		T35	9		T36	4
valid_sources[0x3d]	589	1			T5	1		T77	1		T75	1
valid_sources[0x3e]	600	1			T35	10		T36	1		T149	1
valid_sources[0x3f]	651	1			T62	1		T27	2		T35	3
valid_sources[0x40]	734	1			T35	9		T36	2		T29	1
valid_sources[0x41]	624	1			T62	1		T27	10		T35	6
valid_sources[0x42]	509	1			T35	13		T36	4		T143	1
valid_sources[0x43]	930	1			T62	1		T35	9		T36	5
valid_sources[0x44]	706	1			T7	2		T35	14		T21	1
valid_sources[0x45]	687	1			T9	2		T35	9		T57	1
valid_sources[0x46]	783	1			T35	10		T64	6		T36	1
valid_sources[0x47]	517	1			T14	1		T62	1		T35	5
valid_sources[0x48]	636	1			T62	3		T35	12		T36	6
valid_sources[0x49]	605	1			T5	1		T9	1		T62	1
valid_sources[0x4a]	496	1			T62	1		T35	10		T57	2
valid_sources[0x4b]	551	1			T76	1		T35	3		T36	4
valid_sources[0x4c]	574	1			T62	1		T35	4		T150	1
valid_sources[0x4d]	756	1			T9	1		T27	9		T35	12
valid_sources[0x4e]	558	1			T35	8		T36	2		T49	5
valid_sources[0x4f]	785	1			T35	6		T30	9		T49	8
valid_sources[0x50]	555	1			T62	1		T35	3		T36	6
valid_sources[0x51]	576	1			T35	13		T37	1		T143	2
valid_sources[0x52]	655	1			T9	1		T35	6		T36	4
valid_sources[0x53]	479	1			T75	1		T35	9		T36	2
valid_sources[0x54]	510	1			T35	4		T21	3		T36	1
valid_sources[0x55]	607	1			T5	1		T7	1		T35	7
valid_sources[0x56]	499	1			T35	5		T36	17		T29	2
valid_sources[0x57]	504	1			T35	6		T64	1		T36	13
valid_sources[0x58]	473	1			T9	1		T35	9		T36	2
valid_sources[0x59]	571	1			T5	1		T35	9		T64	1
valid_sources[0x5a]	545	1			T35	10		T36	8		T49	7
valid_sources[0x5b]	516	1			T35	9		T36	6		T29	1
valid_sources[0x5c]	560	1			T35	9		T36	8		T49	21
valid_sources[0x5d]	667	1			T9	5		T24	2		T35	6
valid_sources[0x5e]	932	1			T62	4		T35	13		T36	7
valid_sources[0x5f]	584	1			T35	9		T36	16		T151	2
valid_sources[0x60]	683	1			T5	1		T9	2		T35	9
valid_sources[0x61]	906	1			T9	1		T35	5		T21	135
valid_sources[0x62]	616	1			T35	6		T36	4		T29	1
valid_sources[0x63]	892	1			T75	1		T35	4		T57	1
valid_sources[0x64]	564	1			T7	2		T35	7		T21	56
valid_sources[0x65]	564	1			T12	1		T27	4		T7	1
valid_sources[0x66]	460	1			T9	1		T35	3		T36	14
valid_sources[0x67]	565	1			T35	3		T36	5		T49	12
valid_sources[0x68]	1027	1			T62	2		T76	1		T35	7
valid_sources[0x69]	515	1			T5	1		T9	1		T35	8
valid_sources[0x6a]	633	1			T5	2		T9	1		T62	1
valid_sources[0x6b]	524	1			T35	16		T21	4		T36	4
valid_sources[0x6c]	801	1			T62	1		T35	5		T49	8
valid_sources[0x6d]	589	1			T34	1		T35	8		T57	2
valid_sources[0x6e]	572	1			T35	13		T36	2		T30	1
valid_sources[0x6f]	800	1			T9	1		T147	2		T35	5
valid_sources[0x70]	544	1			T35	6		T36	19		T49	13
valid_sources[0x71]	739	1			T35	14		T57	1		T36	7
valid_sources[0x72]	876	1			T35	8		T36	9		T29	1
valid_sources[0x73]	775	1			T35	8		T36	3		T30	1
valid_sources[0x74]	902	1			T35	12		T49	10		T50	6
valid_sources[0x75]	505	1			T9	1		T75	1		T35	9
valid_sources[0x76]	609	1			T5	5		T75	1		T35	5
valid_sources[0x77]	591	1			T10	1		T28	30		T35	10
valid_sources[0x78]	557	1			T35	8		T36	2		T49	14
valid_sources[0x79]	713	1			T9	2		T35	4		T57	1
valid_sources[0x7a]	580	1			T35	5		T36	1		T149	1
valid_sources[0x7b]	735	1			T5	1		T35	9		T21	3
valid_sources[0x7c]	541	1			T62	2		T35	4		T36	17
valid_sources[0x7d]	788	1			T27	2		T28	1		T101	1
valid_sources[0x7e]	526	1			T35	3		T36	4		T143	1
valid_sources[0x7f]	474	1			T35	10		T64	2		T36	5
valid_sources[0x80]	729	1			T62	4		T35	6		T36	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

36395

1

T5

16

T9

6

T6

11

values[0x0]

all_enables

biggest_size

48831

1

T1

6

T2

2

T4

1

values[0x1]

all_enables

biggest_size

47468

1

T1

1

T4

1

T5

3