Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

12052775

1

T1

14234

T2

156125

T4

175364

full_word

43649536

1

T1

141829

T2

34828

T3

8725

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	55702031	1			T1	156063		T2	190953		T3	8725
auto[TlIntgErrCmd]	93	1			T106	10		T107	4		T108	6
auto[TlIntgErrData]	87	1			T106	3		T107	3		T108	7
auto[TlIntgErrBoth]	100	1			T106	7		T107	3		T108	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25412031

1

T1

58422

T2

95964

T3

4336

auto[1]

30290280

1

T1

97641

T2

94989

T3

4389

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5762598	1			T1	5393		T2	78391		T4	88085
auto[TlIntgErrNone]	partial	auto[1]	6289920	1			T1	8841		T2	77734		T4	87279
auto[TlIntgErrNone]	full_word	auto[0]	19649309	1			T1	53029		T2	17573		T3	4336
auto[TlIntgErrNone]	full_word	auto[1]	24000204	1			T1	88800		T2	17255		T3	4389
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T106	4		T107	2		T108	3
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T106	3		T107	2		T108	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T106	1		T133	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T106	2		T135	1		-	-
auto[TlIntgErrData]	partial	auto[0]	39	1			T106	2		T107	2		T108	2
auto[TlIntgErrData]	partial	auto[1]	41	1			T106	1		T107	1		T108	5
auto[TlIntgErrData]	full_word	auto[0]	5	1			T136	1		T130	1		T131	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T137	1		T134	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T106	3		T107	1		T108	4
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T106	3		T107	2		T108	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T106	1		T108	1		T127	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T128	1		T130	1		T138	1