Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	648739	1			T2	12027		T4	24784		T10	986
auto[1]	8685731	1			T1	5259		T2	12641		T3	4336
auto[2]	563177	1			T2	11865		T4	17879		T10	623
auto[3]	8608583	1			T1	5386		T2	12591		T3	4388

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	11310688	1			T1	8764		T2	990		T3	8724
auto[1]	1828214	1			T1	913		T2	5293		T4	11111
auto[2]	1830693	1			T1	864		T2	7007		T4	9263
auto[3]	3536635	1			T1	104		T2	35834		T4	56070

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5234408

1

T1

10638

T3

8717

T5

1107

auto[1]

13271822

1

T1

7

T2

49124

T3

7

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	268884	1			T10	23		T6	14		T33	2
auto[0]	auto[0]	auto[1]	27602	1			T10	155		T12	2		T21	38
auto[0]	auto[0]	auto[2]	27664	1			T10	156		T12	2		T6	2
auto[0]	auto[0]	auto[3]	8939	1			T10	652		T12	224		T21	3
auto[0]	auto[1]	auto[0]	1857879	1			T1	4306		T3	4333		T5	468
auto[0]	auto[1]	auto[1]	209985	1			T1	480		T5	40		T9	48
auto[0]	auto[1]	auto[2]	188107	1			T1	418		T5	47		T9	26
auto[0]	auto[1]	auto[3]	65857	1			T1	53		T5	4		T9	9
auto[0]	auto[2]	auto[0]	238344	1			T10	33		T6	16		T33	5
auto[0]	auto[2]	auto[1]	24465	1			T10	123		T12	21		T21	26
auto[0]	auto[2]	auto[2]	22155	1			T10	77		T21	61		T58	1529
auto[0]	auto[2]	auto[3]	7089	1			T10	390		T12	128		T21	5
auto[0]	auto[3]	auto[0]	1826534	1			T1	4453		T3	4384		T5	473
auto[0]	auto[3]	auto[1]	185850	1			T1	433		T5	39		T9	19
auto[0]	auto[3]	auto[2]	206598	1			T1	444		T5	32		T9	68
auto[0]	auto[3]	auto[3]	68456	1			T1	51		T5	4		T9	7
auto[1]	auto[0]	auto[0]	10918	1			T2	396		T4	840		T21	1
auto[1]	auto[0]	auto[1]	46844	1			T2	1723		T4	3787		T121	3968
auto[1]	auto[0]	auto[2]	46905	1			T2	1756		T4	3613		T58	2
auto[1]	auto[0]	auto[3]	210983	1			T2	8152		T4	16544		T12	2
auto[1]	auto[1]	auto[0]	3549036	1			T1	2		T2	270		T3	3
auto[1]	auto[1]	auto[1]	661161	1			T2	2094		T4	3526		T14	2
auto[1]	auto[1]	auto[2]	643253	1			T2	1102		T4	686		T77	4
auto[1]	auto[1]	auto[3]	1510453	1			T2	9175		T4	16905		T27	3
auto[1]	auto[2]	auto[0]	8975	1			T2	228		T4	804		T58	14
auto[1]	auto[2]	auto[1]	38484	1			T2	1028		T4	3428		T58	1
auto[1]	auto[2]	auto[2]	40545	1			T2	1929		T4	2459		T58	2
auto[1]	auto[2]	auto[3]	183120	1			T2	8680		T4	11188		T12	2
auto[1]	auto[3]	auto[0]	3550118	1			T1	3		T2	96		T3	4
auto[1]	auto[3]	auto[1]	633823	1			T2	448		T4	370		T77	7
auto[1]	auto[3]	auto[2]	655466	1			T1	2		T2	2220		T4	2505
auto[1]	auto[3]	auto[3]	1481738	1			T2	9827		T4	11433		T12	1