Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.89	100.00	97.78	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	267599483	124262	0	0
ctrl_regwen_rd_A	267599483	6615	0	0
exec_rd_A	267599483	5887	0	0
exec_regwen_rd_A	267599483	6800	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	267599483	124262	0	0
T21	145175	2892	0	0
T26	780	0	0	0
T35	27881	1279	0	0
T36	0	1243	0	0
T37	2238	0	0	0
T49	0	2996	0	0
T50	0	1770	0	0
T51	0	844	0	0
T52	0	4161	0	0
T53	0	2927	0	0
T54	0	1519	0	0
T55	0	3440	0	0
T56	71929	0	0	0
T57	137350	0	0	0
T58	216920	0	0	0
T59	22189	0	0	0
T60	22934	0	0	0
T61	188500	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	267599483	6615	0	0
T50	72973	442	0	0
T51	0	133	0	0
T84	14218	0	0	0
T110	0	424	0	0
T111	0	499	0	0
T112	0	871	0	0
T113	0	750	0	0
T114	0	929	0	0
T115	0	529	0	0
T116	0	110	0	0
T117	0	267	0	0
T118	435687	0	0	0
T119	248360	0	0	0
T120	1654	0	0	0
T121	159336	0	0	0
T122	63164	0	0	0
T123	176622	0	0	0
T124	290664	0	0	0
T125	222424	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	267599483	5887	0	0
T50	72973	361	0	0
T51	0	104	0	0
T84	14218	0	0	0
T110	0	396	0	0
T111	0	375	0	0
T112	0	706	0	0
T113	0	772	0	0
T114	0	870	0	0
T115	0	441	0	0
T116	0	119	0	0
T117	0	196	0	0
T118	435687	0	0	0
T119	248360	0	0	0
T120	1654	0	0	0
T121	159336	0	0	0
T122	63164	0	0	0
T123	176622	0	0	0
T124	290664	0	0	0
T125	222424	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	267599483	6800	0	0
T50	72973	429	0	0
T51	0	93	0	0
T84	14218	0	0	0
T110	0	334	0	0
T111	0	513	0	0
T112	0	956	0	0
T113	0	797	0	0
T114	0	939	0	0
T115	0	582	0	0
T116	0	176	0	0
T117	0	236	0	0
T118	435687	0	0	0
T119	248360	0	0	0
T120	1654	0	0	0
T121	159336	0	0	0
T122	63164	0	0	0
T123	176622	0	0	0
T124	290664	0	0	0
T125	222424	0	0	0