| T302 |
/workspace/coverage/default/29.sram_ctrl_lc_escalation.603060773 |
|
|
Mar 05 12:55:53 PM PST 24 |
Mar 05 12:56:05 PM PST 24 |
695468714 ps |
| T303 |
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1554488621 |
|
|
Mar 05 12:58:29 PM PST 24 |
Mar 05 12:58:46 PM PST 24 |
85693919 ps |
| T304 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.4200044709 |
|
|
Mar 05 12:54:05 PM PST 24 |
Mar 05 12:57:30 PM PST 24 |
2313058839 ps |
| T305 |
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.290518728 |
|
|
Mar 05 12:57:55 PM PST 24 |
Mar 05 12:58:56 PM PST 24 |
129597754 ps |
| T306 |
/workspace/coverage/default/30.sram_ctrl_max_throughput.1339368219 |
|
|
Mar 05 12:56:01 PM PST 24 |
Mar 05 12:56:22 PM PST 24 |
77796627 ps |
| T307 |
/workspace/coverage/default/44.sram_ctrl_regwen.3594807383 |
|
|
Mar 05 12:58:04 PM PST 24 |
Mar 05 01:10:10 PM PST 24 |
10372205754 ps |
| T308 |
/workspace/coverage/default/24.sram_ctrl_regwen.3762282638 |
|
|
Mar 05 12:55:28 PM PST 24 |
Mar 05 01:14:02 PM PST 24 |
2849431346 ps |
| T309 |
/workspace/coverage/default/2.sram_ctrl_ram_cfg.887246612 |
|
|
Mar 05 12:52:55 PM PST 24 |
Mar 05 12:52:56 PM PST 24 |
26972206 ps |
| T310 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.4165806437 |
|
|
Mar 05 12:58:02 PM PST 24 |
Mar 05 12:58:11 PM PST 24 |
1892681536 ps |
| T311 |
/workspace/coverage/default/47.sram_ctrl_executable.2298083477 |
|
|
Mar 05 12:58:19 PM PST 24 |
Mar 05 12:59:16 PM PST 24 |
2519134430 ps |
| T312 |
/workspace/coverage/default/39.sram_ctrl_mem_partial_access.983164706 |
|
|
Mar 05 12:57:40 PM PST 24 |
Mar 05 12:57:43 PM PST 24 |
94344270 ps |
| T313 |
/workspace/coverage/default/5.sram_ctrl_executable.4278124566 |
|
|
Mar 05 12:53:12 PM PST 24 |
Mar 05 01:04:14 PM PST 24 |
7854096060 ps |
| T314 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.2559018416 |
|
|
Mar 05 12:57:52 PM PST 24 |
Mar 05 12:59:54 PM PST 24 |
340164708 ps |
| T315 |
/workspace/coverage/default/11.sram_ctrl_partial_access.3103974986 |
|
|
Mar 05 12:54:00 PM PST 24 |
Mar 05 12:56:04 PM PST 24 |
2595819718 ps |
| T316 |
/workspace/coverage/default/12.sram_ctrl_executable.317348384 |
|
|
Mar 05 12:54:06 PM PST 24 |
Mar 05 01:21:49 PM PST 24 |
33119318135 ps |
| T317 |
/workspace/coverage/default/23.sram_ctrl_stress_all.2623154536 |
|
|
Mar 05 12:55:26 PM PST 24 |
Mar 05 02:06:29 PM PST 24 |
14235217562 ps |
| T318 |
/workspace/coverage/default/14.sram_ctrl_executable.1360930108 |
|
|
Mar 05 12:54:17 PM PST 24 |
Mar 05 01:00:41 PM PST 24 |
3669284314 ps |
| T319 |
/workspace/coverage/default/26.sram_ctrl_lc_escalation.681865473 |
|
|
Mar 05 12:55:36 PM PST 24 |
Mar 05 12:55:39 PM PST 24 |
120498882 ps |
| T320 |
/workspace/coverage/default/35.sram_ctrl_smoke.2053623937 |
|
|
Mar 05 12:56:45 PM PST 24 |
Mar 05 12:57:01 PM PST 24 |
954966540 ps |
| T321 |
/workspace/coverage/default/42.sram_ctrl_bijection.1564973971 |
|
|
Mar 05 12:57:55 PM PST 24 |
Mar 05 12:58:14 PM PST 24 |
521442023 ps |
| T322 |
/workspace/coverage/default/22.sram_ctrl_ram_cfg.1313291059 |
|
|
Mar 05 12:55:10 PM PST 24 |
Mar 05 12:55:11 PM PST 24 |
99795135 ps |
| T323 |
/workspace/coverage/default/47.sram_ctrl_bijection.3199959511 |
|
|
Mar 05 12:58:12 PM PST 24 |
Mar 05 12:59:22 PM PST 24 |
4789776844 ps |
| T324 |
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.3187577118 |
|
|
Mar 05 12:54:18 PM PST 24 |
Mar 05 12:54:24 PM PST 24 |
222728813 ps |
| T325 |
/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.416233075 |
|
|
Mar 05 12:52:56 PM PST 24 |
Mar 05 12:52:59 PM PST 24 |
133277055 ps |
| T326 |
/workspace/coverage/default/14.sram_ctrl_stress_pipeline.1372000359 |
|
|
Mar 05 12:54:18 PM PST 24 |
Mar 05 12:57:36 PM PST 24 |
2115995888 ps |
| T327 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.600340986 |
|
|
Mar 05 12:56:44 PM PST 24 |
Mar 05 12:56:55 PM PST 24 |
2345761523 ps |
| T328 |
/workspace/coverage/default/31.sram_ctrl_executable.3364694107 |
|
|
Mar 05 12:56:16 PM PST 24 |
Mar 05 01:08:47 PM PST 24 |
24715211157 ps |
| T329 |
/workspace/coverage/default/11.sram_ctrl_mem_walk.720746272 |
|
|
Mar 05 12:53:57 PM PST 24 |
Mar 05 12:54:02 PM PST 24 |
461804315 ps |
| T91 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.2577907470 |
|
|
Mar 05 12:53:40 PM PST 24 |
Mar 05 12:53:43 PM PST 24 |
170156023 ps |
| T330 |
/workspace/coverage/default/27.sram_ctrl_stress_all.3100783140 |
|
|
Mar 05 12:55:46 PM PST 24 |
Mar 05 01:37:36 PM PST 24 |
194540960146 ps |
| T331 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.1584098931 |
|
|
Mar 05 12:57:57 PM PST 24 |
Mar 05 12:57:58 PM PST 24 |
128687365 ps |
| T332 |
/workspace/coverage/default/42.sram_ctrl_partial_access.9944071 |
|
|
Mar 05 12:57:56 PM PST 24 |
Mar 05 12:57:59 PM PST 24 |
179930491 ps |
| T333 |
/workspace/coverage/default/35.sram_ctrl_partial_access.3473884038 |
|
|
Mar 05 12:56:46 PM PST 24 |
Mar 05 12:56:55 PM PST 24 |
346695582 ps |
| T334 |
/workspace/coverage/default/40.sram_ctrl_mem_partial_access.2087722919 |
|
|
Mar 05 12:57:41 PM PST 24 |
Mar 05 12:57:44 PM PST 24 |
91382154 ps |
| T335 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.3022526222 |
|
|
Mar 05 12:54:28 PM PST 24 |
Mar 05 12:57:27 PM PST 24 |
2030830101 ps |
| T336 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.1415360611 |
|
|
Mar 05 12:56:40 PM PST 24 |
Mar 05 01:02:10 PM PST 24 |
4900569204 ps |
| T337 |
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.3450799516 |
|
|
Mar 05 12:54:06 PM PST 24 |
Mar 05 12:59:09 PM PST 24 |
29561844604 ps |
| T338 |
/workspace/coverage/default/14.sram_ctrl_alert_test.3218821839 |
|
|
Mar 05 12:54:29 PM PST 24 |
Mar 05 12:54:30 PM PST 24 |
23281192 ps |
| T339 |
/workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.700879224 |
|
|
Mar 05 12:56:35 PM PST 24 |
Mar 05 12:57:48 PM PST 24 |
285235811 ps |
| T340 |
/workspace/coverage/default/23.sram_ctrl_regwen.2971798686 |
|
|
Mar 05 12:55:17 PM PST 24 |
Mar 05 01:10:27 PM PST 24 |
9820455986 ps |
| T341 |
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.87343907 |
|
|
Mar 05 12:53:16 PM PST 24 |
Mar 05 12:57:50 PM PST 24 |
47380973679 ps |
| T342 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.2226354420 |
|
|
Mar 05 12:55:54 PM PST 24 |
Mar 05 12:55:55 PM PST 24 |
30450374 ps |
| T343 |
/workspace/coverage/default/34.sram_ctrl_bijection.3234774202 |
|
|
Mar 05 12:56:35 PM PST 24 |
Mar 05 12:57:31 PM PST 24 |
10444572554 ps |
| T344 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.92837388 |
|
|
Mar 05 12:55:36 PM PST 24 |
Mar 05 12:55:37 PM PST 24 |
57226282 ps |
| T345 |
/workspace/coverage/default/10.sram_ctrl_mem_walk.467323609 |
|
|
Mar 05 12:53:52 PM PST 24 |
Mar 05 12:54:02 PM PST 24 |
2264968977 ps |
| T346 |
/workspace/coverage/default/21.sram_ctrl_alert_test.2115286171 |
|
|
Mar 05 12:55:14 PM PST 24 |
Mar 05 12:55:15 PM PST 24 |
33250079 ps |
| T347 |
/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.118851832 |
|
|
Mar 05 12:56:28 PM PST 24 |
Mar 05 01:04:36 PM PST 24 |
3075834684 ps |
| T348 |
/workspace/coverage/default/20.sram_ctrl_bijection.4004164932 |
|
|
Mar 05 12:55:00 PM PST 24 |
Mar 05 12:55:43 PM PST 24 |
2090042103 ps |
| T349 |
/workspace/coverage/default/16.sram_ctrl_mem_walk.2645981648 |
|
|
Mar 05 12:54:44 PM PST 24 |
Mar 05 12:54:54 PM PST 24 |
579976337 ps |
| T350 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.2427045140 |
|
|
Mar 05 12:55:25 PM PST 24 |
Mar 05 12:55:26 PM PST 24 |
127405181 ps |
| T351 |
/workspace/coverage/default/30.sram_ctrl_smoke.2389187962 |
|
|
Mar 05 12:56:04 PM PST 24 |
Mar 05 12:56:30 PM PST 24 |
2646434326 ps |
| T352 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.1577745371 |
|
|
Mar 05 12:57:57 PM PST 24 |
Mar 05 12:58:11 PM PST 24 |
742425228 ps |
| T353 |
/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.2097548757 |
|
|
Mar 05 12:56:01 PM PST 24 |
Mar 05 12:56:52 PM PST 24 |
534681979 ps |
| T354 |
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3154213167 |
|
|
Mar 05 12:56:36 PM PST 24 |
Mar 05 12:56:49 PM PST 24 |
1419369630 ps |
| T355 |
/workspace/coverage/default/13.sram_ctrl_alert_test.2993560509 |
|
|
Mar 05 12:54:20 PM PST 24 |
Mar 05 12:54:20 PM PST 24 |
32610727 ps |
| T356 |
/workspace/coverage/default/37.sram_ctrl_smoke.2983823365 |
|
|
Mar 05 12:56:55 PM PST 24 |
Mar 05 12:57:10 PM PST 24 |
1745753659 ps |
| T357 |
/workspace/coverage/default/29.sram_ctrl_stress_all.754417977 |
|
|
Mar 05 12:56:01 PM PST 24 |
Mar 05 01:36:07 PM PST 24 |
47930928631 ps |
| T358 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.3644660655 |
|
|
Mar 05 12:56:26 PM PST 24 |
Mar 05 12:59:19 PM PST 24 |
19503881063 ps |
| T359 |
/workspace/coverage/default/32.sram_ctrl_stress_pipeline.2525659634 |
|
|
Mar 05 12:56:26 PM PST 24 |
Mar 05 01:00:55 PM PST 24 |
11925427779 ps |
| T360 |
/workspace/coverage/default/39.sram_ctrl_lc_escalation.2996133154 |
|
|
Mar 05 12:57:17 PM PST 24 |
Mar 05 12:57:19 PM PST 24 |
141304917 ps |
| T361 |
/workspace/coverage/default/36.sram_ctrl_bijection.664111815 |
|
|
Mar 05 12:56:55 PM PST 24 |
Mar 05 12:57:49 PM PST 24 |
923899665 ps |
| T362 |
/workspace/coverage/default/25.sram_ctrl_max_throughput.779191000 |
|
|
Mar 05 12:55:40 PM PST 24 |
Mar 05 12:56:37 PM PST 24 |
112864288 ps |
| T363 |
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.1804225921 |
|
|
Mar 05 12:54:27 PM PST 24 |
Mar 05 12:54:29 PM PST 24 |
54703059 ps |
| T364 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.3960509567 |
|
|
Mar 05 12:53:10 PM PST 24 |
Mar 05 12:54:06 PM PST 24 |
7884986882 ps |
| T365 |
/workspace/coverage/default/14.sram_ctrl_smoke.1604655620 |
|
|
Mar 05 12:54:15 PM PST 24 |
Mar 05 12:54:33 PM PST 24 |
3521743626 ps |
| T366 |
/workspace/coverage/default/36.sram_ctrl_mem_walk.3198444412 |
|
|
Mar 05 12:56:55 PM PST 24 |
Mar 05 12:57:05 PM PST 24 |
6347535463 ps |
| T367 |
/workspace/coverage/default/30.sram_ctrl_lc_escalation.2647885104 |
|
|
Mar 05 12:55:59 PM PST 24 |
Mar 05 12:56:17 PM PST 24 |
1512923946 ps |
| T368 |
/workspace/coverage/default/28.sram_ctrl_executable.2964039500 |
|
|
Mar 05 12:55:50 PM PST 24 |
Mar 05 01:08:47 PM PST 24 |
37607810049 ps |
| T369 |
/workspace/coverage/default/12.sram_ctrl_ram_cfg.986931884 |
|
|
Mar 05 12:54:05 PM PST 24 |
Mar 05 12:54:07 PM PST 24 |
34023537 ps |
| T370 |
/workspace/coverage/default/44.sram_ctrl_smoke.4055011269 |
|
|
Mar 05 12:57:57 PM PST 24 |
Mar 05 12:58:23 PM PST 24 |
1301722861 ps |
| T371 |
/workspace/coverage/default/40.sram_ctrl_mem_walk.215496435 |
|
|
Mar 05 12:57:43 PM PST 24 |
Mar 05 12:57:52 PM PST 24 |
279390590 ps |
| T372 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.2573608705 |
|
|
Mar 05 12:55:11 PM PST 24 |
Mar 05 12:55:28 PM PST 24 |
273568314 ps |
| T373 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.1991718286 |
|
|
Mar 05 12:56:08 PM PST 24 |
Mar 05 01:03:07 PM PST 24 |
4681239195 ps |
| T374 |
/workspace/coverage/default/46.sram_ctrl_alert_test.4105847432 |
|
|
Mar 05 12:58:09 PM PST 24 |
Mar 05 12:58:10 PM PST 24 |
24720186 ps |
| T375 |
/workspace/coverage/default/49.sram_ctrl_alert_test.1647792354 |
|
|
Mar 05 12:58:41 PM PST 24 |
Mar 05 12:58:41 PM PST 24 |
16889248 ps |
| T376 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.1343916608 |
|
|
Mar 05 12:57:16 PM PST 24 |
Mar 05 01:15:51 PM PST 24 |
2592803737 ps |
| T377 |
/workspace/coverage/default/5.sram_ctrl_mem_walk.2921838092 |
|
|
Mar 05 12:53:12 PM PST 24 |
Mar 05 12:53:17 PM PST 24 |
72118068 ps |
| T378 |
/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.730024318 |
|
|
Mar 05 12:55:37 PM PST 24 |
Mar 05 12:58:49 PM PST 24 |
3319718676 ps |
| T379 |
/workspace/coverage/default/23.sram_ctrl_ram_cfg.3403186060 |
|
|
Mar 05 12:55:19 PM PST 24 |
Mar 05 12:55:20 PM PST 24 |
229457731 ps |
| T380 |
/workspace/coverage/default/17.sram_ctrl_mem_partial_access.3831677573 |
|
|
Mar 05 12:54:45 PM PST 24 |
Mar 05 12:54:49 PM PST 24 |
65399875 ps |
| T381 |
/workspace/coverage/default/49.sram_ctrl_lc_escalation.426808133 |
|
|
Mar 05 12:58:39 PM PST 24 |
Mar 05 12:58:49 PM PST 24 |
648201832 ps |
| T382 |
/workspace/coverage/default/18.sram_ctrl_executable.2956322476 |
|
|
Mar 05 12:54:56 PM PST 24 |
Mar 05 01:00:22 PM PST 24 |
4370209341 ps |
| T383 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2232682435 |
|
|
Mar 05 12:53:49 PM PST 24 |
Mar 05 12:53:53 PM PST 24 |
419854034 ps |
| T384 |
/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.3193605995 |
|
|
Mar 05 12:57:15 PM PST 24 |
Mar 05 01:03:18 PM PST 24 |
21014847453 ps |
| T385 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.1335905245 |
|
|
Mar 05 12:54:52 PM PST 24 |
Mar 05 12:55:11 PM PST 24 |
114719907 ps |
| T386 |
/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.43128188 |
|
|
Mar 05 12:55:19 PM PST 24 |
Mar 05 12:56:05 PM PST 24 |
446364072 ps |
| T387 |
/workspace/coverage/default/42.sram_ctrl_alert_test.1693837118 |
|
|
Mar 05 12:57:55 PM PST 24 |
Mar 05 12:57:56 PM PST 24 |
23697179 ps |
| T388 |
/workspace/coverage/default/24.sram_ctrl_alert_test.3508675848 |
|
|
Mar 05 12:55:38 PM PST 24 |
Mar 05 12:55:39 PM PST 24 |
22540343 ps |
| T389 |
/workspace/coverage/default/13.sram_ctrl_executable.3861710402 |
|
|
Mar 05 12:54:05 PM PST 24 |
Mar 05 01:10:28 PM PST 24 |
14513009505 ps |
| T390 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.1390277396 |
|
|
Mar 05 12:55:10 PM PST 24 |
Mar 05 12:55:15 PM PST 24 |
103966847 ps |
| T391 |
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.4153759297 |
|
|
Mar 05 12:58:41 PM PST 24 |
Mar 05 01:00:57 PM PST 24 |
8135975922 ps |
| T392 |
/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.2833363745 |
|
|
Mar 05 12:56:27 PM PST 24 |
Mar 05 12:56:54 PM PST 24 |
98942457 ps |
| T393 |
/workspace/coverage/default/47.sram_ctrl_partial_access.2494665235 |
|
|
Mar 05 12:58:13 PM PST 24 |
Mar 05 12:58:58 PM PST 24 |
141061532 ps |
| T394 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.3584515070 |
|
|
Mar 05 12:54:57 PM PST 24 |
Mar 05 12:54:59 PM PST 24 |
60298385 ps |
| T395 |
/workspace/coverage/default/22.sram_ctrl_executable.3830908405 |
|
|
Mar 05 12:55:10 PM PST 24 |
Mar 05 12:57:43 PM PST 24 |
12779750873 ps |
| T396 |
/workspace/coverage/default/39.sram_ctrl_max_throughput.1930578132 |
|
|
Mar 05 12:57:16 PM PST 24 |
Mar 05 12:58:18 PM PST 24 |
239315333 ps |
| T397 |
/workspace/coverage/default/28.sram_ctrl_multiple_keys.2453192232 |
|
|
Mar 05 12:55:44 PM PST 24 |
Mar 05 01:00:01 PM PST 24 |
3937014603 ps |
| T398 |
/workspace/coverage/default/27.sram_ctrl_ram_cfg.4153078253 |
|
|
Mar 05 12:55:45 PM PST 24 |
Mar 05 12:55:46 PM PST 24 |
69631350 ps |
| T399 |
/workspace/coverage/default/37.sram_ctrl_partial_access.3727775951 |
|
|
Mar 05 12:57:03 PM PST 24 |
Mar 05 12:57:11 PM PST 24 |
267933642 ps |
| T400 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.733973472 |
|
|
Mar 05 12:58:19 PM PST 24 |
Mar 05 01:01:00 PM PST 24 |
1067996240 ps |
| T401 |
/workspace/coverage/default/16.sram_ctrl_alert_test.1128088378 |
|
|
Mar 05 12:54:42 PM PST 24 |
Mar 05 12:54:43 PM PST 24 |
36498094 ps |
| T402 |
/workspace/coverage/default/19.sram_ctrl_alert_test.2258368643 |
|
|
Mar 05 12:54:53 PM PST 24 |
Mar 05 12:54:54 PM PST 24 |
60524309 ps |
| T403 |
/workspace/coverage/default/1.sram_ctrl_smoke.253613778 |
|
|
Mar 05 12:52:37 PM PST 24 |
Mar 05 12:53:38 PM PST 24 |
1949601586 ps |
| T404 |
/workspace/coverage/default/42.sram_ctrl_executable.2412675488 |
|
|
Mar 05 12:57:54 PM PST 24 |
Mar 05 01:06:03 PM PST 24 |
9607144264 ps |
| T405 |
/workspace/coverage/default/0.sram_ctrl_regwen.2214115141 |
|
|
Mar 05 12:52:38 PM PST 24 |
Mar 05 01:19:22 PM PST 24 |
17929217942 ps |
| T406 |
/workspace/coverage/default/19.sram_ctrl_ram_cfg.2144033203 |
|
|
Mar 05 12:54:53 PM PST 24 |
Mar 05 12:54:54 PM PST 24 |
31898044 ps |
| T407 |
/workspace/coverage/default/11.sram_ctrl_alert_test.3358025692 |
|
|
Mar 05 12:53:58 PM PST 24 |
Mar 05 12:53:58 PM PST 24 |
13950374 ps |
| T408 |
/workspace/coverage/default/15.sram_ctrl_executable.459976202 |
|
|
Mar 05 12:54:27 PM PST 24 |
Mar 05 01:06:35 PM PST 24 |
10007615445 ps |
| T409 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.1223299940 |
|
|
Mar 05 12:54:02 PM PST 24 |
Mar 05 12:56:51 PM PST 24 |
912995261 ps |
| T410 |
/workspace/coverage/default/39.sram_ctrl_smoke.3724117142 |
|
|
Mar 05 12:57:17 PM PST 24 |
Mar 05 12:57:21 PM PST 24 |
38252283 ps |
| T411 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.781571701 |
|
|
Mar 05 12:56:55 PM PST 24 |
Mar 05 01:15:15 PM PST 24 |
17967988558 ps |
| T412 |
/workspace/coverage/default/11.sram_ctrl_smoke.2865799760 |
|
|
Mar 05 12:53:52 PM PST 24 |
Mar 05 12:55:21 PM PST 24 |
2151916138 ps |
| T413 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.742711973 |
|
|
Mar 05 12:54:53 PM PST 24 |
Mar 05 12:57:31 PM PST 24 |
1828676559 ps |
| T414 |
/workspace/coverage/default/30.sram_ctrl_regwen.1298398452 |
|
|
Mar 05 12:56:09 PM PST 24 |
Mar 05 01:14:17 PM PST 24 |
3284150019 ps |
| T415 |
/workspace/coverage/default/41.sram_ctrl_alert_test.1849129793 |
|
|
Mar 05 12:57:59 PM PST 24 |
Mar 05 12:58:00 PM PST 24 |
32648721 ps |
| T416 |
/workspace/coverage/default/3.sram_ctrl_bijection.2421489311 |
|
|
Mar 05 12:52:57 PM PST 24 |
Mar 05 12:53:33 PM PST 24 |
1744727069 ps |
| T417 |
/workspace/coverage/default/17.sram_ctrl_partial_access.4184576993 |
|
|
Mar 05 12:54:44 PM PST 24 |
Mar 05 12:55:14 PM PST 24 |
150241680 ps |
| T418 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.99237668 |
|
|
Mar 05 12:58:17 PM PST 24 |
Mar 05 01:00:02 PM PST 24 |
172552006 ps |
| T419 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.2519967614 |
|
|
Mar 05 12:57:54 PM PST 24 |
Mar 05 01:02:20 PM PST 24 |
2788221818 ps |
| T420 |
/workspace/coverage/default/17.sram_ctrl_bijection.696286172 |
|
|
Mar 05 12:54:42 PM PST 24 |
Mar 05 12:54:56 PM PST 24 |
230454369 ps |
| T421 |
/workspace/coverage/default/37.sram_ctrl_mem_walk.221357532 |
|
|
Mar 05 12:57:03 PM PST 24 |
Mar 05 12:57:07 PM PST 24 |
75120481 ps |
| T422 |
/workspace/coverage/default/15.sram_ctrl_lc_escalation.774423471 |
|
|
Mar 05 12:54:28 PM PST 24 |
Mar 05 12:54:48 PM PST 24 |
1409078362 ps |
| T423 |
/workspace/coverage/default/0.sram_ctrl_executable.3102852186 |
|
|
Mar 05 12:52:38 PM PST 24 |
Mar 05 12:52:45 PM PST 24 |
242499811 ps |
| T424 |
/workspace/coverage/default/40.sram_ctrl_max_throughput.1484176759 |
|
|
Mar 05 12:57:42 PM PST 24 |
Mar 05 12:58:11 PM PST 24 |
84089286 ps |
| T425 |
/workspace/coverage/default/47.sram_ctrl_smoke.1689691694 |
|
|
Mar 05 12:58:14 PM PST 24 |
Mar 05 12:58:27 PM PST 24 |
223893414 ps |
| T426 |
/workspace/coverage/default/33.sram_ctrl_multiple_keys.3207384632 |
|
|
Mar 05 12:56:26 PM PST 24 |
Mar 05 01:03:28 PM PST 24 |
40556453413 ps |
| T427 |
/workspace/coverage/default/2.sram_ctrl_mem_partial_access.2205627175 |
|
|
Mar 05 12:52:53 PM PST 24 |
Mar 05 12:52:59 PM PST 24 |
712598271 ps |
| T428 |
/workspace/coverage/default/30.sram_ctrl_stress_pipeline.4036652560 |
|
|
Mar 05 12:56:00 PM PST 24 |
Mar 05 01:01:29 PM PST 24 |
7041690109 ps |
| T429 |
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.560908060 |
|
|
Mar 05 12:53:32 PM PST 24 |
Mar 05 12:54:19 PM PST 24 |
1525157878 ps |
| T430 |
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.3657668156 |
|
|
Mar 05 12:56:27 PM PST 24 |
Mar 05 12:59:42 PM PST 24 |
2117198488 ps |
| T431 |
/workspace/coverage/default/33.sram_ctrl_partial_access.2882564994 |
|
|
Mar 05 12:56:25 PM PST 24 |
Mar 05 12:56:40 PM PST 24 |
290459213 ps |
| T432 |
/workspace/coverage/default/5.sram_ctrl_ram_cfg.2893726968 |
|
|
Mar 05 12:53:14 PM PST 24 |
Mar 05 12:53:15 PM PST 24 |
145391793 ps |
| T433 |
/workspace/coverage/default/41.sram_ctrl_partial_access.3158120071 |
|
|
Mar 05 12:57:42 PM PST 24 |
Mar 05 12:57:46 PM PST 24 |
119109244 ps |
| T434 |
/workspace/coverage/default/31.sram_ctrl_regwen.1171878042 |
|
|
Mar 05 12:56:17 PM PST 24 |
Mar 05 01:08:16 PM PST 24 |
32681366521 ps |
| T435 |
/workspace/coverage/default/49.sram_ctrl_smoke.3193296509 |
|
|
Mar 05 12:58:28 PM PST 24 |
Mar 05 12:58:39 PM PST 24 |
182086561 ps |
| T436 |
/workspace/coverage/default/5.sram_ctrl_partial_access.696052316 |
|
|
Mar 05 12:53:14 PM PST 24 |
Mar 05 12:53:31 PM PST 24 |
10058191337 ps |
| T437 |
/workspace/coverage/default/41.sram_ctrl_stress_all.1886963972 |
|
|
Mar 05 12:57:58 PM PST 24 |
Mar 05 01:35:30 PM PST 24 |
375290815620 ps |
| T438 |
/workspace/coverage/default/29.sram_ctrl_multiple_keys.1021351783 |
|
|
Mar 05 12:55:52 PM PST 24 |
Mar 05 01:00:14 PM PST 24 |
3324488468 ps |
| T439 |
/workspace/coverage/default/0.sram_ctrl_smoke.3788448468 |
|
|
Mar 05 12:52:36 PM PST 24 |
Mar 05 12:52:50 PM PST 24 |
1530088641 ps |
| T440 |
/workspace/coverage/default/5.sram_ctrl_stress_all.2408154475 |
|
|
Mar 05 12:53:23 PM PST 24 |
Mar 05 01:22:36 PM PST 24 |
34947758451 ps |
| T112 |
/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.1346325541 |
|
|
Mar 05 12:55:15 PM PST 24 |
Mar 05 12:58:42 PM PST 24 |
3056435503 ps |
| T441 |
/workspace/coverage/default/19.sram_ctrl_mem_walk.4288581985 |
|
|
Mar 05 12:54:55 PM PST 24 |
Mar 05 12:55:01 PM PST 24 |
938443389 ps |
| T442 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.1359664896 |
|
|
Mar 05 12:53:41 PM PST 24 |
Mar 05 12:53:44 PM PST 24 |
164539182 ps |
| T443 |
/workspace/coverage/default/20.sram_ctrl_lc_escalation.3988467031 |
|
|
Mar 05 12:55:00 PM PST 24 |
Mar 05 12:55:12 PM PST 24 |
803424134 ps |
| T444 |
/workspace/coverage/default/42.sram_ctrl_stress_all.3380326751 |
|
|
Mar 05 12:57:55 PM PST 24 |
Mar 05 01:27:56 PM PST 24 |
25449932569 ps |
| T445 |
/workspace/coverage/default/38.sram_ctrl_smoke.2840403179 |
|
|
Mar 05 12:57:04 PM PST 24 |
Mar 05 12:57:34 PM PST 24 |
1321570160 ps |
| T446 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.850691972 |
|
|
Mar 05 12:55:01 PM PST 24 |
Mar 05 12:55:02 PM PST 24 |
27633566 ps |
| T447 |
/workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.1071881921 |
|
|
Mar 05 12:55:29 PM PST 24 |
Mar 05 12:55:35 PM PST 24 |
174584399 ps |
| T448 |
/workspace/coverage/default/2.sram_ctrl_smoke.1797653510 |
|
|
Mar 05 12:52:49 PM PST 24 |
Mar 05 12:53:20 PM PST 24 |
1010031188 ps |
| T449 |
/workspace/coverage/default/18.sram_ctrl_smoke.2840520710 |
|
|
Mar 05 12:54:57 PM PST 24 |
Mar 05 12:55:45 PM PST 24 |
447464783 ps |
| T450 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.1593392717 |
|
|
Mar 05 12:54:08 PM PST 24 |
Mar 05 12:54:09 PM PST 24 |
35855100 ps |
| T451 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.1598474790 |
|
|
Mar 05 12:54:54 PM PST 24 |
Mar 05 01:15:52 PM PST 24 |
15109012666 ps |
| T452 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.1530075737 |
|
|
Mar 05 12:55:10 PM PST 24 |
Mar 05 12:57:53 PM PST 24 |
9043646410 ps |
| T453 |
/workspace/coverage/default/14.sram_ctrl_stress_all.3597027962 |
|
|
Mar 05 12:54:28 PM PST 24 |
Mar 05 01:23:54 PM PST 24 |
45785103954 ps |
| T454 |
/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.1035025920 |
|
|
Mar 05 12:53:10 PM PST 24 |
Mar 05 12:54:58 PM PST 24 |
147161246 ps |
| T455 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.390752767 |
|
|
Mar 05 12:53:49 PM PST 24 |
Mar 05 12:59:29 PM PST 24 |
14051657301 ps |
| T456 |
/workspace/coverage/default/46.sram_ctrl_bijection.1518065767 |
|
|
Mar 05 12:58:11 PM PST 24 |
Mar 05 12:59:03 PM PST 24 |
11764362715 ps |
| T457 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.3434009009 |
|
|
Mar 05 12:54:26 PM PST 24 |
Mar 05 12:55:51 PM PST 24 |
4915563262 ps |
| T458 |
/workspace/coverage/default/4.sram_ctrl_alert_test.261422231 |
|
|
Mar 05 12:53:09 PM PST 24 |
Mar 05 12:53:10 PM PST 24 |
37988304 ps |
| T459 |
/workspace/coverage/default/39.sram_ctrl_partial_access.3051707289 |
|
|
Mar 05 12:57:15 PM PST 24 |
Mar 05 12:59:29 PM PST 24 |
345715108 ps |
| T460 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.1864759666 |
|
|
Mar 05 12:58:40 PM PST 24 |
Mar 05 01:03:03 PM PST 24 |
2681942363 ps |
| T461 |
/workspace/coverage/default/6.sram_ctrl_alert_test.425584135 |
|
|
Mar 05 12:53:22 PM PST 24 |
Mar 05 12:53:24 PM PST 24 |
37198772 ps |
| T462 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.170464915 |
|
|
Mar 05 12:56:37 PM PST 24 |
Mar 05 01:20:33 PM PST 24 |
3694799743 ps |
| T463 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.3044044957 |
|
|
Mar 05 12:54:17 PM PST 24 |
Mar 05 12:54:25 PM PST 24 |
522265592 ps |
| T464 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.835544050 |
|
|
Mar 05 12:54:44 PM PST 24 |
Mar 05 12:58:14 PM PST 24 |
8108022574 ps |
| T465 |
/workspace/coverage/default/34.sram_ctrl_stress_all.2312441262 |
|
|
Mar 05 12:56:44 PM PST 24 |
Mar 05 02:09:30 PM PST 24 |
36183381043 ps |
| T466 |
/workspace/coverage/default/29.sram_ctrl_alert_test.3391748532 |
|
|
Mar 05 12:56:01 PM PST 24 |
Mar 05 12:56:02 PM PST 24 |
44302049 ps |
| T467 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.3070447931 |
|
|
Mar 05 12:54:28 PM PST 24 |
Mar 05 12:55:48 PM PST 24 |
166952758 ps |
| T468 |
/workspace/coverage/default/39.sram_ctrl_stress_pipeline.3253611685 |
|
|
Mar 05 12:57:16 PM PST 24 |
Mar 05 12:59:11 PM PST 24 |
1177076538 ps |
| T469 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.1232387340 |
|
|
Mar 05 12:56:55 PM PST 24 |
Mar 05 01:07:55 PM PST 24 |
54603709367 ps |
| T470 |
/workspace/coverage/default/20.sram_ctrl_alert_test.2846239115 |
|
|
Mar 05 12:55:02 PM PST 24 |
Mar 05 12:55:02 PM PST 24 |
53498213 ps |
| T471 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.3794671661 |
|
|
Mar 05 12:53:05 PM PST 24 |
Mar 05 12:53:36 PM PST 24 |
360805997 ps |
| T472 |
/workspace/coverage/default/39.sram_ctrl_stress_all.2367271944 |
|
|
Mar 05 12:57:42 PM PST 24 |
Mar 05 01:29:08 PM PST 24 |
115364904093 ps |
| T473 |
/workspace/coverage/default/32.sram_ctrl_ram_cfg.2967024214 |
|
|
Mar 05 12:56:16 PM PST 24 |
Mar 05 12:56:17 PM PST 24 |
50688812 ps |
| T474 |
/workspace/coverage/default/12.sram_ctrl_partial_access.1507463764 |
|
|
Mar 05 12:54:02 PM PST 24 |
Mar 05 12:54:21 PM PST 24 |
3995550330 ps |
| T475 |
/workspace/coverage/default/22.sram_ctrl_stress_all.675087390 |
|
|
Mar 05 12:55:23 PM PST 24 |
Mar 05 01:13:33 PM PST 24 |
25627605056 ps |
| T476 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.1229431723 |
|
|
Mar 05 12:53:14 PM PST 24 |
Mar 05 12:53:16 PM PST 24 |
155289860 ps |
| T477 |
/workspace/coverage/default/28.sram_ctrl_stress_pipeline.258565330 |
|
|
Mar 05 12:55:46 PM PST 24 |
Mar 05 12:58:50 PM PST 24 |
7896037929 ps |
| T478 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.3714951300 |
|
|
Mar 05 12:54:18 PM PST 24 |
Mar 05 12:54:43 PM PST 24 |
1190780634 ps |
| T479 |
/workspace/coverage/default/0.sram_ctrl_partial_access.3730015996 |
|
|
Mar 05 12:52:37 PM PST 24 |
Mar 05 12:53:23 PM PST 24 |
187000780 ps |
| T480 |
/workspace/coverage/default/44.sram_ctrl_max_throughput.65617059 |
|
|
Mar 05 12:58:00 PM PST 24 |
Mar 05 12:58:30 PM PST 24 |
566271492 ps |
| T481 |
/workspace/coverage/default/4.sram_ctrl_smoke.3910166242 |
|
|
Mar 05 12:53:03 PM PST 24 |
Mar 05 12:53:16 PM PST 24 |
3200005994 ps |
| T482 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.3295225771 |
|
|
Mar 05 12:58:40 PM PST 24 |
Mar 05 12:58:49 PM PST 24 |
62519576 ps |
| T483 |
/workspace/coverage/default/35.sram_ctrl_alert_test.573396742 |
|
|
Mar 05 12:56:46 PM PST 24 |
Mar 05 12:56:48 PM PST 24 |
27060539 ps |
| T484 |
/workspace/coverage/default/17.sram_ctrl_smoke.4026779746 |
|
|
Mar 05 12:54:44 PM PST 24 |
Mar 05 12:54:48 PM PST 24 |
203255172 ps |
| T485 |
/workspace/coverage/default/41.sram_ctrl_regwen.310816448 |
|
|
Mar 05 12:57:56 PM PST 24 |
Mar 05 01:10:14 PM PST 24 |
11287668399 ps |
| T486 |
/workspace/coverage/default/18.sram_ctrl_lc_escalation.2618079533 |
|
|
Mar 05 12:54:54 PM PST 24 |
Mar 05 12:55:15 PM PST 24 |
1805301914 ps |
| T487 |
/workspace/coverage/default/38.sram_ctrl_executable.1004206813 |
|
|
Mar 05 12:57:14 PM PST 24 |
Mar 05 01:19:49 PM PST 24 |
52422923577 ps |
| T488 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.3152628089 |
|
|
Mar 05 12:57:04 PM PST 24 |
Mar 05 12:57:07 PM PST 24 |
85030878 ps |
| T489 |
/workspace/coverage/default/17.sram_ctrl_alert_test.2782927969 |
|
|
Mar 05 12:54:55 PM PST 24 |
Mar 05 12:54:56 PM PST 24 |
33295197 ps |
| T490 |
/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.3807727686 |
|
|
Mar 05 12:52:58 PM PST 24 |
Mar 05 12:57:36 PM PST 24 |
13784128902 ps |
| T491 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.2947499007 |
|
|
Mar 05 12:58:23 PM PST 24 |
Mar 05 12:59:05 PM PST 24 |
186315689 ps |
| T492 |
/workspace/coverage/default/20.sram_ctrl_partial_access.789820557 |
|
|
Mar 05 12:55:00 PM PST 24 |
Mar 05 12:55:19 PM PST 24 |
1110472918 ps |
| T493 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.4155524160 |
|
|
Mar 05 12:54:05 PM PST 24 |
Mar 05 12:54:10 PM PST 24 |
231787924 ps |
| T494 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.60544580 |
|
|
Mar 05 12:53:40 PM PST 24 |
Mar 05 12:53:41 PM PST 24 |
54626023 ps |
| T495 |
/workspace/coverage/default/36.sram_ctrl_alert_test.1523308343 |
|
|
Mar 05 12:56:54 PM PST 24 |
Mar 05 12:56:54 PM PST 24 |
10933311 ps |
| T496 |
/workspace/coverage/default/27.sram_ctrl_mem_partial_access.749114794 |
|
|
Mar 05 12:55:43 PM PST 24 |
Mar 05 12:55:46 PM PST 24 |
446626729 ps |
| T497 |
/workspace/coverage/default/48.sram_ctrl_mem_walk.2408728240 |
|
|
Mar 05 12:58:29 PM PST 24 |
Mar 05 12:58:39 PM PST 24 |
1760133625 ps |
| T498 |
/workspace/coverage/default/26.sram_ctrl_regwen.555768501 |
|
|
Mar 05 12:55:36 PM PST 24 |
Mar 05 01:15:32 PM PST 24 |
108927167609 ps |
| T499 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.1863303697 |
|
|
Mar 05 12:53:34 PM PST 24 |
Mar 05 12:56:41 PM PST 24 |
2138610049 ps |
| T500 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.803636218 |
|
|
Mar 05 12:57:52 PM PST 24 |
Mar 05 12:58:32 PM PST 24 |
113731025 ps |
| T501 |
/workspace/coverage/default/41.sram_ctrl_bijection.4135240495 |
|
|
Mar 05 12:57:45 PM PST 24 |
Mar 05 12:58:11 PM PST 24 |
15267118238 ps |
| T502 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.4152225585 |
|
|
Mar 05 12:54:05 PM PST 24 |
Mar 05 12:54:41 PM PST 24 |
9132401434 ps |
| T503 |
/workspace/coverage/default/26.sram_ctrl_smoke.3622459398 |
|
|
Mar 05 12:55:38 PM PST 24 |
Mar 05 12:55:51 PM PST 24 |
370876048 ps |
| T504 |
/workspace/coverage/default/4.sram_ctrl_executable.2815696660 |
|
|
Mar 05 12:53:09 PM PST 24 |
Mar 05 01:17:41 PM PST 24 |
4992384141 ps |
| T505 |
/workspace/coverage/default/33.sram_ctrl_mem_walk.3531920541 |
|
|
Mar 05 12:56:29 PM PST 24 |
Mar 05 12:56:40 PM PST 24 |
8075296346 ps |
| T506 |
/workspace/coverage/default/15.sram_ctrl_partial_access.2796503969 |
|
|
Mar 05 12:54:30 PM PST 24 |
Mar 05 12:54:52 PM PST 24 |
132193802 ps |
| T507 |
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.1966827556 |
|
|
Mar 05 12:57:42 PM PST 24 |
Mar 05 01:01:52 PM PST 24 |
13530291442 ps |
| T508 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.1944386560 |
|
|
Mar 05 12:54:17 PM PST 24 |
Mar 05 12:54:25 PM PST 24 |
138991650 ps |
| T509 |
/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.2038010059 |
|
|
Mar 05 12:56:17 PM PST 24 |
Mar 05 12:57:21 PM PST 24 |
883672012 ps |
| T510 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.1889634073 |
|
|
Mar 05 12:53:23 PM PST 24 |
Mar 05 12:53:26 PM PST 24 |
189157962 ps |
| T511 |
/workspace/coverage/default/11.sram_ctrl_regwen.3411875323 |
|
|
Mar 05 12:53:58 PM PST 24 |
Mar 05 01:16:17 PM PST 24 |
17546255338 ps |
| T512 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.1761469003 |
|
|
Mar 05 12:53:10 PM PST 24 |
Mar 05 12:53:11 PM PST 24 |
54307455 ps |
| T513 |
/workspace/coverage/default/46.sram_ctrl_mem_walk.1343765132 |
|
|
Mar 05 12:58:11 PM PST 24 |
Mar 05 12:58:21 PM PST 24 |
1004329743 ps |
| T514 |
/workspace/coverage/default/3.sram_ctrl_ram_cfg.56092059 |
|
|
Mar 05 12:53:00 PM PST 24 |
Mar 05 12:53:01 PM PST 24 |
81127879 ps |
| T515 |
/workspace/coverage/default/43.sram_ctrl_smoke.1569535066 |
|
|
Mar 05 12:57:55 PM PST 24 |
Mar 05 12:58:10 PM PST 24 |
1727428460 ps |
| T516 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.3919268051 |
|
|
Mar 05 12:54:51 PM PST 24 |
Mar 05 12:55:26 PM PST 24 |
98990861 ps |
| T517 |
/workspace/coverage/default/31.sram_ctrl_alert_test.1612710344 |
|
|
Mar 05 12:56:24 PM PST 24 |
Mar 05 12:56:25 PM PST 24 |
33362474 ps |
| T518 |
/workspace/coverage/default/31.sram_ctrl_bijection.3814763702 |
|
|
Mar 05 12:56:10 PM PST 24 |
Mar 05 12:56:59 PM PST 24 |
9661498212 ps |
| T519 |
/workspace/coverage/default/20.sram_ctrl_regwen.1645908987 |
|
|
Mar 05 12:55:05 PM PST 24 |
Mar 05 01:09:46 PM PST 24 |
14634685095 ps |
| T520 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.75599621 |
|
|
Mar 05 12:53:22 PM PST 24 |
Mar 05 12:53:23 PM PST 24 |
28893591 ps |
| T521 |
/workspace/coverage/default/13.sram_ctrl_regwen.2163017110 |
|
|
Mar 05 12:54:11 PM PST 24 |
Mar 05 12:58:26 PM PST 24 |
2488524581 ps |
| T92 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.1977807249 |
|
|
Mar 05 12:56:11 PM PST 24 |
Mar 05 12:56:14 PM PST 24 |
43145113 ps |
| T522 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.4264729520 |
|
|
Mar 05 12:53:48 PM PST 24 |
Mar 05 12:54:44 PM PST 24 |
432098035 ps |
| T523 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.2499811022 |
|
|
Mar 05 12:56:10 PM PST 24 |
Mar 05 01:07:55 PM PST 24 |
12393205916 ps |
| T524 |
/workspace/coverage/default/45.sram_ctrl_bijection.3656555346 |
|
|
Mar 05 12:58:03 PM PST 24 |
Mar 05 12:58:31 PM PST 24 |
434849465 ps |
| T525 |
/workspace/coverage/default/18.sram_ctrl_regwen.1097158766 |
|
|
Mar 05 12:54:51 PM PST 24 |
Mar 05 01:03:44 PM PST 24 |
9489609892 ps |
| T113 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.2086241213 |
|
|
Mar 05 12:55:02 PM PST 24 |
Mar 05 12:59:26 PM PST 24 |
6844598055 ps |
| T526 |
/workspace/coverage/default/28.sram_ctrl_partial_access.4085281842 |
|
|
Mar 05 12:55:47 PM PST 24 |
Mar 05 12:56:23 PM PST 24 |
578104439 ps |
| T527 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.1915827204 |
|
|
Mar 05 12:56:09 PM PST 24 |
Mar 05 12:56:10 PM PST 24 |
30536841 ps |
| T528 |
/workspace/coverage/default/16.sram_ctrl_mem_partial_access.184886731 |
|
|
Mar 05 12:54:44 PM PST 24 |
Mar 05 12:54:48 PM PST 24 |
246686787 ps |
| T529 |
/workspace/coverage/default/2.sram_ctrl_alert_test.1480185125 |
|
|
Mar 05 12:52:52 PM PST 24 |
Mar 05 12:52:53 PM PST 24 |
12311221 ps |
| T530 |
/workspace/coverage/default/49.sram_ctrl_executable.3307975894 |
|
|
Mar 05 12:58:43 PM PST 24 |
Mar 05 01:02:08 PM PST 24 |
5257774161 ps |
| T531 |
/workspace/coverage/default/33.sram_ctrl_max_throughput.1241606773 |
|
|
Mar 05 12:56:27 PM PST 24 |
Mar 05 12:58:03 PM PST 24 |
224580203 ps |
| T532 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.1937414263 |
|
|
Mar 05 12:55:38 PM PST 24 |
Mar 05 12:55:47 PM PST 24 |
140287628 ps |
| T533 |
/workspace/coverage/default/27.sram_ctrl_executable.1345477926 |
|
|
Mar 05 12:57:13 PM PST 24 |
Mar 05 01:04:45 PM PST 24 |
2083301860 ps |
| T534 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.3960690583 |
|
|
Mar 05 12:52:39 PM PST 24 |
Mar 05 12:52:55 PM PST 24 |
1296680829 ps |
| T535 |
/workspace/coverage/default/44.sram_ctrl_executable.4010841282 |
|
|
Mar 05 12:58:06 PM PST 24 |
Mar 05 01:13:57 PM PST 24 |
41012958890 ps |
| T536 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3307582209 |
|
|
Mar 05 12:57:53 PM PST 24 |
Mar 05 01:04:16 PM PST 24 |
97297032305 ps |
| T537 |
/workspace/coverage/default/32.sram_ctrl_regwen.475708577 |
|
|
Mar 05 12:56:17 PM PST 24 |
Mar 05 01:01:33 PM PST 24 |
1289812345 ps |
| T538 |
/workspace/coverage/default/24.sram_ctrl_mem_partial_access.3717548125 |
|
|
Mar 05 12:55:26 PM PST 24 |
Mar 05 12:55:29 PM PST 24 |
47410068 ps |
| T19 |
/workspace/coverage/default/4.sram_ctrl_sec_cm.3859160897 |
|
|
Mar 05 12:53:03 PM PST 24 |
Mar 05 12:53:05 PM PST 24 |
250083274 ps |
| T539 |
/workspace/coverage/default/3.sram_ctrl_alert_test.3502991380 |
|
|
Mar 05 12:53:02 PM PST 24 |
Mar 05 12:53:03 PM PST 24 |
13579436 ps |
| T540 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.1507315268 |
|
|
Mar 05 12:54:29 PM PST 24 |
Mar 05 12:54:32 PM PST 24 |
47395212 ps |
| T541 |
/workspace/coverage/default/49.sram_ctrl_bijection.1125284323 |
|
|
Mar 05 12:58:30 PM PST 24 |
Mar 05 12:59:08 PM PST 24 |
2138214424 ps |
| T542 |
/workspace/coverage/default/25.sram_ctrl_executable.1197221041 |
|
|
Mar 05 12:55:38 PM PST 24 |
Mar 05 01:05:37 PM PST 24 |
1850738953 ps |
| T543 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.1227804862 |
|
|
Mar 05 12:58:00 PM PST 24 |
Mar 05 12:58:15 PM PST 24 |
240437607 ps |
| T544 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.4189169594 |
|
|
Mar 05 12:53:30 PM PST 24 |
Mar 05 12:53:33 PM PST 24 |
631520413 ps |
| T545 |
/workspace/coverage/default/1.sram_ctrl_multiple_keys.548796684 |
|
|
Mar 05 12:52:39 PM PST 24 |
Mar 05 01:10:45 PM PST 24 |
14277855387 ps |
| T546 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.1258344032 |
|
|
Mar 05 12:57:41 PM PST 24 |
Mar 05 12:57:42 PM PST 24 |
29585180 ps |