| T547 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.926021167 |
|
|
Mar 05 12:56:55 PM PST 24 |
Mar 05 12:57:01 PM PST 24 |
57194585 ps |
| T548 |
/workspace/coverage/default/13.sram_ctrl_partial_access.3980412252 |
|
|
Mar 05 12:54:06 PM PST 24 |
Mar 05 12:55:35 PM PST 24 |
2441349683 ps |
| T549 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.858735719 |
|
|
Mar 05 12:53:33 PM PST 24 |
Mar 05 12:53:34 PM PST 24 |
70157612 ps |
| T550 |
/workspace/coverage/default/7.sram_ctrl_alert_test.3354375711 |
|
|
Mar 05 12:53:39 PM PST 24 |
Mar 05 12:53:40 PM PST 24 |
35887232 ps |
| T551 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.598206729 |
|
|
Mar 05 12:55:11 PM PST 24 |
Mar 05 12:55:15 PM PST 24 |
182911826 ps |
| T552 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.3472567601 |
|
|
Mar 05 12:55:02 PM PST 24 |
Mar 05 12:56:10 PM PST 24 |
127667303 ps |
| T553 |
/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.3954613460 |
|
|
Mar 05 12:55:51 PM PST 24 |
Mar 05 12:59:35 PM PST 24 |
21969735149 ps |
| T554 |
/workspace/coverage/default/39.sram_ctrl_regwen.4084998527 |
|
|
Mar 05 12:57:15 PM PST 24 |
Mar 05 12:57:56 PM PST 24 |
1426559378 ps |
| T555 |
/workspace/coverage/default/1.sram_ctrl_max_throughput.2706791792 |
|
|
Mar 05 12:52:39 PM PST 24 |
Mar 05 12:53:18 PM PST 24 |
176295796 ps |
| T556 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.2493491209 |
|
|
Mar 05 12:58:02 PM PST 24 |
Mar 05 12:58:13 PM PST 24 |
649388720 ps |
| T557 |
/workspace/coverage/default/34.sram_ctrl_executable.45673470 |
|
|
Mar 05 12:56:41 PM PST 24 |
Mar 05 01:10:47 PM PST 24 |
9299905485 ps |
| T558 |
/workspace/coverage/default/16.sram_ctrl_smoke.399117423 |
|
|
Mar 05 12:54:29 PM PST 24 |
Mar 05 12:56:28 PM PST 24 |
633350696 ps |
| T559 |
/workspace/coverage/default/45.sram_ctrl_stress_all.4094669502 |
|
|
Mar 05 12:58:09 PM PST 24 |
Mar 05 01:15:49 PM PST 24 |
1938396589 ps |
| T560 |
/workspace/coverage/default/34.sram_ctrl_partial_access.274686612 |
|
|
Mar 05 12:56:35 PM PST 24 |
Mar 05 12:57:05 PM PST 24 |
355196060 ps |
| T561 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.84506520 |
|
|
Mar 05 12:58:41 PM PST 24 |
Mar 05 01:00:55 PM PST 24 |
300181144 ps |
| T20 |
/workspace/coverage/default/1.sram_ctrl_sec_cm.3415810023 |
|
|
Mar 05 12:52:48 PM PST 24 |
Mar 05 12:52:51 PM PST 24 |
229836060 ps |
| T562 |
/workspace/coverage/default/3.sram_ctrl_max_throughput.284923477 |
|
|
Mar 05 12:52:56 PM PST 24 |
Mar 05 12:53:01 PM PST 24 |
179259779 ps |
| T563 |
/workspace/coverage/default/16.sram_ctrl_max_throughput.3770246151 |
|
|
Mar 05 12:54:29 PM PST 24 |
Mar 05 12:54:58 PM PST 24 |
196137139 ps |
| T564 |
/workspace/coverage/default/21.sram_ctrl_bijection.3787748080 |
|
|
Mar 05 12:55:04 PM PST 24 |
Mar 05 12:56:03 PM PST 24 |
992767827 ps |
| T565 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.3116813578 |
|
|
Mar 05 12:53:33 PM PST 24 |
Mar 05 12:53:43 PM PST 24 |
3859658941 ps |
| T566 |
/workspace/coverage/default/30.sram_ctrl_partial_access.2256801902 |
|
|
Mar 05 12:56:00 PM PST 24 |
Mar 05 12:56:12 PM PST 24 |
636936297 ps |
| T567 |
/workspace/coverage/default/16.sram_ctrl_bijection.1967252732 |
|
|
Mar 05 12:54:29 PM PST 24 |
Mar 05 12:54:58 PM PST 24 |
452177401 ps |
| T568 |
/workspace/coverage/default/10.sram_ctrl_regwen.1926637608 |
|
|
Mar 05 12:53:48 PM PST 24 |
Mar 05 12:55:47 PM PST 24 |
2214850490 ps |
| T569 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.2841719480 |
|
|
Mar 05 12:58:19 PM PST 24 |
Mar 05 12:58:29 PM PST 24 |
739990789 ps |
| T570 |
/workspace/coverage/default/0.sram_ctrl_mem_walk.309062205 |
|
|
Mar 05 12:52:40 PM PST 24 |
Mar 05 12:52:45 PM PST 24 |
656833528 ps |
| T571 |
/workspace/coverage/default/21.sram_ctrl_mem_walk.1595031185 |
|
|
Mar 05 12:55:08 PM PST 24 |
Mar 05 12:55:14 PM PST 24 |
74692023 ps |
| T572 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.3611914860 |
|
|
Mar 05 12:58:40 PM PST 24 |
Mar 05 12:58:45 PM PST 24 |
966721445 ps |
| T573 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.2574867252 |
|
|
Mar 05 12:53:59 PM PST 24 |
Mar 05 12:57:30 PM PST 24 |
2513677502 ps |
| T574 |
/workspace/coverage/default/28.sram_ctrl_mem_partial_access.4204601111 |
|
|
Mar 05 12:55:51 PM PST 24 |
Mar 05 12:55:56 PM PST 24 |
666050575 ps |
| T575 |
/workspace/coverage/default/41.sram_ctrl_executable.373060524 |
|
|
Mar 05 12:57:55 PM PST 24 |
Mar 05 01:17:42 PM PST 24 |
21966541841 ps |
| T576 |
/workspace/coverage/default/1.sram_ctrl_executable.3789501697 |
|
|
Mar 05 12:52:40 PM PST 24 |
Mar 05 12:54:38 PM PST 24 |
2933853158 ps |
| T577 |
/workspace/coverage/default/27.sram_ctrl_bijection.1424499666 |
|
|
Mar 05 12:55:43 PM PST 24 |
Mar 05 12:56:06 PM PST 24 |
465327468 ps |
| T578 |
/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.2380418268 |
|
|
Mar 05 12:55:45 PM PST 24 |
Mar 05 01:02:38 PM PST 24 |
51009649230 ps |
| T579 |
/workspace/coverage/default/1.sram_ctrl_stress_all.4207619266 |
|
|
Mar 05 12:52:48 PM PST 24 |
Mar 05 01:05:46 PM PST 24 |
4546761925 ps |
| T580 |
/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.1784822315 |
|
|
Mar 05 12:53:03 PM PST 24 |
Mar 05 12:59:30 PM PST 24 |
16565471493 ps |
| T581 |
/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.1822984604 |
|
|
Mar 05 12:57:29 PM PST 24 |
Mar 05 12:57:41 PM PST 24 |
352799614 ps |
| T582 |
/workspace/coverage/default/10.sram_ctrl_alert_test.2476275675 |
|
|
Mar 05 12:53:47 PM PST 24 |
Mar 05 12:53:48 PM PST 24 |
50430526 ps |
| T583 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1376322298 |
|
|
Mar 05 12:54:02 PM PST 24 |
Mar 05 12:57:32 PM PST 24 |
8526593980 ps |
| T584 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.23260148 |
|
|
Mar 05 12:55:36 PM PST 24 |
Mar 05 12:55:42 PM PST 24 |
1435130228 ps |
| T585 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.218239762 |
|
|
Mar 05 12:53:57 PM PST 24 |
Mar 05 12:54:01 PM PST 24 |
162882662 ps |
| T586 |
/workspace/coverage/default/48.sram_ctrl_regwen.4210099862 |
|
|
Mar 05 12:58:34 PM PST 24 |
Mar 05 01:12:07 PM PST 24 |
63582050782 ps |
| T587 |
/workspace/coverage/default/42.sram_ctrl_regwen.1621943335 |
|
|
Mar 05 12:58:03 PM PST 24 |
Mar 05 01:07:06 PM PST 24 |
8508445908 ps |
| T588 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.1393086409 |
|
|
Mar 05 12:57:42 PM PST 24 |
Mar 05 12:59:14 PM PST 24 |
583717204 ps |
| T589 |
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.284818575 |
|
|
Mar 05 12:53:22 PM PST 24 |
Mar 05 12:53:30 PM PST 24 |
189522870 ps |
| T590 |
/workspace/coverage/default/17.sram_ctrl_stress_all.2681663197 |
|
|
Mar 05 12:54:50 PM PST 24 |
Mar 05 01:41:01 PM PST 24 |
47024188229 ps |
| T591 |
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.1804833737 |
|
|
Mar 05 12:58:30 PM PST 24 |
Mar 05 12:58:33 PM PST 24 |
50660578 ps |
| T592 |
/workspace/coverage/default/46.sram_ctrl_regwen.3573938408 |
|
|
Mar 05 12:58:14 PM PST 24 |
Mar 05 12:59:55 PM PST 24 |
6974708027 ps |
| T593 |
/workspace/coverage/default/8.sram_ctrl_lc_escalation.1771339515 |
|
|
Mar 05 12:53:35 PM PST 24 |
Mar 05 12:53:54 PM PST 24 |
1661889701 ps |
| T594 |
/workspace/coverage/default/9.sram_ctrl_mem_walk.1623891589 |
|
|
Mar 05 12:53:41 PM PST 24 |
Mar 05 12:53:45 PM PST 24 |
239595654 ps |
| T595 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.3796337141 |
|
|
Mar 05 12:55:36 PM PST 24 |
Mar 05 12:57:53 PM PST 24 |
168152406 ps |
| T596 |
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.403540224 |
|
|
Mar 05 12:54:18 PM PST 24 |
Mar 05 12:57:14 PM PST 24 |
9687534737 ps |
| T597 |
/workspace/coverage/default/29.sram_ctrl_bijection.1075421163 |
|
|
Mar 05 12:55:51 PM PST 24 |
Mar 05 12:56:43 PM PST 24 |
3258122259 ps |
| T598 |
/workspace/coverage/default/15.sram_ctrl_max_throughput.3866294724 |
|
|
Mar 05 12:54:29 PM PST 24 |
Mar 05 12:55:20 PM PST 24 |
223892434 ps |
| T599 |
/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.1882185235 |
|
|
Mar 05 12:57:03 PM PST 24 |
Mar 05 01:02:58 PM PST 24 |
14101580456 ps |
| T600 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.795328356 |
|
|
Mar 05 12:53:31 PM PST 24 |
Mar 05 12:55:16 PM PST 24 |
13604270376 ps |
| T601 |
/workspace/coverage/default/45.sram_ctrl_partial_access.3561413686 |
|
|
Mar 05 12:58:00 PM PST 24 |
Mar 05 12:58:02 PM PST 24 |
521162781 ps |
| T602 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.22569319 |
|
|
Mar 05 12:53:25 PM PST 24 |
Mar 05 12:54:56 PM PST 24 |
303551167 ps |
| T603 |
/workspace/coverage/default/21.sram_ctrl_lc_escalation.2076776404 |
|
|
Mar 05 12:55:10 PM PST 24 |
Mar 05 12:55:23 PM PST 24 |
1159347697 ps |
| T604 |
/workspace/coverage/default/40.sram_ctrl_partial_access.2989628901 |
|
|
Mar 05 12:57:42 PM PST 24 |
Mar 05 12:57:45 PM PST 24 |
105546928 ps |
| T605 |
/workspace/coverage/default/2.sram_ctrl_multiple_keys.3431001276 |
|
|
Mar 05 12:52:48 PM PST 24 |
Mar 05 01:09:29 PM PST 24 |
12370635693 ps |
| T606 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.2473518305 |
|
|
Mar 05 12:55:21 PM PST 24 |
Mar 05 12:55:24 PM PST 24 |
529243217 ps |
| T607 |
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2019506412 |
|
|
Mar 05 12:53:33 PM PST 24 |
Mar 05 12:53:36 PM PST 24 |
170999531 ps |
| T608 |
/workspace/coverage/default/8.sram_ctrl_smoke.799454872 |
|
|
Mar 05 12:53:33 PM PST 24 |
Mar 05 12:54:26 PM PST 24 |
131307055 ps |
| T609 |
/workspace/coverage/default/15.sram_ctrl_smoke.116193734 |
|
|
Mar 05 12:54:29 PM PST 24 |
Mar 05 12:55:06 PM PST 24 |
379656839 ps |
| T610 |
/workspace/coverage/default/4.sram_ctrl_regwen.2423542111 |
|
|
Mar 05 12:53:11 PM PST 24 |
Mar 05 01:16:01 PM PST 24 |
16235761781 ps |
| T611 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.1147770486 |
|
|
Mar 05 12:55:02 PM PST 24 |
Mar 05 01:04:00 PM PST 24 |
5024798929 ps |
| T612 |
/workspace/coverage/default/43.sram_ctrl_regwen.3183743534 |
|
|
Mar 05 12:57:55 PM PST 24 |
Mar 05 01:11:12 PM PST 24 |
30342738218 ps |
| T613 |
/workspace/coverage/default/46.sram_ctrl_lc_escalation.1640126570 |
|
|
Mar 05 12:58:13 PM PST 24 |
Mar 05 12:58:19 PM PST 24 |
816110985 ps |
| T614 |
/workspace/coverage/default/29.sram_ctrl_stress_pipeline.3369066205 |
|
|
Mar 05 12:55:54 PM PST 24 |
Mar 05 01:03:18 PM PST 24 |
4640772887 ps |
| T615 |
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.3498799252 |
|
|
Mar 05 12:58:00 PM PST 24 |
Mar 05 01:02:25 PM PST 24 |
14231250596 ps |
| T616 |
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3159859880 |
|
|
Mar 05 12:58:25 PM PST 24 |
Mar 05 01:06:46 PM PST 24 |
38136244081 ps |
| T617 |
/workspace/coverage/default/4.sram_ctrl_bijection.3101532008 |
|
|
Mar 05 12:53:05 PM PST 24 |
Mar 05 12:54:01 PM PST 24 |
1775223256 ps |
| T618 |
/workspace/coverage/default/16.sram_ctrl_multiple_keys.1519862712 |
|
|
Mar 05 12:54:29 PM PST 24 |
Mar 05 01:00:28 PM PST 24 |
1894682859 ps |
| T619 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.2354748493 |
|
|
Mar 05 12:56:56 PM PST 24 |
Mar 05 01:01:00 PM PST 24 |
3631218115 ps |
| T620 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.4163374460 |
|
|
Mar 05 12:56:36 PM PST 24 |
Mar 05 01:00:03 PM PST 24 |
2346777132 ps |
| T621 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.625754837 |
|
|
Mar 05 12:58:29 PM PST 24 |
Mar 05 01:05:07 PM PST 24 |
5568526582 ps |
| T622 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.165306608 |
|
|
Mar 05 12:56:01 PM PST 24 |
Mar 05 12:56:07 PM PST 24 |
455759442 ps |
| T623 |
/workspace/coverage/default/31.sram_ctrl_partial_access.1372326791 |
|
|
Mar 05 12:56:08 PM PST 24 |
Mar 05 12:56:22 PM PST 24 |
4747273895 ps |
| T624 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.4061730251 |
|
|
Mar 05 12:57:55 PM PST 24 |
Mar 05 12:58:53 PM PST 24 |
240208440 ps |
| T625 |
/workspace/coverage/default/43.sram_ctrl_executable.2097999405 |
|
|
Mar 05 12:57:56 PM PST 24 |
Mar 05 01:10:42 PM PST 24 |
4692651266 ps |
| T626 |
/workspace/coverage/default/33.sram_ctrl_ram_cfg.3887895883 |
|
|
Mar 05 12:56:27 PM PST 24 |
Mar 05 12:56:28 PM PST 24 |
32764960 ps |
| T627 |
/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.2193300560 |
|
|
Mar 05 12:54:51 PM PST 24 |
Mar 05 12:57:49 PM PST 24 |
7298002381 ps |
| T628 |
/workspace/coverage/default/24.sram_ctrl_multiple_keys.522297596 |
|
|
Mar 05 12:55:24 PM PST 24 |
Mar 05 01:00:39 PM PST 24 |
7154529178 ps |
| T629 |
/workspace/coverage/default/46.sram_ctrl_ram_cfg.3477356724 |
|
|
Mar 05 12:58:12 PM PST 24 |
Mar 05 12:58:13 PM PST 24 |
35567011 ps |
| T630 |
/workspace/coverage/default/24.sram_ctrl_stress_all.1293867216 |
|
|
Mar 05 12:55:38 PM PST 24 |
Mar 05 01:46:44 PM PST 24 |
44276136619 ps |
| T631 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.663892415 |
|
|
Mar 05 12:53:32 PM PST 24 |
Mar 05 12:55:28 PM PST 24 |
134770754 ps |
| T632 |
/workspace/coverage/default/46.sram_ctrl_stress_all.2760210740 |
|
|
Mar 05 12:58:12 PM PST 24 |
Mar 05 01:06:20 PM PST 24 |
6820246254 ps |
| T633 |
/workspace/coverage/default/4.sram_ctrl_lc_escalation.3514918907 |
|
|
Mar 05 12:53:03 PM PST 24 |
Mar 05 12:53:23 PM PST 24 |
1748998860 ps |
| T634 |
/workspace/coverage/default/12.sram_ctrl_bijection.1893839325 |
|
|
Mar 05 12:54:02 PM PST 24 |
Mar 05 12:54:44 PM PST 24 |
664624668 ps |
| T635 |
/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.1668777565 |
|
|
Mar 05 12:54:26 PM PST 24 |
Mar 05 12:59:49 PM PST 24 |
52827117252 ps |
| T636 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3165330781 |
|
|
Mar 05 12:53:34 PM PST 24 |
Mar 05 12:58:44 PM PST 24 |
30356663929 ps |
| T637 |
/workspace/coverage/default/43.sram_ctrl_partial_access.38785101 |
|
|
Mar 05 12:57:55 PM PST 24 |
Mar 05 12:58:06 PM PST 24 |
504390248 ps |
| T638 |
/workspace/coverage/default/41.sram_ctrl_smoke.1837045475 |
|
|
Mar 05 12:57:41 PM PST 24 |
Mar 05 12:57:56 PM PST 24 |
1025630054 ps |
| T639 |
/workspace/coverage/default/32.sram_ctrl_mem_partial_access.1021120353 |
|
|
Mar 05 12:56:28 PM PST 24 |
Mar 05 12:56:31 PM PST 24 |
67563910 ps |
| T640 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.3913618879 |
|
|
Mar 05 12:55:49 PM PST 24 |
Mar 05 12:57:43 PM PST 24 |
1286121485 ps |
| T641 |
/workspace/coverage/default/22.sram_ctrl_regwen.1812058329 |
|
|
Mar 05 12:55:10 PM PST 24 |
Mar 05 01:00:48 PM PST 24 |
19566350028 ps |
| T642 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.91270217 |
|
|
Mar 05 12:56:08 PM PST 24 |
Mar 05 12:59:54 PM PST 24 |
2350256943 ps |
| T643 |
/workspace/coverage/default/14.sram_ctrl_partial_access.397708509 |
|
|
Mar 05 12:54:17 PM PST 24 |
Mar 05 12:54:23 PM PST 24 |
2752757804 ps |
| T644 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.4161996510 |
|
|
Mar 05 12:55:43 PM PST 24 |
Mar 05 12:56:16 PM PST 24 |
95050159 ps |
| T645 |
/workspace/coverage/default/32.sram_ctrl_partial_access.1296036501 |
|
|
Mar 05 12:56:20 PM PST 24 |
Mar 05 12:57:32 PM PST 24 |
689861896 ps |
| T646 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.2353442756 |
|
|
Mar 05 12:54:44 PM PST 24 |
Mar 05 12:55:35 PM PST 24 |
646363266 ps |
| T647 |
/workspace/coverage/default/47.sram_ctrl_multiple_keys.2859394229 |
|
|
Mar 05 12:58:13 PM PST 24 |
Mar 05 01:08:12 PM PST 24 |
4906325667 ps |
| T648 |
/workspace/coverage/default/48.sram_ctrl_alert_test.1449561867 |
|
|
Mar 05 12:58:29 PM PST 24 |
Mar 05 12:58:30 PM PST 24 |
64697070 ps |
| T649 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.670501555 |
|
|
Mar 05 12:52:37 PM PST 24 |
Mar 05 12:59:56 PM PST 24 |
24571374109 ps |
| T650 |
/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.4227903037 |
|
|
Mar 05 12:52:49 PM PST 24 |
Mar 05 12:57:55 PM PST 24 |
59298253433 ps |
| T651 |
/workspace/coverage/default/37.sram_ctrl_executable.1816430 |
|
|
Mar 05 12:57:04 PM PST 24 |
Mar 05 01:12:37 PM PST 24 |
121098432563 ps |
| T652 |
/workspace/coverage/default/11.sram_ctrl_bijection.1739971020 |
|
|
Mar 05 12:53:57 PM PST 24 |
Mar 05 12:54:46 PM PST 24 |
2425021238 ps |
| T653 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.3156617093 |
|
|
Mar 05 12:58:41 PM PST 24 |
Mar 05 12:58:42 PM PST 24 |
113137857 ps |
| T654 |
/workspace/coverage/default/48.sram_ctrl_executable.3651264682 |
|
|
Mar 05 12:58:29 PM PST 24 |
Mar 05 01:10:08 PM PST 24 |
3719119334 ps |
| T655 |
/workspace/coverage/default/2.sram_ctrl_mem_walk.782543922 |
|
|
Mar 05 12:52:54 PM PST 24 |
Mar 05 12:52:59 PM PST 24 |
294640676 ps |
| T656 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1958438795 |
|
|
Mar 05 12:54:29 PM PST 24 |
Mar 05 12:57:51 PM PST 24 |
3161945512 ps |
| T657 |
/workspace/coverage/default/24.sram_ctrl_bijection.3681631002 |
|
|
Mar 05 12:55:27 PM PST 24 |
Mar 05 12:56:21 PM PST 24 |
2604197970 ps |
| T658 |
/workspace/coverage/default/46.sram_ctrl_multiple_keys.907423950 |
|
|
Mar 05 12:58:14 PM PST 24 |
Mar 05 01:04:00 PM PST 24 |
6192082235 ps |
| T659 |
/workspace/coverage/default/6.sram_ctrl_stress_all.1760438513 |
|
|
Mar 05 12:53:21 PM PST 24 |
Mar 05 01:27:30 PM PST 24 |
27696485766 ps |
| T660 |
/workspace/coverage/default/33.sram_ctrl_alert_test.244506201 |
|
|
Mar 05 12:56:35 PM PST 24 |
Mar 05 12:56:36 PM PST 24 |
36476152 ps |
| T661 |
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.4193478593 |
|
|
Mar 05 12:55:19 PM PST 24 |
Mar 05 01:00:27 PM PST 24 |
16914061634 ps |
| T662 |
/workspace/coverage/default/8.sram_ctrl_stress_all.1243700347 |
|
|
Mar 05 12:53:39 PM PST 24 |
Mar 05 01:10:32 PM PST 24 |
15038277160 ps |
| T663 |
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2914760165 |
|
|
Mar 05 12:53:11 PM PST 24 |
Mar 05 12:58:28 PM PST 24 |
12985659340 ps |
| T664 |
/workspace/coverage/default/43.sram_ctrl_alert_test.3506226666 |
|
|
Mar 05 12:58:04 PM PST 24 |
Mar 05 12:58:05 PM PST 24 |
22264812 ps |
| T665 |
/workspace/coverage/default/19.sram_ctrl_partial_access.2135712014 |
|
|
Mar 05 12:54:52 PM PST 24 |
Mar 05 12:54:54 PM PST 24 |
245527524 ps |
| T666 |
/workspace/coverage/default/13.sram_ctrl_mem_walk.36728817 |
|
|
Mar 05 12:54:06 PM PST 24 |
Mar 05 12:54:15 PM PST 24 |
139872389 ps |
| T667 |
/workspace/coverage/default/46.sram_ctrl_smoke.2941014943 |
|
|
Mar 05 12:58:09 PM PST 24 |
Mar 05 12:58:29 PM PST 24 |
3416570162 ps |
| T668 |
/workspace/coverage/default/38.sram_ctrl_bijection.3817363322 |
|
|
Mar 05 12:57:04 PM PST 24 |
Mar 05 12:57:27 PM PST 24 |
361465860 ps |
| T669 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.3932924069 |
|
|
Mar 05 12:57:57 PM PST 24 |
Mar 05 12:58:26 PM PST 24 |
183138456 ps |
| T670 |
/workspace/coverage/default/6.sram_ctrl_multiple_keys.3635948881 |
|
|
Mar 05 12:53:22 PM PST 24 |
Mar 05 12:56:25 PM PST 24 |
1185153004 ps |
| T671 |
/workspace/coverage/default/25.sram_ctrl_alert_test.729499736 |
|
|
Mar 05 12:55:37 PM PST 24 |
Mar 05 12:55:38 PM PST 24 |
19172926 ps |
| T672 |
/workspace/coverage/default/15.sram_ctrl_bijection.502668552 |
|
|
Mar 05 12:54:33 PM PST 24 |
Mar 05 12:54:53 PM PST 24 |
1765160304 ps |
| T673 |
/workspace/coverage/default/8.sram_ctrl_bijection.2902575652 |
|
|
Mar 05 12:53:34 PM PST 24 |
Mar 05 12:54:51 PM PST 24 |
3584875939 ps |
| T674 |
/workspace/coverage/default/23.sram_ctrl_partial_access.3412495621 |
|
|
Mar 05 12:55:19 PM PST 24 |
Mar 05 12:57:32 PM PST 24 |
1428055051 ps |
| T675 |
/workspace/coverage/default/16.sram_ctrl_lc_escalation.1683179810 |
|
|
Mar 05 12:54:28 PM PST 24 |
Mar 05 12:54:36 PM PST 24 |
731318214 ps |
| T676 |
/workspace/coverage/default/7.sram_ctrl_partial_access.235484366 |
|
|
Mar 05 12:53:34 PM PST 24 |
Mar 05 12:53:54 PM PST 24 |
4318954385 ps |
| T114 |
/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3666575373 |
|
|
Mar 05 12:57:15 PM PST 24 |
Mar 05 01:02:25 PM PST 24 |
10637847836 ps |
| T677 |
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.1261336648 |
|
|
Mar 05 12:53:41 PM PST 24 |
Mar 05 12:57:23 PM PST 24 |
2635330809 ps |
| T678 |
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.2775378120 |
|
|
Mar 05 12:58:12 PM PST 24 |
Mar 05 12:58:18 PM PST 24 |
157363963 ps |
| T679 |
/workspace/coverage/default/30.sram_ctrl_alert_test.2505313870 |
|
|
Mar 05 12:56:08 PM PST 24 |
Mar 05 12:56:09 PM PST 24 |
15063001 ps |
| T680 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.1953222867 |
|
|
Mar 05 12:53:35 PM PST 24 |
Mar 05 12:58:27 PM PST 24 |
16059386286 ps |
| T681 |
/workspace/coverage/default/10.sram_ctrl_stress_all.938273717 |
|
|
Mar 05 12:53:52 PM PST 24 |
Mar 05 01:47:01 PM PST 24 |
40483066013 ps |
| T682 |
/workspace/coverage/default/23.sram_ctrl_smoke.378581992 |
|
|
Mar 05 12:55:21 PM PST 24 |
Mar 05 12:56:46 PM PST 24 |
559626805 ps |
| T683 |
/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.3415808170 |
|
|
Mar 05 12:54:04 PM PST 24 |
Mar 05 12:54:10 PM PST 24 |
229690271 ps |
| T684 |
/workspace/coverage/default/0.sram_ctrl_alert_test.684391380 |
|
|
Mar 05 12:52:39 PM PST 24 |
Mar 05 12:52:40 PM PST 24 |
12886121 ps |
| T685 |
/workspace/coverage/default/0.sram_ctrl_stress_all.2140708364 |
|
|
Mar 05 12:52:44 PM PST 24 |
Mar 05 01:24:13 PM PST 24 |
33673861763 ps |
| T686 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.4219082160 |
|
|
Mar 05 12:55:01 PM PST 24 |
Mar 05 12:55:07 PM PST 24 |
2068620631 ps |
| T687 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.770199899 |
|
|
Mar 05 12:58:11 PM PST 24 |
Mar 05 01:00:00 PM PST 24 |
13245464139 ps |
| T688 |
/workspace/coverage/default/7.sram_ctrl_stress_all.802178342 |
|
|
Mar 05 12:53:32 PM PST 24 |
Mar 05 01:36:49 PM PST 24 |
415806988456 ps |
| T689 |
/workspace/coverage/default/42.sram_ctrl_ram_cfg.2761355223 |
|
|
Mar 05 12:57:54 PM PST 24 |
Mar 05 12:57:55 PM PST 24 |
123818799 ps |
| T690 |
/workspace/coverage/default/13.sram_ctrl_bijection.3472917309 |
|
|
Mar 05 12:54:05 PM PST 24 |
Mar 05 12:54:37 PM PST 24 |
2954555906 ps |
| T691 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.1852155845 |
|
|
Mar 05 12:53:31 PM PST 24 |
Mar 05 01:02:58 PM PST 24 |
2393902740 ps |
| T692 |
/workspace/coverage/default/36.sram_ctrl_partial_access.928177505 |
|
|
Mar 05 12:56:56 PM PST 24 |
Mar 05 12:59:27 PM PST 24 |
2677211223 ps |
| T693 |
/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.2785135303 |
|
|
Mar 05 12:55:10 PM PST 24 |
Mar 05 12:56:42 PM PST 24 |
1794436055 ps |
| T694 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.577298125 |
|
|
Mar 05 12:57:17 PM PST 24 |
Mar 05 12:57:20 PM PST 24 |
90160160 ps |
| T695 |
/workspace/coverage/default/47.sram_ctrl_regwen.2884449597 |
|
|
Mar 05 12:58:18 PM PST 24 |
Mar 05 01:20:56 PM PST 24 |
13515876142 ps |
| T696 |
/workspace/coverage/default/37.sram_ctrl_regwen.3589735747 |
|
|
Mar 05 12:57:03 PM PST 24 |
Mar 05 01:20:20 PM PST 24 |
17089312255 ps |
| T697 |
/workspace/coverage/default/9.sram_ctrl_partial_access.3791819953 |
|
|
Mar 05 12:53:43 PM PST 24 |
Mar 05 12:54:42 PM PST 24 |
2094455022 ps |
| T698 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.2880044268 |
|
|
Mar 05 12:58:28 PM PST 24 |
Mar 05 12:58:29 PM PST 24 |
88440615 ps |
| T699 |
/workspace/coverage/default/19.sram_ctrl_stress_pipeline.2832490917 |
|
|
Mar 05 12:54:56 PM PST 24 |
Mar 05 12:58:44 PM PST 24 |
2406525095 ps |
| T700 |
/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.915386825 |
|
|
Mar 05 12:55:46 PM PST 24 |
Mar 05 01:00:48 PM PST 24 |
4687996241 ps |
| T701 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.526358075 |
|
|
Mar 05 12:58:03 PM PST 24 |
Mar 05 01:02:17 PM PST 24 |
12159675650 ps |
| T702 |
/workspace/coverage/default/47.sram_ctrl_mem_walk.1528431784 |
|
|
Mar 05 12:58:23 PM PST 24 |
Mar 05 12:58:29 PM PST 24 |
743893969 ps |
| T703 |
/workspace/coverage/default/16.sram_ctrl_executable.2878721967 |
|
|
Mar 05 12:54:28 PM PST 24 |
Mar 05 12:57:15 PM PST 24 |
637047889 ps |
| T704 |
/workspace/coverage/default/41.sram_ctrl_stress_pipeline.2223516591 |
|
|
Mar 05 12:57:38 PM PST 24 |
Mar 05 01:00:26 PM PST 24 |
1920880523 ps |
| T705 |
/workspace/coverage/default/43.sram_ctrl_bijection.4172805645 |
|
|
Mar 05 12:57:53 PM PST 24 |
Mar 05 12:58:37 PM PST 24 |
10544674291 ps |
| T706 |
/workspace/coverage/default/21.sram_ctrl_executable.705355510 |
|
|
Mar 05 12:55:10 PM PST 24 |
Mar 05 01:05:48 PM PST 24 |
10671464698 ps |
| T707 |
/workspace/coverage/default/40.sram_ctrl_lc_escalation.918172380 |
|
|
Mar 05 12:57:43 PM PST 24 |
Mar 05 12:57:48 PM PST 24 |
273505234 ps |
| T708 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.1171544173 |
|
|
Mar 05 12:56:26 PM PST 24 |
Mar 05 01:02:35 PM PST 24 |
19074714636 ps |
| T709 |
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3678586998 |
|
|
Mar 05 12:54:53 PM PST 24 |
Mar 05 12:54:59 PM PST 24 |
459655597 ps |
| T710 |
/workspace/coverage/default/32.sram_ctrl_smoke.2855268265 |
|
|
Mar 05 12:56:17 PM PST 24 |
Mar 05 12:56:34 PM PST 24 |
265069442 ps |
| T711 |
/workspace/coverage/default/8.sram_ctrl_regwen.1859572601 |
|
|
Mar 05 12:53:41 PM PST 24 |
Mar 05 12:59:37 PM PST 24 |
8880370621 ps |
| T712 |
/workspace/coverage/default/4.sram_ctrl_stress_all.34526851 |
|
|
Mar 05 12:53:14 PM PST 24 |
Mar 05 01:20:35 PM PST 24 |
5438955393 ps |
| T713 |
/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.4094188833 |
|
|
Mar 05 12:56:56 PM PST 24 |
Mar 05 12:57:41 PM PST 24 |
115047139 ps |
| T115 |
/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.3916172892 |
|
|
Mar 05 12:56:18 PM PST 24 |
Mar 05 12:56:52 PM PST 24 |
4591804685 ps |
| T714 |
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.4268755424 |
|
|
Mar 05 12:58:00 PM PST 24 |
Mar 05 12:59:07 PM PST 24 |
557951268 ps |
| T715 |
/workspace/coverage/default/36.sram_ctrl_smoke.3415285500 |
|
|
Mar 05 12:56:56 PM PST 24 |
Mar 05 12:58:17 PM PST 24 |
1172214804 ps |
| T716 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.2788791241 |
|
|
Mar 05 12:58:29 PM PST 24 |
Mar 05 12:59:15 PM PST 24 |
107395880 ps |
| T717 |
/workspace/coverage/default/7.sram_ctrl_executable.4017816804 |
|
|
Mar 05 12:53:35 PM PST 24 |
Mar 05 12:57:23 PM PST 24 |
10701664687 ps |
| T718 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.987591598 |
|
|
Mar 05 12:55:10 PM PST 24 |
Mar 05 12:55:21 PM PST 24 |
214712779 ps |
| T719 |
/workspace/coverage/default/16.sram_ctrl_regwen.428530285 |
|
|
Mar 05 12:54:29 PM PST 24 |
Mar 05 01:12:44 PM PST 24 |
2653109097 ps |
| T720 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.1674844817 |
|
|
Mar 05 12:52:38 PM PST 24 |
Mar 05 12:52:42 PM PST 24 |
271195257 ps |
| T721 |
/workspace/coverage/default/22.sram_ctrl_smoke.1301669159 |
|
|
Mar 05 12:55:10 PM PST 24 |
Mar 05 12:56:16 PM PST 24 |
480942869 ps |
| T38 |
/workspace/coverage/default/0.sram_ctrl_sec_cm.2487188654 |
|
|
Mar 05 12:52:38 PM PST 24 |
Mar 05 12:52:43 PM PST 24 |
924939399 ps |
| T722 |
/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.12913741 |
|
|
Mar 05 12:56:18 PM PST 24 |
Mar 05 12:57:09 PM PST 24 |
124734209 ps |
| T723 |
/workspace/coverage/default/17.sram_ctrl_ram_cfg.456445573 |
|
|
Mar 05 12:54:44 PM PST 24 |
Mar 05 12:54:45 PM PST 24 |
50344514 ps |
| T724 |
/workspace/coverage/default/6.sram_ctrl_smoke.2724136520 |
|
|
Mar 05 12:53:20 PM PST 24 |
Mar 05 12:54:06 PM PST 24 |
126001531 ps |
| T725 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.4100152779 |
|
|
Mar 05 12:56:46 PM PST 24 |
Mar 05 12:56:49 PM PST 24 |
81929656 ps |
| T726 |
/workspace/coverage/default/37.sram_ctrl_alert_test.3257242104 |
|
|
Mar 05 12:57:04 PM PST 24 |
Mar 05 12:57:05 PM PST 24 |
30863629 ps |
| T727 |
/workspace/coverage/default/24.sram_ctrl_mem_walk.4040116358 |
|
|
Mar 05 12:55:26 PM PST 24 |
Mar 05 12:55:34 PM PST 24 |
479079207 ps |
| T728 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.2226321063 |
|
|
Mar 05 12:55:35 PM PST 24 |
Mar 05 01:03:02 PM PST 24 |
17486922972 ps |
| T729 |
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3051178876 |
|
|
Mar 05 12:58:42 PM PST 24 |
Mar 05 12:58:49 PM PST 24 |
759976587 ps |
| T730 |
/workspace/coverage/default/35.sram_ctrl_mem_walk.1675734149 |
|
|
Mar 05 12:56:45 PM PST 24 |
Mar 05 12:56:51 PM PST 24 |
1196281144 ps |
| T39 |
/workspace/coverage/default/3.sram_ctrl_sec_cm.2566578915 |
|
|
Mar 05 12:53:03 PM PST 24 |
Mar 05 12:53:07 PM PST 24 |
163610462 ps |
| T731 |
/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.3592631619 |
|
|
Mar 05 12:54:43 PM PST 24 |
Mar 05 12:54:55 PM PST 24 |
283355917 ps |
| T732 |
/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.2373551705 |
|
|
Mar 05 12:57:04 PM PST 24 |
Mar 05 12:57:38 PM PST 24 |
204894526 ps |
| T733 |
/workspace/coverage/default/10.sram_ctrl_ram_cfg.1448320672 |
|
|
Mar 05 12:53:50 PM PST 24 |
Mar 05 12:53:51 PM PST 24 |
27963677 ps |
| T734 |
/workspace/coverage/default/9.sram_ctrl_regwen.1539007604 |
|
|
Mar 05 12:53:42 PM PST 24 |
Mar 05 01:10:14 PM PST 24 |
79693911373 ps |
| T735 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.3728992246 |
|
|
Mar 05 12:58:40 PM PST 24 |
Mar 05 12:58:45 PM PST 24 |
249465313 ps |
| T736 |
/workspace/coverage/default/41.sram_ctrl_mem_walk.555784711 |
|
|
Mar 05 12:57:53 PM PST 24 |
Mar 05 12:57:59 PM PST 24 |
354159057 ps |
| T737 |
/workspace/coverage/default/17.sram_ctrl_regwen.1508046292 |
|
|
Mar 05 12:54:45 PM PST 24 |
Mar 05 01:17:54 PM PST 24 |
2898714456 ps |
| T738 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3308302620 |
|
|
Mar 05 12:52:41 PM PST 24 |
Mar 05 12:52:42 PM PST 24 |
117658901 ps |
| T17 |
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.3986106054 |
|
|
Mar 05 12:56:17 PM PST 24 |
Mar 05 12:57:04 PM PST 24 |
474045933 ps |
| T739 |
/workspace/coverage/default/28.sram_ctrl_lc_escalation.567904552 |
|
|
Mar 05 12:55:50 PM PST 24 |
Mar 05 12:56:01 PM PST 24 |
873713931 ps |
| T740 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1162473374 |
|
|
Mar 05 12:57:56 PM PST 24 |
Mar 05 01:05:44 PM PST 24 |
92560427041 ps |
| T741 |
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.1190326506 |
|
|
Mar 05 12:53:59 PM PST 24 |
Mar 05 12:54:03 PM PST 24 |
204580306 ps |
| T742 |
/workspace/coverage/default/8.sram_ctrl_alert_test.3864702535 |
|
|
Mar 05 12:53:42 PM PST 24 |
Mar 05 12:53:44 PM PST 24 |
13646238 ps |
| T743 |
/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.468889412 |
|
|
Mar 05 12:57:03 PM PST 24 |
Mar 05 01:03:45 PM PST 24 |
31970880332 ps |
| T744 |
/workspace/coverage/default/33.sram_ctrl_regwen.3298024020 |
|
|
Mar 05 12:56:27 PM PST 24 |
Mar 05 01:22:33 PM PST 24 |
58058585477 ps |
| T745 |
/workspace/coverage/default/10.sram_ctrl_bijection.886362355 |
|
|
Mar 05 12:53:50 PM PST 24 |
Mar 05 12:54:59 PM PST 24 |
3743564024 ps |
| T746 |
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.902551720 |
|
|
Mar 05 12:52:51 PM PST 24 |
Mar 05 12:55:04 PM PST 24 |
1078604038 ps |
| T747 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.3811485568 |
|
|
Mar 05 12:57:04 PM PST 24 |
Mar 05 01:03:43 PM PST 24 |
3954899060 ps |
| T748 |
/workspace/coverage/default/45.sram_ctrl_executable.2532687698 |
|
|
Mar 05 12:58:04 PM PST 24 |
Mar 05 01:18:33 PM PST 24 |
5295841309 ps |
| T749 |
/workspace/coverage/default/23.sram_ctrl_multiple_keys.1156881080 |
|
|
Mar 05 12:55:18 PM PST 24 |
Mar 05 01:19:29 PM PST 24 |
147543875262 ps |
| T750 |
/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.1727884864 |
|
|
Mar 05 12:57:42 PM PST 24 |
Mar 05 12:59:54 PM PST 24 |
1267253825 ps |
| T751 |
/workspace/coverage/default/24.sram_ctrl_executable.1239378344 |
|
|
Mar 05 12:55:26 PM PST 24 |
Mar 05 01:15:27 PM PST 24 |
46061082021 ps |
| T752 |
/workspace/coverage/default/20.sram_ctrl_smoke.4282541671 |
|
|
Mar 05 12:54:56 PM PST 24 |
Mar 05 12:55:05 PM PST 24 |
1137490159 ps |
| T753 |
/workspace/coverage/default/36.sram_ctrl_lc_escalation.1591943563 |
|
|
Mar 05 12:56:57 PM PST 24 |
Mar 05 12:57:38 PM PST 24 |
4340996402 ps |
| T754 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.2952546093 |
|
|
Mar 05 12:54:29 PM PST 24 |
Mar 05 12:56:57 PM PST 24 |
3208737812 ps |
| T755 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.4203543311 |
|
|
Mar 05 12:54:07 PM PST 24 |
Mar 05 12:54:12 PM PST 24 |
221553500 ps |
| T756 |
/workspace/coverage/default/44.sram_ctrl_stress_all.157633281 |
|
|
Mar 05 12:58:08 PM PST 24 |
Mar 05 01:26:48 PM PST 24 |
73899024667 ps |
| T757 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.918983167 |
|
|
Mar 05 12:54:01 PM PST 24 |
Mar 05 01:06:48 PM PST 24 |
12448285262 ps |
| T758 |
/workspace/coverage/default/17.sram_ctrl_mem_walk.3189513863 |
|
|
Mar 05 12:54:49 PM PST 24 |
Mar 05 12:54:58 PM PST 24 |
1154917829 ps |
| T759 |
/workspace/coverage/default/3.sram_ctrl_multiple_keys.3102166265 |
|
|
Mar 05 12:52:54 PM PST 24 |
Mar 05 01:03:24 PM PST 24 |
10417331821 ps |
| T760 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.1372836097 |
|
|
Mar 05 12:58:09 PM PST 24 |
Mar 05 01:01:46 PM PST 24 |
4781965020 ps |
| T761 |
/workspace/coverage/default/27.sram_ctrl_mem_walk.1437349439 |
|
|
Mar 05 12:55:43 PM PST 24 |
Mar 05 12:55:48 PM PST 24 |
663870192 ps |
| T762 |
/workspace/coverage/default/26.sram_ctrl_mem_partial_access.2359236399 |
|
|
Mar 05 12:55:45 PM PST 24 |
Mar 05 12:55:51 PM PST 24 |
688349023 ps |
| T763 |
/workspace/coverage/default/28.sram_ctrl_mem_walk.162707874 |
|
|
Mar 05 12:55:54 PM PST 24 |
Mar 05 12:55:58 PM PST 24 |
77185677 ps |
| T764 |
/workspace/coverage/default/19.sram_ctrl_bijection.3676523707 |
|
|
Mar 05 12:54:54 PM PST 24 |
Mar 05 12:55:50 PM PST 24 |
3149023138 ps |
| T765 |
/workspace/coverage/default/2.sram_ctrl_executable.2775656992 |
|
|
Mar 05 12:52:54 PM PST 24 |
Mar 05 01:11:54 PM PST 24 |
13673940014 ps |
| T766 |
/workspace/coverage/default/1.sram_ctrl_bijection.2004085550 |
|
|
Mar 05 12:52:38 PM PST 24 |
Mar 05 12:52:52 PM PST 24 |
239805988 ps |
| T767 |
/workspace/coverage/default/14.sram_ctrl_bijection.1274759349 |
|
|
Mar 05 12:54:17 PM PST 24 |
Mar 05 12:54:41 PM PST 24 |
6150231122 ps |
| T768 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.743635633 |
|
|
Mar 05 12:58:19 PM PST 24 |
Mar 05 12:58:22 PM PST 24 |
226478600 ps |
| T769 |
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.2434617829 |
|
|
Mar 05 12:58:01 PM PST 24 |
Mar 05 12:58:04 PM PST 24 |
96316759 ps |
| T770 |
/workspace/coverage/default/14.sram_ctrl_regwen.1171727631 |
|
|
Mar 05 12:54:16 PM PST 24 |
Mar 05 01:03:16 PM PST 24 |
5249308474 ps |
| T771 |
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.3579987332 |
|
|
Mar 05 12:56:01 PM PST 24 |
Mar 05 12:57:45 PM PST 24 |
6860724165 ps |
| T772 |
/workspace/coverage/default/0.sram_ctrl_ram_cfg.2677870482 |
|
|
Mar 05 12:52:34 PM PST 24 |
Mar 05 12:52:36 PM PST 24 |
29199051 ps |
| T773 |
/workspace/coverage/default/23.sram_ctrl_alert_test.1865410390 |
|
|
Mar 05 12:57:13 PM PST 24 |
Mar 05 12:57:14 PM PST 24 |
27301272 ps |
| T774 |
/workspace/coverage/default/10.sram_ctrl_executable.3831208427 |
|
|
Mar 05 12:53:48 PM PST 24 |
Mar 05 01:02:41 PM PST 24 |
15304901534 ps |
| T775 |
/workspace/coverage/default/43.sram_ctrl_multiple_keys.172021264 |
|
|
Mar 05 12:58:00 PM PST 24 |
Mar 05 01:09:39 PM PST 24 |
49045086401 ps |
| T776 |
/workspace/coverage/default/3.sram_ctrl_partial_access.1698634336 |
|
|
Mar 05 12:52:53 PM PST 24 |
Mar 05 12:53:07 PM PST 24 |
808372485 ps |
| T777 |
/workspace/coverage/default/35.sram_ctrl_bijection.2012315857 |
|
|
Mar 05 12:56:45 PM PST 24 |
Mar 05 12:57:06 PM PST 24 |
2328627891 ps |
| T778 |
/workspace/coverage/default/25.sram_ctrl_bijection.142039269 |
|
|
Mar 05 12:55:40 PM PST 24 |
Mar 05 12:56:50 PM PST 24 |
24965871115 ps |
| T779 |
/workspace/coverage/default/40.sram_ctrl_partial_access_b2b.2190981493 |
|
|
Mar 05 12:57:45 PM PST 24 |
Mar 05 01:04:18 PM PST 24 |
22667566937 ps |
| T780 |
/workspace/coverage/default/30.sram_ctrl_executable.900004651 |
|
|
Mar 05 12:56:12 PM PST 24 |
Mar 05 12:59:38 PM PST 24 |
3650296017 ps |
| T781 |
/workspace/coverage/default/4.sram_ctrl_stress_pipeline.574028896 |
|
|
Mar 05 12:53:03 PM PST 24 |
Mar 05 12:58:02 PM PST 24 |
8846408836 ps |
| T782 |
/workspace/coverage/default/32.sram_ctrl_max_throughput.2294528101 |
|
|
Mar 05 12:56:19 PM PST 24 |
Mar 05 12:57:16 PM PST 24 |
354863003 ps |
| T783 |
/workspace/coverage/default/32.sram_ctrl_mem_walk.2048743271 |
|
|
Mar 05 12:56:29 PM PST 24 |
Mar 05 12:56:40 PM PST 24 |
3835799763 ps |
| T784 |
/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3108787049 |
|
|
Mar 05 12:52:58 PM PST 24 |
Mar 05 12:57:23 PM PST 24 |
4032957827 ps |
| T785 |
/workspace/coverage/default/23.sram_ctrl_mem_walk.3943713227 |
|
|
Mar 05 12:55:19 PM PST 24 |
Mar 05 12:55:25 PM PST 24 |
346027519 ps |
| T786 |
/workspace/coverage/default/25.sram_ctrl_multiple_keys.3704916242 |
|
|
Mar 05 12:55:38 PM PST 24 |
Mar 05 12:57:55 PM PST 24 |
3619865427 ps |
| T787 |
/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.1411805676 |
|
|
Mar 05 12:54:27 PM PST 24 |
Mar 05 01:04:51 PM PST 24 |
2514591310 ps |
| T788 |
/workspace/coverage/default/3.sram_ctrl_smoke.890960767 |
|
|
Mar 05 12:52:55 PM PST 24 |
Mar 05 12:52:58 PM PST 24 |
1197397606 ps |
| T789 |
/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.4221010511 |
|
|
Mar 05 12:55:25 PM PST 24 |
Mar 05 01:00:52 PM PST 24 |
23371663622 ps |
| T790 |
/workspace/coverage/default/19.sram_ctrl_stress_all.4034579965 |
|
|
Mar 05 12:54:52 PM PST 24 |
Mar 05 02:09:48 PM PST 24 |
482277758348 ps |