| T546 |
/workspace/coverage/default/42.sram_ctrl_stress_all.1099599099 |
|
|
Mar 10 02:40:43 PM PDT 24 |
Mar 10 03:21:08 PM PDT 24 |
13126098753 ps |
| T547 |
/workspace/coverage/default/30.sram_ctrl_regwen.3672112978 |
|
|
Mar 10 02:38:49 PM PDT 24 |
Mar 10 02:49:54 PM PDT 24 |
1192891226 ps |
| T548 |
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3636308173 |
|
|
Mar 10 02:35:48 PM PDT 24 |
Mar 10 02:42:12 PM PDT 24 |
10483337136 ps |
| T549 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.270368099 |
|
|
Mar 10 02:35:59 PM PDT 24 |
Mar 10 02:38:38 PM PDT 24 |
1753194115 ps |
| T550 |
/workspace/coverage/default/24.sram_ctrl_partial_access.3151969770 |
|
|
Mar 10 02:38:10 PM PDT 24 |
Mar 10 02:38:27 PM PDT 24 |
1748087047 ps |
| T551 |
/workspace/coverage/default/42.sram_ctrl_multiple_keys.1460966724 |
|
|
Mar 10 02:40:30 PM PDT 24 |
Mar 10 02:54:40 PM PDT 24 |
3087598089 ps |
| T552 |
/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.1274330740 |
|
|
Mar 10 02:36:55 PM PDT 24 |
Mar 10 02:37:01 PM PDT 24 |
231928241 ps |
| T553 |
/workspace/coverage/default/4.sram_ctrl_partial_access.1866623668 |
|
|
Mar 10 02:35:14 PM PDT 24 |
Mar 10 02:35:16 PM PDT 24 |
172573389 ps |
| T554 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.996754528 |
|
|
Mar 10 02:38:12 PM PDT 24 |
Mar 10 02:38:13 PM PDT 24 |
55287603 ps |
| T555 |
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.3984824004 |
|
|
Mar 10 02:40:27 PM PDT 24 |
Mar 10 02:40:48 PM PDT 24 |
422117390 ps |
| T33 |
/workspace/coverage/default/4.sram_ctrl_sec_cm.1605058768 |
|
|
Mar 10 02:35:18 PM PDT 24 |
Mar 10 02:35:20 PM PDT 24 |
142329352 ps |
| T556 |
/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.3214173890 |
|
|
Mar 10 02:38:16 PM PDT 24 |
Mar 10 02:38:18 PM PDT 24 |
126943830 ps |
| T557 |
/workspace/coverage/default/25.sram_ctrl_multiple_keys.32248916 |
|
|
Mar 10 02:38:12 PM PDT 24 |
Mar 10 03:02:16 PM PDT 24 |
62921684498 ps |
| T558 |
/workspace/coverage/default/2.sram_ctrl_access_during_key_req.2600273752 |
|
|
Mar 10 02:35:00 PM PDT 24 |
Mar 10 02:43:20 PM PDT 24 |
3057072166 ps |
| T559 |
/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.2328903525 |
|
|
Mar 10 02:40:00 PM PDT 24 |
Mar 10 02:51:30 PM PDT 24 |
8092909366 ps |
| T560 |
/workspace/coverage/default/45.sram_ctrl_executable.2301312877 |
|
|
Mar 10 02:40:58 PM PDT 24 |
Mar 10 03:18:54 PM PDT 24 |
4698757512 ps |
| T561 |
/workspace/coverage/default/15.sram_ctrl_partial_access.2177056799 |
|
|
Mar 10 02:36:37 PM PDT 24 |
Mar 10 02:36:46 PM PDT 24 |
1920043331 ps |
| T562 |
/workspace/coverage/default/20.sram_ctrl_mem_partial_access.2852182109 |
|
|
Mar 10 02:37:20 PM PDT 24 |
Mar 10 02:37:26 PM PDT 24 |
162302322 ps |
| T563 |
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.2200211867 |
|
|
Mar 10 02:37:35 PM PDT 24 |
Mar 10 02:37:46 PM PDT 24 |
132374026 ps |
| T564 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.2997618852 |
|
|
Mar 10 02:39:50 PM PDT 24 |
Mar 10 02:40:03 PM PDT 24 |
662010489 ps |
| T565 |
/workspace/coverage/default/17.sram_ctrl_access_during_key_req.3193997628 |
|
|
Mar 10 02:36:54 PM PDT 24 |
Mar 10 02:39:18 PM PDT 24 |
539558770 ps |
| T566 |
/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.3707015994 |
|
|
Mar 10 02:37:00 PM PDT 24 |
Mar 10 02:37:42 PM PDT 24 |
143456549 ps |
| T567 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.2636470083 |
|
|
Mar 10 02:40:28 PM PDT 24 |
Mar 10 02:40:29 PM PDT 24 |
29512400 ps |
| T568 |
/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.1688433374 |
|
|
Mar 10 02:39:25 PM PDT 24 |
Mar 10 02:40:29 PM PDT 24 |
661319979 ps |
| T569 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.2608546951 |
|
|
Mar 10 02:36:29 PM PDT 24 |
Mar 10 02:37:49 PM PDT 24 |
1406675504 ps |
| T570 |
/workspace/coverage/default/41.sram_ctrl_executable.4255993231 |
|
|
Mar 10 02:40:27 PM PDT 24 |
Mar 10 02:57:35 PM PDT 24 |
2423775436 ps |
| T571 |
/workspace/coverage/default/3.sram_ctrl_access_during_key_req.1407947613 |
|
|
Mar 10 02:35:13 PM PDT 24 |
Mar 10 02:35:36 PM PDT 24 |
1562482040 ps |
| T572 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.2188980058 |
|
|
Mar 10 02:39:43 PM PDT 24 |
Mar 10 02:43:31 PM PDT 24 |
2085412308 ps |
| T573 |
/workspace/coverage/default/49.sram_ctrl_partial_access.1876374696 |
|
|
Mar 10 02:41:34 PM PDT 24 |
Mar 10 02:44:33 PM PDT 24 |
1591939680 ps |
| T574 |
/workspace/coverage/default/42.sram_ctrl_ram_cfg.1440632957 |
|
|
Mar 10 02:40:37 PM PDT 24 |
Mar 10 02:40:38 PM PDT 24 |
26850919 ps |
| T575 |
/workspace/coverage/default/2.sram_ctrl_smoke.446916284 |
|
|
Mar 10 02:34:55 PM PDT 24 |
Mar 10 02:35:12 PM PDT 24 |
905546034 ps |
| T576 |
/workspace/coverage/default/14.sram_ctrl_partial_access.818047738 |
|
|
Mar 10 02:36:22 PM PDT 24 |
Mar 10 02:36:29 PM PDT 24 |
119758529 ps |
| T577 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.2613318577 |
|
|
Mar 10 02:39:09 PM PDT 24 |
Mar 10 02:48:12 PM PDT 24 |
21288245391 ps |
| T578 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.1344282994 |
|
|
Mar 10 02:40:04 PM PDT 24 |
Mar 10 02:45:08 PM PDT 24 |
1650854241 ps |
| T579 |
/workspace/coverage/default/27.sram_ctrl_lc_escalation.3874355721 |
|
|
Mar 10 02:38:22 PM PDT 24 |
Mar 10 02:38:33 PM PDT 24 |
1419885138 ps |
| T580 |
/workspace/coverage/default/43.sram_ctrl_stress_all.1816827711 |
|
|
Mar 10 02:40:45 PM PDT 24 |
Mar 10 03:31:27 PM PDT 24 |
119359749971 ps |
| T581 |
/workspace/coverage/default/25.sram_ctrl_partial_access.4072643996 |
|
|
Mar 10 02:38:14 PM PDT 24 |
Mar 10 02:38:58 PM PDT 24 |
584614964 ps |
| T582 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.4050249290 |
|
|
Mar 10 02:35:21 PM PDT 24 |
Mar 10 02:35:54 PM PDT 24 |
3517692178 ps |
| T583 |
/workspace/coverage/default/24.sram_ctrl_mem_walk.2832781605 |
|
|
Mar 10 02:38:10 PM PDT 24 |
Mar 10 02:38:19 PM PDT 24 |
268349003 ps |
| T584 |
/workspace/coverage/default/23.sram_ctrl_access_during_key_req.2662609949 |
|
|
Mar 10 02:38:10 PM PDT 24 |
Mar 10 02:53:11 PM PDT 24 |
7609657990 ps |
| T585 |
/workspace/coverage/default/24.sram_ctrl_stress_all.3328369900 |
|
|
Mar 10 02:38:14 PM PDT 24 |
Mar 10 03:37:09 PM PDT 24 |
77043258324 ps |
| T586 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.2743631404 |
|
|
Mar 10 02:40:21 PM PDT 24 |
Mar 10 02:40:22 PM PDT 24 |
186580925 ps |
| T587 |
/workspace/coverage/default/13.sram_ctrl_partial_access.875796682 |
|
|
Mar 10 02:36:15 PM PDT 24 |
Mar 10 02:38:06 PM PDT 24 |
700358169 ps |
| T588 |
/workspace/coverage/default/43.sram_ctrl_alert_test.3661910557 |
|
|
Mar 10 02:40:47 PM PDT 24 |
Mar 10 02:40:49 PM PDT 24 |
27991106 ps |
| T589 |
/workspace/coverage/default/38.sram_ctrl_regwen.1722449011 |
|
|
Mar 10 02:39:55 PM PDT 24 |
Mar 10 03:02:36 PM PDT 24 |
4968902109 ps |
| T590 |
/workspace/coverage/default/38.sram_ctrl_stress_pipeline.3296802677 |
|
|
Mar 10 02:39:52 PM PDT 24 |
Mar 10 02:45:12 PM PDT 24 |
7935572894 ps |
| T591 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2016097112 |
|
|
Mar 10 02:41:24 PM PDT 24 |
Mar 10 02:42:22 PM PDT 24 |
2352276853 ps |
| T592 |
/workspace/coverage/default/26.sram_ctrl_access_during_key_req.160963928 |
|
|
Mar 10 02:38:17 PM PDT 24 |
Mar 10 02:48:08 PM PDT 24 |
2488002505 ps |
| T593 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.3624683298 |
|
|
Mar 10 02:38:17 PM PDT 24 |
Mar 10 02:45:20 PM PDT 24 |
69136976265 ps |
| T594 |
/workspace/coverage/default/0.sram_ctrl_partial_access.3373532757 |
|
|
Mar 10 02:34:44 PM PDT 24 |
Mar 10 02:35:24 PM PDT 24 |
2116657172 ps |
| T595 |
/workspace/coverage/default/19.sram_ctrl_ram_cfg.1018550738 |
|
|
Mar 10 02:37:09 PM PDT 24 |
Mar 10 02:37:10 PM PDT 24 |
28894483 ps |
| T596 |
/workspace/coverage/default/3.sram_ctrl_partial_access.4064505240 |
|
|
Mar 10 02:35:09 PM PDT 24 |
Mar 10 02:35:27 PM PDT 24 |
939808228 ps |
| T597 |
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2772297002 |
|
|
Mar 10 02:40:57 PM PDT 24 |
Mar 10 02:41:09 PM PDT 24 |
961751584 ps |
| T598 |
/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.2365290444 |
|
|
Mar 10 02:38:29 PM PDT 24 |
Mar 10 02:38:36 PM PDT 24 |
63068902 ps |
| T599 |
/workspace/coverage/default/18.sram_ctrl_multiple_keys.2381823137 |
|
|
Mar 10 02:36:53 PM PDT 24 |
Mar 10 02:48:32 PM PDT 24 |
9655388512 ps |
| T600 |
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.4052795456 |
|
|
Mar 10 02:40:26 PM PDT 24 |
Mar 10 02:46:22 PM PDT 24 |
15998857501 ps |
| T601 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.437697433 |
|
|
Mar 10 02:41:20 PM PDT 24 |
Mar 10 02:41:22 PM PDT 24 |
82235641 ps |
| T602 |
/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.3374582462 |
|
|
Mar 10 02:39:00 PM PDT 24 |
Mar 10 02:39:03 PM PDT 24 |
43716263 ps |
| T603 |
/workspace/coverage/default/13.sram_ctrl_regwen.2709220638 |
|
|
Mar 10 02:36:13 PM PDT 24 |
Mar 10 02:54:09 PM PDT 24 |
98898788908 ps |
| T604 |
/workspace/coverage/default/39.sram_ctrl_partial_access.3334206807 |
|
|
Mar 10 02:40:05 PM PDT 24 |
Mar 10 02:40:13 PM PDT 24 |
144359068 ps |
| T605 |
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.1338440384 |
|
|
Mar 10 02:41:35 PM PDT 24 |
Mar 10 02:41:38 PM PDT 24 |
670453375 ps |
| T606 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.1908028873 |
|
|
Mar 10 02:41:42 PM PDT 24 |
Mar 10 02:41:47 PM PDT 24 |
140496223 ps |
| T607 |
/workspace/coverage/default/2.sram_ctrl_partial_access.3665803782 |
|
|
Mar 10 02:34:59 PM PDT 24 |
Mar 10 02:35:40 PM PDT 24 |
2936119634 ps |
| T608 |
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.1648887483 |
|
|
Mar 10 02:37:26 PM PDT 24 |
Mar 10 02:40:27 PM PDT 24 |
1986397711 ps |
| T609 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.3468074243 |
|
|
Mar 10 02:37:04 PM PDT 24 |
Mar 10 02:39:24 PM PDT 24 |
133162981 ps |
| T610 |
/workspace/coverage/default/45.sram_ctrl_bijection.3486187320 |
|
|
Mar 10 02:41:00 PM PDT 24 |
Mar 10 02:41:44 PM PDT 24 |
8692784573 ps |
| T611 |
/workspace/coverage/default/21.sram_ctrl_smoke.187424988 |
|
|
Mar 10 02:37:27 PM PDT 24 |
Mar 10 02:37:42 PM PDT 24 |
241759881 ps |
| T612 |
/workspace/coverage/default/27.sram_ctrl_mem_walk.2377412446 |
|
|
Mar 10 02:38:25 PM PDT 24 |
Mar 10 02:38:30 PM PDT 24 |
228677608 ps |
| T613 |
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.752279912 |
|
|
Mar 10 02:41:33 PM PDT 24 |
Mar 10 02:50:53 PM PDT 24 |
2288640198 ps |
| T614 |
/workspace/coverage/default/24.sram_ctrl_max_throughput.321510851 |
|
|
Mar 10 02:38:12 PM PDT 24 |
Mar 10 02:38:55 PM PDT 24 |
109316115 ps |
| T615 |
/workspace/coverage/default/4.sram_ctrl_access_during_key_req.3740146240 |
|
|
Mar 10 02:35:13 PM PDT 24 |
Mar 10 02:47:35 PM PDT 24 |
8766204383 ps |
| T616 |
/workspace/coverage/default/0.sram_ctrl_max_throughput.131668137 |
|
|
Mar 10 02:34:43 PM PDT 24 |
Mar 10 02:35:34 PM PDT 24 |
99384390 ps |
| T617 |
/workspace/coverage/default/13.sram_ctrl_alert_test.614948724 |
|
|
Mar 10 02:36:24 PM PDT 24 |
Mar 10 02:36:26 PM PDT 24 |
31960554 ps |
| T618 |
/workspace/coverage/default/37.sram_ctrl_ram_cfg.527534951 |
|
|
Mar 10 02:39:45 PM PDT 24 |
Mar 10 02:39:48 PM PDT 24 |
30608939 ps |
| T619 |
/workspace/coverage/default/11.sram_ctrl_executable.1884973164 |
|
|
Mar 10 02:35:59 PM PDT 24 |
Mar 10 02:41:42 PM PDT 24 |
18651917861 ps |
| T620 |
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.813129473 |
|
|
Mar 10 02:35:55 PM PDT 24 |
Mar 10 02:40:05 PM PDT 24 |
4334281845 ps |
| T621 |
/workspace/coverage/default/49.sram_ctrl_alert_test.210907310 |
|
|
Mar 10 02:41:42 PM PDT 24 |
Mar 10 02:41:43 PM PDT 24 |
38164855 ps |
| T622 |
/workspace/coverage/default/18.sram_ctrl_stress_all.1800250447 |
|
|
Mar 10 02:37:06 PM PDT 24 |
Mar 10 03:34:50 PM PDT 24 |
28208390639 ps |
| T107 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.650329417 |
|
|
Mar 10 02:35:27 PM PDT 24 |
Mar 10 02:36:31 PM PDT 24 |
1524600878 ps |
| T623 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.3700828316 |
|
|
Mar 10 02:36:24 PM PDT 24 |
Mar 10 02:39:13 PM PDT 24 |
12018645342 ps |
| T624 |
/workspace/coverage/default/30.sram_ctrl_max_throughput.1949024447 |
|
|
Mar 10 02:38:49 PM PDT 24 |
Mar 10 02:38:54 PM PDT 24 |
321898733 ps |
| T625 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.711028339 |
|
|
Mar 10 02:40:13 PM PDT 24 |
Mar 10 02:40:15 PM PDT 24 |
46611336 ps |
| T626 |
/workspace/coverage/default/19.sram_ctrl_mem_partial_access.3105357899 |
|
|
Mar 10 02:37:10 PM PDT 24 |
Mar 10 02:37:15 PM PDT 24 |
451979542 ps |
| T627 |
/workspace/coverage/default/4.sram_ctrl_stress_pipeline.2126457329 |
|
|
Mar 10 02:35:11 PM PDT 24 |
Mar 10 02:39:10 PM PDT 24 |
13915735957 ps |
| T628 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.1429002326 |
|
|
Mar 10 02:36:01 PM PDT 24 |
Mar 10 02:57:10 PM PDT 24 |
99172843705 ps |
| T629 |
/workspace/coverage/default/12.sram_ctrl_stress_all.3202207684 |
|
|
Mar 10 02:36:09 PM PDT 24 |
Mar 10 03:13:47 PM PDT 24 |
31767623549 ps |
| T630 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.3019795976 |
|
|
Mar 10 02:35:47 PM PDT 24 |
Mar 10 02:35:54 PM PDT 24 |
191549090 ps |
| T631 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.3886685118 |
|
|
Mar 10 02:36:50 PM PDT 24 |
Mar 10 02:45:41 PM PDT 24 |
7553681091 ps |
| T632 |
/workspace/coverage/default/5.sram_ctrl_executable.2450167921 |
|
|
Mar 10 02:35:23 PM PDT 24 |
Mar 10 02:54:57 PM PDT 24 |
14006406352 ps |
| T633 |
/workspace/coverage/default/34.sram_ctrl_partial_access.3697868667 |
|
|
Mar 10 02:39:20 PM PDT 24 |
Mar 10 02:39:37 PM PDT 24 |
316325035 ps |
| T634 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1950063395 |
|
|
Mar 10 02:40:52 PM PDT 24 |
Mar 10 02:45:34 PM PDT 24 |
22425839402 ps |
| T635 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.636292094 |
|
|
Mar 10 02:41:38 PM PDT 24 |
Mar 10 02:43:09 PM PDT 24 |
908828557 ps |
| T636 |
/workspace/coverage/default/42.sram_ctrl_smoke.3263959836 |
|
|
Mar 10 02:40:26 PM PDT 24 |
Mar 10 02:40:42 PM PDT 24 |
252218895 ps |
| T637 |
/workspace/coverage/default/27.sram_ctrl_alert_test.233299368 |
|
|
Mar 10 02:38:22 PM PDT 24 |
Mar 10 02:38:23 PM PDT 24 |
18162113 ps |
| T638 |
/workspace/coverage/default/7.sram_ctrl_smoke.3504714712 |
|
|
Mar 10 02:35:35 PM PDT 24 |
Mar 10 02:35:39 PM PDT 24 |
865362757 ps |
| T639 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.1291526064 |
|
|
Mar 10 02:40:48 PM PDT 24 |
Mar 10 02:40:49 PM PDT 24 |
108464881 ps |
| T640 |
/workspace/coverage/default/4.sram_ctrl_executable.1005266504 |
|
|
Mar 10 02:35:17 PM PDT 24 |
Mar 10 02:48:30 PM PDT 24 |
2881589761 ps |
| T641 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.2269959197 |
|
|
Mar 10 02:39:40 PM PDT 24 |
Mar 10 02:41:01 PM PDT 24 |
163346745 ps |
| T642 |
/workspace/coverage/default/0.sram_ctrl_bijection.4172593616 |
|
|
Mar 10 02:34:44 PM PDT 24 |
Mar 10 02:35:10 PM PDT 24 |
314852795 ps |
| T643 |
/workspace/coverage/default/10.sram_ctrl_alert_test.2637135461 |
|
|
Mar 10 02:35:59 PM PDT 24 |
Mar 10 02:36:00 PM PDT 24 |
38920995 ps |
| T644 |
/workspace/coverage/default/34.sram_ctrl_ram_cfg.4269944364 |
|
|
Mar 10 02:39:23 PM PDT 24 |
Mar 10 02:39:24 PM PDT 24 |
44535115 ps |
| T645 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.548828937 |
|
|
Mar 10 02:36:50 PM PDT 24 |
Mar 10 02:43:50 PM PDT 24 |
80626902001 ps |
| T646 |
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3970589986 |
|
|
Mar 10 02:40:59 PM PDT 24 |
Mar 10 02:46:23 PM PDT 24 |
12896871978 ps |
| T647 |
/workspace/coverage/default/46.sram_ctrl_bijection.278979340 |
|
|
Mar 10 02:41:14 PM PDT 24 |
Mar 10 02:41:31 PM PDT 24 |
784496297 ps |
| T648 |
/workspace/coverage/default/27.sram_ctrl_mem_partial_access.1367839726 |
|
|
Mar 10 02:38:24 PM PDT 24 |
Mar 10 02:38:27 PM PDT 24 |
375519571 ps |
| T649 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.1074451445 |
|
|
Mar 10 02:35:35 PM PDT 24 |
Mar 10 02:35:44 PM PDT 24 |
1597029350 ps |
| T650 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.33766496 |
|
|
Mar 10 02:39:18 PM PDT 24 |
Mar 10 02:42:33 PM PDT 24 |
2277776023 ps |
| T651 |
/workspace/coverage/default/47.sram_ctrl_mem_walk.1468264365 |
|
|
Mar 10 02:41:24 PM PDT 24 |
Mar 10 02:41:32 PM PDT 24 |
485239592 ps |
| T652 |
/workspace/coverage/default/40.sram_ctrl_access_during_key_req.4076423255 |
|
|
Mar 10 02:40:15 PM PDT 24 |
Mar 10 02:55:01 PM PDT 24 |
23660984571 ps |
| T653 |
/workspace/coverage/default/46.sram_ctrl_regwen.939676466 |
|
|
Mar 10 02:41:13 PM PDT 24 |
Mar 10 03:02:18 PM PDT 24 |
55883089947 ps |
| T654 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.447722680 |
|
|
Mar 10 02:36:13 PM PDT 24 |
Mar 10 02:37:06 PM PDT 24 |
395624612 ps |
| T655 |
/workspace/coverage/default/38.sram_ctrl_smoke.4033966653 |
|
|
Mar 10 02:39:50 PM PDT 24 |
Mar 10 02:39:56 PM PDT 24 |
299070112 ps |
| T656 |
/workspace/coverage/default/9.sram_ctrl_smoke.694734675 |
|
|
Mar 10 02:35:49 PM PDT 24 |
Mar 10 02:36:06 PM PDT 24 |
765906811 ps |
| T657 |
/workspace/coverage/default/26.sram_ctrl_max_throughput.3980691685 |
|
|
Mar 10 02:38:16 PM PDT 24 |
Mar 10 02:38:47 PM PDT 24 |
100043385 ps |
| T658 |
/workspace/coverage/default/22.sram_ctrl_executable.2249346145 |
|
|
Mar 10 02:37:33 PM PDT 24 |
Mar 10 02:46:43 PM PDT 24 |
37812796800 ps |
| T659 |
/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.858067016 |
|
|
Mar 10 02:39:36 PM PDT 24 |
Mar 10 02:40:27 PM PDT 24 |
239309104 ps |
| T660 |
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1593882423 |
|
|
Mar 10 02:41:27 PM PDT 24 |
Mar 10 02:42:10 PM PDT 24 |
153036514 ps |
| T661 |
/workspace/coverage/default/36.sram_ctrl_ram_cfg.3464823671 |
|
|
Mar 10 02:39:39 PM PDT 24 |
Mar 10 02:39:40 PM PDT 24 |
50126124 ps |
| T662 |
/workspace/coverage/default/23.sram_ctrl_mem_walk.1290191666 |
|
|
Mar 10 02:38:10 PM PDT 24 |
Mar 10 02:38:14 PM PDT 24 |
299739242 ps |
| T663 |
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2407164678 |
|
|
Mar 10 02:36:00 PM PDT 24 |
Mar 10 02:38:04 PM PDT 24 |
572700240 ps |
| T664 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2897257238 |
|
|
Mar 10 02:35:25 PM PDT 24 |
Mar 10 02:37:32 PM PDT 24 |
147822787 ps |
| T665 |
/workspace/coverage/default/13.sram_ctrl_stress_all.2305336687 |
|
|
Mar 10 02:36:23 PM PDT 24 |
Mar 10 03:43:53 PM PDT 24 |
18963757280 ps |
| T666 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.3673324122 |
|
|
Mar 10 02:39:25 PM PDT 24 |
Mar 10 02:39:36 PM PDT 24 |
672676566 ps |
| T667 |
/workspace/coverage/default/22.sram_ctrl_partial_access.304059447 |
|
|
Mar 10 02:37:42 PM PDT 24 |
Mar 10 02:38:01 PM PDT 24 |
968902614 ps |
| T668 |
/workspace/coverage/default/36.sram_ctrl_regwen.4273904858 |
|
|
Mar 10 02:39:38 PM PDT 24 |
Mar 10 02:47:45 PM PDT 24 |
59726175176 ps |
| T669 |
/workspace/coverage/default/10.sram_ctrl_stress_all.2792453715 |
|
|
Mar 10 02:35:54 PM PDT 24 |
Mar 10 02:42:50 PM PDT 24 |
32668626854 ps |
| T670 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.427915327 |
|
|
Mar 10 02:36:07 PM PDT 24 |
Mar 10 02:38:50 PM PDT 24 |
1957977967 ps |
| T671 |
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.3845587731 |
|
|
Mar 10 02:41:23 PM PDT 24 |
Mar 10 03:03:24 PM PDT 24 |
14730162306 ps |
| T672 |
/workspace/coverage/default/49.sram_ctrl_bijection.3190245788 |
|
|
Mar 10 02:41:36 PM PDT 24 |
Mar 10 02:42:35 PM PDT 24 |
3684306737 ps |
| T673 |
/workspace/coverage/default/44.sram_ctrl_bijection.929381796 |
|
|
Mar 10 02:40:50 PM PDT 24 |
Mar 10 02:41:45 PM PDT 24 |
4552681083 ps |
| T674 |
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1452785629 |
|
|
Mar 10 02:41:38 PM PDT 24 |
Mar 10 02:43:36 PM PDT 24 |
1644775484 ps |
| T675 |
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.223566981 |
|
|
Mar 10 02:38:12 PM PDT 24 |
Mar 10 02:39:21 PM PDT 24 |
957619590 ps |
| T676 |
/workspace/coverage/default/48.sram_ctrl_alert_test.383537199 |
|
|
Mar 10 02:41:34 PM PDT 24 |
Mar 10 02:41:34 PM PDT 24 |
15957081 ps |
| T677 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.2185886312 |
|
|
Mar 10 02:37:29 PM PDT 24 |
Mar 10 02:37:34 PM PDT 24 |
606098717 ps |
| T678 |
/workspace/coverage/default/12.sram_ctrl_smoke.2321338759 |
|
|
Mar 10 02:36:03 PM PDT 24 |
Mar 10 02:36:19 PM PDT 24 |
1414165455 ps |
| T679 |
/workspace/coverage/default/16.sram_ctrl_smoke.2914730827 |
|
|
Mar 10 02:36:39 PM PDT 24 |
Mar 10 02:36:42 PM PDT 24 |
93985900 ps |
| T680 |
/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.2875448109 |
|
|
Mar 10 02:38:48 PM PDT 24 |
Mar 10 02:41:40 PM PDT 24 |
14431046655 ps |
| T681 |
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.440077991 |
|
|
Mar 10 02:40:44 PM PDT 24 |
Mar 10 02:47:23 PM PDT 24 |
3034836133 ps |
| T682 |
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2170018203 |
|
|
Mar 10 02:34:57 PM PDT 24 |
Mar 10 02:37:23 PM PDT 24 |
4111507885 ps |
| T683 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.558014307 |
|
|
Mar 10 02:35:35 PM PDT 24 |
Mar 10 02:36:46 PM PDT 24 |
1051716213 ps |
| T684 |
/workspace/coverage/default/4.sram_ctrl_smoke.4150979649 |
|
|
Mar 10 02:35:14 PM PDT 24 |
Mar 10 02:35:22 PM PDT 24 |
1810084684 ps |
| T685 |
/workspace/coverage/default/12.sram_ctrl_ram_cfg.1202299398 |
|
|
Mar 10 02:36:11 PM PDT 24 |
Mar 10 02:36:12 PM PDT 24 |
79370458 ps |
| T686 |
/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.2474862074 |
|
|
Mar 10 02:36:56 PM PDT 24 |
Mar 10 02:39:30 PM PDT 24 |
14725019198 ps |
| T687 |
/workspace/coverage/default/31.sram_ctrl_ram_cfg.1558049852 |
|
|
Mar 10 02:38:55 PM PDT 24 |
Mar 10 02:38:56 PM PDT 24 |
42456709 ps |
| T688 |
/workspace/coverage/default/40.sram_ctrl_stress_all.318736801 |
|
|
Mar 10 02:40:23 PM PDT 24 |
Mar 10 03:55:31 PM PDT 24 |
302091555919 ps |
| T34 |
/workspace/coverage/default/0.sram_ctrl_sec_cm.4113449434 |
|
|
Mar 10 02:34:46 PM PDT 24 |
Mar 10 02:34:53 PM PDT 24 |
814354141 ps |
| T689 |
/workspace/coverage/default/47.sram_ctrl_regwen.390525586 |
|
|
Mar 10 02:41:23 PM PDT 24 |
Mar 10 03:07:55 PM PDT 24 |
49772460755 ps |
| T690 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3687712632 |
|
|
Mar 10 02:37:21 PM PDT 24 |
Mar 10 02:37:56 PM PDT 24 |
4731994463 ps |
| T691 |
/workspace/coverage/default/30.sram_ctrl_executable.981917003 |
|
|
Mar 10 02:38:48 PM PDT 24 |
Mar 10 02:39:16 PM PDT 24 |
1350868025 ps |
| T692 |
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.1126350990 |
|
|
Mar 10 02:36:23 PM PDT 24 |
Mar 10 02:38:11 PM PDT 24 |
144532895 ps |
| T693 |
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.4100803930 |
|
|
Mar 10 02:35:30 PM PDT 24 |
Mar 10 02:43:54 PM PDT 24 |
2163747940 ps |
| T694 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.371089875 |
|
|
Mar 10 02:40:01 PM PDT 24 |
Mar 10 02:40:06 PM PDT 24 |
154758607 ps |
| T695 |
/workspace/coverage/default/34.sram_ctrl_max_throughput.2706633948 |
|
|
Mar 10 02:39:18 PM PDT 24 |
Mar 10 02:39:37 PM PDT 24 |
285870686 ps |
| T696 |
/workspace/coverage/default/31.sram_ctrl_partial_access.49406947 |
|
|
Mar 10 02:38:49 PM PDT 24 |
Mar 10 02:40:46 PM PDT 24 |
391318993 ps |
| T697 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1087113423 |
|
|
Mar 10 02:34:45 PM PDT 24 |
Mar 10 02:36:47 PM PDT 24 |
601491722 ps |
| T698 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.1685918951 |
|
|
Mar 10 02:35:58 PM PDT 24 |
Mar 10 02:36:02 PM PDT 24 |
136803515 ps |
| T699 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.1167209836 |
|
|
Mar 10 02:34:55 PM PDT 24 |
Mar 10 02:35:54 PM PDT 24 |
104577119 ps |
| T700 |
/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.2728916058 |
|
|
Mar 10 02:35:01 PM PDT 24 |
Mar 10 02:41:16 PM PDT 24 |
19109562720 ps |
| T108 |
/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.2559202567 |
|
|
Mar 10 02:37:30 PM PDT 24 |
Mar 10 02:37:46 PM PDT 24 |
525790298 ps |
| T701 |
/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.1176488372 |
|
|
Mar 10 02:39:40 PM PDT 24 |
Mar 10 02:45:10 PM PDT 24 |
133658366352 ps |
| T702 |
/workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.760669652 |
|
|
Mar 10 02:38:13 PM PDT 24 |
Mar 10 02:38:49 PM PDT 24 |
2237228334 ps |
| T703 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.2379471467 |
|
|
Mar 10 02:41:02 PM PDT 24 |
Mar 10 02:43:45 PM PDT 24 |
612937867 ps |
| T704 |
/workspace/coverage/default/1.sram_ctrl_multiple_keys.2353946657 |
|
|
Mar 10 02:34:46 PM PDT 24 |
Mar 10 02:53:29 PM PDT 24 |
9218715339 ps |
| T705 |
/workspace/coverage/default/44.sram_ctrl_partial_access.2527767667 |
|
|
Mar 10 02:40:51 PM PDT 24 |
Mar 10 02:40:58 PM PDT 24 |
132293289 ps |
| T706 |
/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.1880778291 |
|
|
Mar 10 02:38:22 PM PDT 24 |
Mar 10 02:45:56 PM PDT 24 |
20870863946 ps |
| T707 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.440149539 |
|
|
Mar 10 02:41:13 PM PDT 24 |
Mar 10 02:47:10 PM PDT 24 |
5135781043 ps |
| T708 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.1572680014 |
|
|
Mar 10 02:39:42 PM PDT 24 |
Mar 10 02:51:08 PM PDT 24 |
2251904270 ps |
| T709 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.1515744009 |
|
|
Mar 10 02:34:43 PM PDT 24 |
Mar 10 02:35:12 PM PDT 24 |
1782228277 ps |
| T109 |
/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.3458937179 |
|
|
Mar 10 02:39:29 PM PDT 24 |
Mar 10 02:40:03 PM PDT 24 |
1516046016 ps |
| T710 |
/workspace/coverage/default/33.sram_ctrl_multiple_keys.1190827903 |
|
|
Mar 10 02:39:07 PM PDT 24 |
Mar 10 02:49:37 PM PDT 24 |
14169792556 ps |
| T711 |
/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.4207273738 |
|
|
Mar 10 02:38:56 PM PDT 24 |
Mar 10 02:41:37 PM PDT 24 |
300907469 ps |
| T712 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.2036031552 |
|
|
Mar 10 02:36:27 PM PDT 24 |
Mar 10 02:36:34 PM PDT 24 |
58236444 ps |
| T713 |
/workspace/coverage/default/11.sram_ctrl_partial_access.2385423934 |
|
|
Mar 10 02:36:00 PM PDT 24 |
Mar 10 02:36:18 PM PDT 24 |
4454708774 ps |
| T714 |
/workspace/coverage/default/31.sram_ctrl_lc_escalation.1729430414 |
|
|
Mar 10 02:38:54 PM PDT 24 |
Mar 10 02:39:18 PM PDT 24 |
2125897028 ps |
| T715 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.1473083531 |
|
|
Mar 10 02:35:40 PM PDT 24 |
Mar 10 02:40:57 PM PDT 24 |
3346060144 ps |
| T716 |
/workspace/coverage/default/23.sram_ctrl_bijection.975181456 |
|
|
Mar 10 02:37:40 PM PDT 24 |
Mar 10 02:38:14 PM PDT 24 |
2136000619 ps |
| T717 |
/workspace/coverage/default/6.sram_ctrl_max_throughput.759612711 |
|
|
Mar 10 02:35:25 PM PDT 24 |
Mar 10 02:36:19 PM PDT 24 |
100285715 ps |
| T718 |
/workspace/coverage/default/8.sram_ctrl_partial_access.1509652439 |
|
|
Mar 10 02:35:42 PM PDT 24 |
Mar 10 02:35:45 PM PDT 24 |
42891164 ps |
| T719 |
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3970833247 |
|
|
Mar 10 02:37:15 PM PDT 24 |
Mar 10 02:40:07 PM PDT 24 |
4211897249 ps |
| T720 |
/workspace/coverage/default/28.sram_ctrl_partial_access.1936269655 |
|
|
Mar 10 02:38:24 PM PDT 24 |
Mar 10 02:39:28 PM PDT 24 |
1697434494 ps |
| T721 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.2684466227 |
|
|
Mar 10 02:36:42 PM PDT 24 |
Mar 10 02:38:11 PM PDT 24 |
128940443 ps |
| T722 |
/workspace/coverage/default/12.sram_ctrl_regwen.1484656587 |
|
|
Mar 10 02:36:12 PM PDT 24 |
Mar 10 02:54:03 PM PDT 24 |
4480810186 ps |
| T723 |
/workspace/coverage/default/24.sram_ctrl_multiple_keys.3306516163 |
|
|
Mar 10 02:38:11 PM PDT 24 |
Mar 10 02:45:17 PM PDT 24 |
16251694537 ps |
| T724 |
/workspace/coverage/default/17.sram_ctrl_max_throughput.104106479 |
|
|
Mar 10 02:36:50 PM PDT 24 |
Mar 10 02:37:36 PM PDT 24 |
416384650 ps |
| T725 |
/workspace/coverage/default/35.sram_ctrl_alert_test.2508968982 |
|
|
Mar 10 02:39:36 PM PDT 24 |
Mar 10 02:39:37 PM PDT 24 |
15629948 ps |
| T726 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.1163254869 |
|
|
Mar 10 02:37:25 PM PDT 24 |
Mar 10 02:54:26 PM PDT 24 |
35461318138 ps |
| T727 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.2150417425 |
|
|
Mar 10 02:41:15 PM PDT 24 |
Mar 10 02:43:12 PM PDT 24 |
1910614673 ps |
| T728 |
/workspace/coverage/default/18.sram_ctrl_access_during_key_req.3667266018 |
|
|
Mar 10 02:36:59 PM PDT 24 |
Mar 10 02:46:53 PM PDT 24 |
6833488475 ps |
| T729 |
/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.2111226054 |
|
|
Mar 10 02:38:11 PM PDT 24 |
Mar 10 02:45:12 PM PDT 24 |
18948695884 ps |
| T730 |
/workspace/coverage/default/49.sram_ctrl_lc_escalation.4177405301 |
|
|
Mar 10 02:41:38 PM PDT 24 |
Mar 10 02:41:50 PM PDT 24 |
904298750 ps |
| T731 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.3603888796 |
|
|
Mar 10 02:40:31 PM PDT 24 |
Mar 10 02:46:22 PM PDT 24 |
25834559070 ps |
| T732 |
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.3483072663 |
|
|
Mar 10 02:37:39 PM PDT 24 |
Mar 10 02:43:05 PM PDT 24 |
59384727466 ps |
| T733 |
/workspace/coverage/default/32.sram_ctrl_regwen.4205203227 |
|
|
Mar 10 02:39:04 PM PDT 24 |
Mar 10 03:03:35 PM PDT 24 |
63912031822 ps |
| T734 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.2975815999 |
|
|
Mar 10 02:35:30 PM PDT 24 |
Mar 10 02:35:33 PM PDT 24 |
335233875 ps |
| T735 |
/workspace/coverage/default/32.sram_ctrl_bijection.1885587911 |
|
|
Mar 10 02:39:00 PM PDT 24 |
Mar 10 02:40:05 PM PDT 24 |
969140909 ps |
| T736 |
/workspace/coverage/default/35.sram_ctrl_bijection.2912981002 |
|
|
Mar 10 02:39:22 PM PDT 24 |
Mar 10 02:40:23 PM PDT 24 |
4609998591 ps |
| T737 |
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.2231582123 |
|
|
Mar 10 02:40:55 PM PDT 24 |
Mar 10 02:52:25 PM PDT 24 |
1498698665 ps |
| T738 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.4085397492 |
|
|
Mar 10 02:35:35 PM PDT 24 |
Mar 10 02:35:59 PM PDT 24 |
1861070162 ps |
| T110 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.4247892698 |
|
|
Mar 10 02:35:46 PM PDT 24 |
Mar 10 02:38:43 PM PDT 24 |
1816304620 ps |
| T739 |
/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3059700171 |
|
|
Mar 10 02:35:13 PM PDT 24 |
Mar 10 02:42:35 PM PDT 24 |
6322997551 ps |
| T740 |
/workspace/coverage/default/29.sram_ctrl_smoke.1810719782 |
|
|
Mar 10 02:38:32 PM PDT 24 |
Mar 10 02:38:44 PM PDT 24 |
835844864 ps |
| T741 |
/workspace/coverage/default/26.sram_ctrl_mem_partial_access.2118789407 |
|
|
Mar 10 02:38:18 PM PDT 24 |
Mar 10 02:38:21 PM PDT 24 |
176150668 ps |
| T742 |
/workspace/coverage/default/6.sram_ctrl_bijection.3076266500 |
|
|
Mar 10 02:35:25 PM PDT 24 |
Mar 10 02:36:24 PM PDT 24 |
2854843635 ps |
| T743 |
/workspace/coverage/default/11.sram_ctrl_bijection.4253523357 |
|
|
Mar 10 02:35:59 PM PDT 24 |
Mar 10 02:37:01 PM PDT 24 |
6395906915 ps |
| T744 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.57477874 |
|
|
Mar 10 02:36:10 PM PDT 24 |
Mar 10 02:42:08 PM PDT 24 |
583485488 ps |
| T745 |
/workspace/coverage/default/28.sram_ctrl_stress_all.2844865089 |
|
|
Mar 10 02:38:29 PM PDT 24 |
Mar 10 03:10:18 PM PDT 24 |
16201236969 ps |
| T746 |
/workspace/coverage/default/41.sram_ctrl_mem_walk.782615393 |
|
|
Mar 10 02:40:26 PM PDT 24 |
Mar 10 02:40:37 PM PDT 24 |
4675094670 ps |
| T747 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.2694102994 |
|
|
Mar 10 02:41:39 PM PDT 24 |
Mar 10 02:41:40 PM PDT 24 |
27719472 ps |
| T748 |
/workspace/coverage/default/17.sram_ctrl_mem_walk.28617773 |
|
|
Mar 10 02:36:56 PM PDT 24 |
Mar 10 02:37:05 PM PDT 24 |
458470110 ps |
| T749 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.2152228815 |
|
|
Mar 10 02:41:16 PM PDT 24 |
Mar 10 02:51:10 PM PDT 24 |
11200352225 ps |
| T750 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3253908221 |
|
|
Mar 10 02:35:23 PM PDT 24 |
Mar 10 02:37:51 PM PDT 24 |
635880428 ps |
| T751 |
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.3007386847 |
|
|
Mar 10 02:39:04 PM PDT 24 |
Mar 10 02:41:19 PM PDT 24 |
1431243842 ps |
| T752 |
/workspace/coverage/default/22.sram_ctrl_stress_all.3428367797 |
|
|
Mar 10 02:37:40 PM PDT 24 |
Mar 10 03:03:43 PM PDT 24 |
35400145378 ps |
| T753 |
/workspace/coverage/default/7.sram_ctrl_alert_test.3028186276 |
|
|
Mar 10 02:35:42 PM PDT 24 |
Mar 10 02:35:44 PM PDT 24 |
42653763 ps |
| T754 |
/workspace/coverage/default/35.sram_ctrl_smoke.2023171285 |
|
|
Mar 10 02:39:26 PM PDT 24 |
Mar 10 02:39:33 PM PDT 24 |
339368851 ps |
| T755 |
/workspace/coverage/default/33.sram_ctrl_mem_walk.4156519329 |
|
|
Mar 10 02:39:14 PM PDT 24 |
Mar 10 02:39:25 PM PDT 24 |
138398091 ps |
| T756 |
/workspace/coverage/default/5.sram_ctrl_bijection.4076234797 |
|
|
Mar 10 02:35:20 PM PDT 24 |
Mar 10 02:36:04 PM PDT 24 |
9835654618 ps |
| T757 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.1697293248 |
|
|
Mar 10 02:35:44 PM PDT 24 |
Mar 10 02:54:54 PM PDT 24 |
3843163003 ps |
| T758 |
/workspace/coverage/default/35.sram_ctrl_stress_all.1606334004 |
|
|
Mar 10 02:39:27 PM PDT 24 |
Mar 10 03:00:55 PM PDT 24 |
16100333986 ps |
| T759 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.25413187 |
|
|
Mar 10 02:34:44 PM PDT 24 |
Mar 10 02:38:49 PM PDT 24 |
9592933005 ps |
| T760 |
/workspace/coverage/default/49.sram_ctrl_regwen.3660810914 |
|
|
Mar 10 02:41:38 PM PDT 24 |
Mar 10 03:33:38 PM PDT 24 |
76115252619 ps |
| T761 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.2749267446 |
|
|
Mar 10 02:36:05 PM PDT 24 |
Mar 10 03:08:20 PM PDT 24 |
9876070418 ps |
| T762 |
/workspace/coverage/default/26.sram_ctrl_partial_access.1182188005 |
|
|
Mar 10 02:38:16 PM PDT 24 |
Mar 10 02:39:04 PM PDT 24 |
1856910750 ps |
| T763 |
/workspace/coverage/default/23.sram_ctrl_max_throughput.996997990 |
|
|
Mar 10 02:37:40 PM PDT 24 |
Mar 10 02:38:25 PM PDT 24 |
191257643 ps |
| T764 |
/workspace/coverage/default/15.sram_ctrl_lc_escalation.3705404959 |
|
|
Mar 10 02:36:35 PM PDT 24 |
Mar 10 02:36:41 PM PDT 24 |
274420813 ps |
| T765 |
/workspace/coverage/default/39.sram_ctrl_bijection.4173114314 |
|
|
Mar 10 02:40:05 PM PDT 24 |
Mar 10 02:40:49 PM PDT 24 |
2822067000 ps |
| T766 |
/workspace/coverage/default/25.sram_ctrl_regwen.356747092 |
|
|
Mar 10 02:38:17 PM PDT 24 |
Mar 10 03:07:03 PM PDT 24 |
25158830680 ps |
| T767 |
/workspace/coverage/default/11.sram_ctrl_mem_walk.2600366479 |
|
|
Mar 10 02:36:05 PM PDT 24 |
Mar 10 02:36:14 PM PDT 24 |
908867887 ps |
| T768 |
/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.4141815117 |
|
|
Mar 10 02:35:05 PM PDT 24 |
Mar 10 02:35:06 PM PDT 24 |
127888046 ps |
| T769 |
/workspace/coverage/default/14.sram_ctrl_stress_all.2509779909 |
|
|
Mar 10 02:36:29 PM PDT 24 |
Mar 10 03:32:20 PM PDT 24 |
22089937668 ps |
| T770 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.3107222952 |
|
|
Mar 10 02:39:20 PM PDT 24 |
Mar 10 02:59:02 PM PDT 24 |
9677760676 ps |
| T771 |
/workspace/coverage/default/27.sram_ctrl_executable.1158901057 |
|
|
Mar 10 02:38:21 PM PDT 24 |
Mar 10 02:59:58 PM PDT 24 |
16573526074 ps |
| T772 |
/workspace/coverage/default/26.sram_ctrl_bijection.3268946607 |
|
|
Mar 10 02:38:16 PM PDT 24 |
Mar 10 02:38:33 PM PDT 24 |
1016159723 ps |
| T773 |
/workspace/coverage/default/40.sram_ctrl_bijection.3589048098 |
|
|
Mar 10 02:40:10 PM PDT 24 |
Mar 10 02:40:58 PM PDT 24 |
3184235519 ps |
| T774 |
/workspace/coverage/default/15.sram_ctrl_regwen.2444153859 |
|
|
Mar 10 02:36:38 PM PDT 24 |
Mar 10 02:58:36 PM PDT 24 |
14445774646 ps |
| T775 |
/workspace/coverage/default/20.sram_ctrl_alert_test.762793888 |
|
|
Mar 10 02:37:25 PM PDT 24 |
Mar 10 02:37:26 PM PDT 24 |
44034588 ps |
| T776 |
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.4273270198 |
|
|
Mar 10 02:35:35 PM PDT 24 |
Mar 10 02:35:39 PM PDT 24 |
52505801 ps |
| T777 |
/workspace/coverage/default/38.sram_ctrl_stress_all.1676434620 |
|
|
Mar 10 02:40:00 PM PDT 24 |
Mar 10 02:57:46 PM PDT 24 |
4638935485 ps |
| T778 |
/workspace/coverage/default/9.sram_ctrl_partial_access.239715666 |
|
|
Mar 10 02:35:49 PM PDT 24 |
Mar 10 02:36:05 PM PDT 24 |
286146923 ps |
| T779 |
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.338578770 |
|
|
Mar 10 02:40:46 PM PDT 24 |
Mar 10 02:40:59 PM PDT 24 |
326636383 ps |
| T780 |
/workspace/coverage/default/24.sram_ctrl_mem_partial_access.1637698772 |
|
|
Mar 10 02:38:12 PM PDT 24 |
Mar 10 02:38:16 PM PDT 24 |
243168180 ps |
| T781 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.1412204630 |
|
|
Mar 10 02:36:14 PM PDT 24 |
Mar 10 02:37:55 PM PDT 24 |
411021338 ps |
| T782 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.1883623818 |
|
|
Mar 10 02:39:42 PM PDT 24 |
Mar 10 02:39:55 PM PDT 24 |
1264164842 ps |
| T111 |
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3380539465 |
|
|
Mar 10 02:40:37 PM PDT 24 |
Mar 10 02:44:17 PM PDT 24 |
7180851418 ps |
| T783 |
/workspace/coverage/default/30.sram_ctrl_bijection.3429098992 |
|
|
Mar 10 02:38:50 PM PDT 24 |
Mar 10 02:39:45 PM PDT 24 |
5877384680 ps |
| T784 |
/workspace/coverage/default/31.sram_ctrl_stress_all.2461597135 |
|
|
Mar 10 02:38:53 PM PDT 24 |
Mar 10 03:01:39 PM PDT 24 |
24173006262 ps |
| T785 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.3397279957 |
|
|
Mar 10 02:38:11 PM PDT 24 |
Mar 10 02:38:16 PM PDT 24 |
603083246 ps |
| T786 |
/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.4223470958 |
|
|
Mar 10 02:38:10 PM PDT 24 |
Mar 10 02:43:57 PM PDT 24 |
5101885238 ps |
| T787 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.2684544608 |
|
|
Mar 10 02:39:33 PM PDT 24 |
Mar 10 02:48:45 PM PDT 24 |
90624723797 ps |
| T788 |
/workspace/coverage/default/28.sram_ctrl_mem_walk.4181794249 |
|
|
Mar 10 02:38:27 PM PDT 24 |
Mar 10 02:38:32 PM PDT 24 |
150441786 ps |