| T789 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.4201240154 |
|
|
Mar 10 02:41:20 PM PDT 24 |
Mar 10 02:46:15 PM PDT 24 |
11816173603 ps |
| T790 |
/workspace/coverage/default/22.sram_ctrl_multiple_keys.3998910398 |
|
|
Mar 10 02:37:42 PM PDT 24 |
Mar 10 02:43:18 PM PDT 24 |
22688770187 ps |
| T791 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.3005890121 |
|
|
Mar 10 02:39:00 PM PDT 24 |
Mar 10 02:47:30 PM PDT 24 |
83356737358 ps |
| T792 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.2981772696 |
|
|
Mar 10 02:35:34 PM PDT 24 |
Mar 10 02:35:35 PM PDT 24 |
79202236 ps |
| T793 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.3261197277 |
|
|
Mar 10 02:40:42 PM PDT 24 |
Mar 10 02:41:13 PM PDT 24 |
2631737342 ps |
| T794 |
/workspace/coverage/default/4.sram_ctrl_stress_all.50224032 |
|
|
Mar 10 02:35:18 PM PDT 24 |
Mar 10 03:38:23 PM PDT 24 |
24191204828 ps |
| T795 |
/workspace/coverage/default/9.sram_ctrl_stress_all.1288444634 |
|
|
Mar 10 02:35:46 PM PDT 24 |
Mar 10 02:58:31 PM PDT 24 |
16099612396 ps |
| T796 |
/workspace/coverage/default/8.sram_ctrl_stress_all.554963437 |
|
|
Mar 10 02:35:45 PM PDT 24 |
Mar 10 03:10:31 PM PDT 24 |
89830681836 ps |
| T797 |
/workspace/coverage/default/39.sram_ctrl_alert_test.311043376 |
|
|
Mar 10 02:40:11 PM PDT 24 |
Mar 10 02:40:12 PM PDT 24 |
42027811 ps |
| T798 |
/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.3483782759 |
|
|
Mar 10 02:36:41 PM PDT 24 |
Mar 10 02:40:17 PM PDT 24 |
16953605988 ps |
| T799 |
/workspace/coverage/default/10.sram_ctrl_executable.1650072018 |
|
|
Mar 10 02:35:59 PM PDT 24 |
Mar 10 02:50:47 PM PDT 24 |
3245292989 ps |
| T800 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.1772637160 |
|
|
Mar 10 02:38:18 PM PDT 24 |
Mar 10 02:38:18 PM PDT 24 |
26761324 ps |
| T801 |
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.3362612923 |
|
|
Mar 10 02:38:51 PM PDT 24 |
Mar 10 02:41:54 PM PDT 24 |
10672595541 ps |
| T802 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3001841015 |
|
|
Mar 10 02:41:19 PM PDT 24 |
Mar 10 02:49:34 PM PDT 24 |
2590896446 ps |
| T803 |
/workspace/coverage/default/4.sram_ctrl_regwen.3793767519 |
|
|
Mar 10 02:35:18 PM PDT 24 |
Mar 10 02:45:25 PM PDT 24 |
2592354018 ps |
| T804 |
/workspace/coverage/default/34.sram_ctrl_smoke.3344843019 |
|
|
Mar 10 02:39:15 PM PDT 24 |
Mar 10 02:41:59 PM PDT 24 |
2653228656 ps |
| T805 |
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.2652544982 |
|
|
Mar 10 02:35:34 PM PDT 24 |
Mar 10 02:43:12 PM PDT 24 |
17444537160 ps |
| T806 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.880753650 |
|
|
Mar 10 02:40:33 PM PDT 24 |
Mar 10 02:40:38 PM PDT 24 |
57055733 ps |
| T807 |
/workspace/coverage/default/2.sram_ctrl_bijection.1699263694 |
|
|
Mar 10 02:34:57 PM PDT 24 |
Mar 10 02:35:34 PM PDT 24 |
7249445263 ps |
| T808 |
/workspace/coverage/default/35.sram_ctrl_multiple_keys.2257239744 |
|
|
Mar 10 02:39:23 PM PDT 24 |
Mar 10 02:57:08 PM PDT 24 |
35669442422 ps |
| T809 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1712451776 |
|
|
Mar 10 02:34:44 PM PDT 24 |
Mar 10 02:40:29 PM PDT 24 |
70787912906 ps |
| T810 |
/workspace/coverage/default/38.sram_ctrl_executable.3750076817 |
|
|
Mar 10 02:39:55 PM PDT 24 |
Mar 10 02:46:08 PM PDT 24 |
4262727812 ps |
| T811 |
/workspace/coverage/default/19.sram_ctrl_executable.2407441503 |
|
|
Mar 10 02:37:10 PM PDT 24 |
Mar 10 03:09:43 PM PDT 24 |
112182090720 ps |
| T812 |
/workspace/coverage/default/18.sram_ctrl_smoke.3641418793 |
|
|
Mar 10 02:36:53 PM PDT 24 |
Mar 10 02:39:08 PM PDT 24 |
670956567 ps |
| T813 |
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3569225460 |
|
|
Mar 10 02:39:15 PM PDT 24 |
Mar 10 02:40:09 PM PDT 24 |
437069676 ps |
| T814 |
/workspace/coverage/default/27.sram_ctrl_regwen.2666181787 |
|
|
Mar 10 02:38:22 PM PDT 24 |
Mar 10 02:46:19 PM PDT 24 |
8723835386 ps |
| T815 |
/workspace/coverage/default/39.sram_ctrl_lc_escalation.3090039507 |
|
|
Mar 10 02:40:06 PM PDT 24 |
Mar 10 02:40:18 PM PDT 24 |
835739149 ps |
| T816 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.4119144471 |
|
|
Mar 10 02:35:31 PM PDT 24 |
Mar 10 02:55:21 PM PDT 24 |
34124166121 ps |
| T817 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.220154024 |
|
|
Mar 10 02:38:18 PM PDT 24 |
Mar 10 02:38:28 PM PDT 24 |
594927166 ps |
| T818 |
/workspace/coverage/default/10.sram_ctrl_smoke.2273457588 |
|
|
Mar 10 02:35:49 PM PDT 24 |
Mar 10 02:36:30 PM PDT 24 |
312104848 ps |
| T819 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.426036740 |
|
|
Mar 10 02:41:17 PM PDT 24 |
Mar 10 02:44:05 PM PDT 24 |
687754700 ps |
| T820 |
/workspace/coverage/default/28.sram_ctrl_alert_test.927698964 |
|
|
Mar 10 02:38:32 PM PDT 24 |
Mar 10 02:38:33 PM PDT 24 |
51281080 ps |
| T821 |
/workspace/coverage/default/16.sram_ctrl_ram_cfg.1907634385 |
|
|
Mar 10 02:36:44 PM PDT 24 |
Mar 10 02:36:45 PM PDT 24 |
65082101 ps |
| T822 |
/workspace/coverage/default/11.sram_ctrl_regwen.1263177043 |
|
|
Mar 10 02:36:04 PM PDT 24 |
Mar 10 02:51:04 PM PDT 24 |
65975553364 ps |
| T823 |
/workspace/coverage/default/32.sram_ctrl_mem_walk.19777979 |
|
|
Mar 10 02:39:04 PM PDT 24 |
Mar 10 02:39:09 PM PDT 24 |
73962842 ps |
| T824 |
/workspace/coverage/default/17.sram_ctrl_bijection.3128702147 |
|
|
Mar 10 02:36:50 PM PDT 24 |
Mar 10 02:37:55 PM PDT 24 |
4527306149 ps |
| T825 |
/workspace/coverage/default/33.sram_ctrl_partial_access.3439462993 |
|
|
Mar 10 02:39:09 PM PDT 24 |
Mar 10 02:39:52 PM PDT 24 |
1860308787 ps |
| T826 |
/workspace/coverage/default/30.sram_ctrl_lc_escalation.3072300345 |
|
|
Mar 10 02:38:47 PM PDT 24 |
Mar 10 02:39:00 PM PDT 24 |
774968955 ps |
| T827 |
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.2027396527 |
|
|
Mar 10 02:35:01 PM PDT 24 |
Mar 10 02:35:04 PM PDT 24 |
351154028 ps |
| T828 |
/workspace/coverage/default/14.sram_ctrl_smoke.1441959204 |
|
|
Mar 10 02:36:24 PM PDT 24 |
Mar 10 02:36:36 PM PDT 24 |
227411438 ps |
| T829 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.3152847671 |
|
|
Mar 10 02:36:21 PM PDT 24 |
Mar 10 02:36:22 PM PDT 24 |
44582429 ps |
| T830 |
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.1310780621 |
|
|
Mar 10 02:40:38 PM PDT 24 |
Mar 10 02:40:42 PM PDT 24 |
232380734 ps |
| T831 |
/workspace/coverage/default/16.sram_ctrl_max_throughput.1226844102 |
|
|
Mar 10 02:36:38 PM PDT 24 |
Mar 10 02:37:34 PM PDT 24 |
194228679 ps |
| T832 |
/workspace/coverage/default/27.sram_ctrl_stress_all.971319208 |
|
|
Mar 10 02:38:24 PM PDT 24 |
Mar 10 04:00:35 PM PDT 24 |
62191776090 ps |
| T833 |
/workspace/coverage/default/30.sram_ctrl_stress_all.504210715 |
|
|
Mar 10 02:38:50 PM PDT 24 |
Mar 10 03:45:10 PM PDT 24 |
21851293254 ps |
| T834 |
/workspace/coverage/default/32.sram_ctrl_stress_pipeline.301930554 |
|
|
Mar 10 02:38:59 PM PDT 24 |
Mar 10 02:41:42 PM PDT 24 |
3640634607 ps |
| T835 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.2556585139 |
|
|
Mar 10 02:38:49 PM PDT 24 |
Mar 10 02:38:52 PM PDT 24 |
69342028 ps |
| T836 |
/workspace/coverage/default/20.sram_ctrl_partial_access.3361659249 |
|
|
Mar 10 02:37:15 PM PDT 24 |
Mar 10 02:37:32 PM PDT 24 |
318780635 ps |
| T837 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.3563132831 |
|
|
Mar 10 02:36:34 PM PDT 24 |
Mar 10 02:41:26 PM PDT 24 |
11450753123 ps |
| T838 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.3735464224 |
|
|
Mar 10 02:39:32 PM PDT 24 |
Mar 10 02:43:14 PM PDT 24 |
9233061240 ps |
| T839 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1239320072 |
|
|
Mar 10 02:41:13 PM PDT 24 |
Mar 10 02:41:17 PM PDT 24 |
533325883 ps |
| T840 |
/workspace/coverage/default/1.sram_ctrl_max_throughput.249080200 |
|
|
Mar 10 02:34:53 PM PDT 24 |
Mar 10 02:34:59 PM PDT 24 |
60546442 ps |
| T841 |
/workspace/coverage/default/2.sram_ctrl_stress_pipeline.2649895578 |
|
|
Mar 10 02:35:01 PM PDT 24 |
Mar 10 02:41:27 PM PDT 24 |
4056621457 ps |
| T842 |
/workspace/coverage/default/29.sram_ctrl_mem_partial_access.424071430 |
|
|
Mar 10 02:38:41 PM PDT 24 |
Mar 10 02:38:46 PM PDT 24 |
655629494 ps |
| T843 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.158878587 |
|
|
Mar 10 02:38:11 PM PDT 24 |
Mar 10 02:40:45 PM PDT 24 |
374331797 ps |
| T844 |
/workspace/coverage/default/43.sram_ctrl_bijection.2299026433 |
|
|
Mar 10 02:40:43 PM PDT 24 |
Mar 10 02:42:03 PM PDT 24 |
5242944782 ps |
| T845 |
/workspace/coverage/default/44.sram_ctrl_executable.3610373969 |
|
|
Mar 10 02:40:56 PM PDT 24 |
Mar 10 03:06:47 PM PDT 24 |
91812053069 ps |
| T846 |
/workspace/coverage/default/40.sram_ctrl_mem_walk.2713004125 |
|
|
Mar 10 02:40:22 PM PDT 24 |
Mar 10 02:40:26 PM PDT 24 |
79043295 ps |
| T847 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.2366213487 |
|
|
Mar 10 02:36:38 PM PDT 24 |
Mar 10 02:36:41 PM PDT 24 |
343809762 ps |
| T848 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.3392874243 |
|
|
Mar 10 02:37:30 PM PDT 24 |
Mar 10 02:40:06 PM PDT 24 |
168985184 ps |
| T849 |
/workspace/coverage/default/35.sram_ctrl_regwen.39333560 |
|
|
Mar 10 02:39:28 PM PDT 24 |
Mar 10 03:08:50 PM PDT 24 |
71214865952 ps |
| T850 |
/workspace/coverage/default/15.sram_ctrl_bijection.473977225 |
|
|
Mar 10 02:36:34 PM PDT 24 |
Mar 10 02:37:04 PM PDT 24 |
2675595033 ps |
| T851 |
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2519162855 |
|
|
Mar 10 02:35:26 PM PDT 24 |
Mar 10 02:41:42 PM PDT 24 |
22698917776 ps |
| T852 |
/workspace/coverage/default/4.sram_ctrl_mem_walk.3324465392 |
|
|
Mar 10 02:35:16 PM PDT 24 |
Mar 10 02:35:25 PM PDT 24 |
873967593 ps |
| T853 |
/workspace/coverage/default/17.sram_ctrl_stress_all.3776826702 |
|
|
Mar 10 02:36:54 PM PDT 24 |
Mar 10 03:24:09 PM PDT 24 |
29549732192 ps |
| T854 |
/workspace/coverage/default/45.sram_ctrl_lc_escalation.2549133186 |
|
|
Mar 10 02:40:59 PM PDT 24 |
Mar 10 02:41:18 PM PDT 24 |
1728469565 ps |
| T855 |
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.2613210907 |
|
|
Mar 10 02:41:03 PM PDT 24 |
Mar 10 02:41:07 PM PDT 24 |
123830091 ps |
| T856 |
/workspace/coverage/default/28.sram_ctrl_regwen.6040370 |
|
|
Mar 10 02:38:28 PM PDT 24 |
Mar 10 03:04:28 PM PDT 24 |
27382824532 ps |
| T857 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.3545098508 |
|
|
Mar 10 02:36:34 PM PDT 24 |
Mar 10 03:02:08 PM PDT 24 |
19356755367 ps |
| T858 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.12751470 |
|
|
Mar 10 02:35:44 PM PDT 24 |
Mar 10 02:37:50 PM PDT 24 |
122325646 ps |
| T859 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.3449962267 |
|
|
Mar 10 02:35:05 PM PDT 24 |
Mar 10 02:35:09 PM PDT 24 |
598492295 ps |
| T860 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.578228499 |
|
|
Mar 10 02:37:25 PM PDT 24 |
Mar 10 02:37:26 PM PDT 24 |
42036580 ps |
| T861 |
/workspace/coverage/default/29.sram_ctrl_access_during_key_req.4233831304 |
|
|
Mar 10 02:38:44 PM PDT 24 |
Mar 10 02:58:27 PM PDT 24 |
17872659111 ps |
| T862 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.517444463 |
|
|
Mar 10 02:38:16 PM PDT 24 |
Mar 10 02:43:51 PM PDT 24 |
7096560168 ps |
| T863 |
/workspace/coverage/default/23.sram_ctrl_stress_pipeline.2227436390 |
|
|
Mar 10 02:37:39 PM PDT 24 |
Mar 10 02:42:13 PM PDT 24 |
5316061575 ps |
| T864 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.700967701 |
|
|
Mar 10 02:36:53 PM PDT 24 |
Mar 10 02:36:59 PM PDT 24 |
676666890 ps |
| T865 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.248971683 |
|
|
Mar 10 02:35:16 PM PDT 24 |
Mar 10 02:48:08 PM PDT 24 |
9269843051 ps |
| T866 |
/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.1090539487 |
|
|
Mar 10 02:35:18 PM PDT 24 |
Mar 10 02:35:26 PM PDT 24 |
236399512 ps |
| T867 |
/workspace/coverage/default/6.sram_ctrl_multiple_keys.993987889 |
|
|
Mar 10 02:35:26 PM PDT 24 |
Mar 10 02:40:27 PM PDT 24 |
81961199838 ps |
| T868 |
/workspace/coverage/default/16.sram_ctrl_bijection.3414722761 |
|
|
Mar 10 02:36:39 PM PDT 24 |
Mar 10 02:37:44 PM PDT 24 |
16205126992 ps |
| T869 |
/workspace/coverage/default/26.sram_ctrl_smoke.2258740315 |
|
|
Mar 10 02:38:15 PM PDT 24 |
Mar 10 02:38:26 PM PDT 24 |
749579152 ps |
| T870 |
/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.735063284 |
|
|
Mar 10 02:39:51 PM PDT 24 |
Mar 10 02:49:32 PM PDT 24 |
53905175404 ps |
| T871 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.3123125493 |
|
|
Mar 10 02:37:34 PM PDT 24 |
Mar 10 02:37:45 PM PDT 24 |
675147422 ps |
| T872 |
/workspace/coverage/default/27.sram_ctrl_ram_cfg.4177835450 |
|
|
Mar 10 02:38:24 PM PDT 24 |
Mar 10 02:38:25 PM PDT 24 |
43196690 ps |
| T873 |
/workspace/coverage/default/46.sram_ctrl_lc_escalation.3911596270 |
|
|
Mar 10 02:41:14 PM PDT 24 |
Mar 10 02:41:27 PM PDT 24 |
787232141 ps |
| T874 |
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.861129871 |
|
|
Mar 10 02:36:37 PM PDT 24 |
Mar 10 02:36:48 PM PDT 24 |
429192222 ps |
| T875 |
/workspace/coverage/default/7.sram_ctrl_regwen.1261497647 |
|
|
Mar 10 02:35:35 PM PDT 24 |
Mar 10 02:51:57 PM PDT 24 |
60845139111 ps |
| T876 |
/workspace/coverage/default/31.sram_ctrl_bijection.1330855387 |
|
|
Mar 10 02:38:52 PM PDT 24 |
Mar 10 02:39:38 PM PDT 24 |
8448550541 ps |
| T877 |
/workspace/coverage/default/28.sram_ctrl_multiple_keys.764897563 |
|
|
Mar 10 02:38:27 PM PDT 24 |
Mar 10 02:51:36 PM PDT 24 |
3174173140 ps |
| T878 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.2477137418 |
|
|
Mar 10 02:39:32 PM PDT 24 |
Mar 10 02:44:17 PM PDT 24 |
6267753282 ps |
| T879 |
/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.1025614169 |
|
|
Mar 10 02:37:41 PM PDT 24 |
Mar 10 02:37:49 PM PDT 24 |
835908789 ps |
| T880 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.182212668 |
|
|
Mar 10 02:35:45 PM PDT 24 |
Mar 10 02:35:49 PM PDT 24 |
655058565 ps |
| T881 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.3359443284 |
|
|
Mar 10 02:38:40 PM PDT 24 |
Mar 10 02:40:00 PM PDT 24 |
466378260 ps |
| T882 |
/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.376487967 |
|
|
Mar 10 02:38:30 PM PDT 24 |
Mar 10 02:38:43 PM PDT 24 |
418534045 ps |
| T883 |
/workspace/coverage/default/38.sram_ctrl_partial_access.204132985 |
|
|
Mar 10 02:39:55 PM PDT 24 |
Mar 10 02:42:17 PM PDT 24 |
670112090 ps |
| T884 |
/workspace/coverage/default/25.sram_ctrl_bijection.1145585309 |
|
|
Mar 10 02:38:14 PM PDT 24 |
Mar 10 02:38:39 PM PDT 24 |
409720862 ps |
| T885 |
/workspace/coverage/default/20.sram_ctrl_access_during_key_req.1897181888 |
|
|
Mar 10 02:37:19 PM PDT 24 |
Mar 10 02:42:12 PM PDT 24 |
7013302753 ps |
| T886 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.377545400 |
|
|
Mar 10 02:34:51 PM PDT 24 |
Mar 10 02:35:33 PM PDT 24 |
456451569 ps |
| T887 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.1661534569 |
|
|
Mar 10 02:36:59 PM PDT 24 |
Mar 10 02:37:09 PM PDT 24 |
1361505552 ps |
| T888 |
/workspace/coverage/default/23.sram_ctrl_stress_all.2601612472 |
|
|
Mar 10 02:38:11 PM PDT 24 |
Mar 10 03:25:42 PM PDT 24 |
10495612294 ps |
| T889 |
/workspace/coverage/default/36.sram_ctrl_bijection.2344153532 |
|
|
Mar 10 02:39:34 PM PDT 24 |
Mar 10 02:40:39 PM PDT 24 |
7670021390 ps |
| T890 |
/workspace/coverage/default/36.sram_ctrl_access_during_key_req.557655604 |
|
|
Mar 10 02:39:39 PM PDT 24 |
Mar 10 02:49:34 PM PDT 24 |
1699730954 ps |
| T891 |
/workspace/coverage/default/42.sram_ctrl_mem_walk.3438158307 |
|
|
Mar 10 02:40:38 PM PDT 24 |
Mar 10 02:40:46 PM PDT 24 |
262747781 ps |
| T892 |
/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.1942898481 |
|
|
Mar 10 02:38:51 PM PDT 24 |
Mar 10 02:45:07 PM PDT 24 |
6309549278 ps |
| T893 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.267240836 |
|
|
Mar 10 02:38:21 PM PDT 24 |
Mar 10 02:48:17 PM PDT 24 |
7062604346 ps |
| T894 |
/workspace/coverage/default/32.sram_ctrl_smoke.2679443153 |
|
|
Mar 10 02:39:00 PM PDT 24 |
Mar 10 02:39:10 PM PDT 24 |
861209794 ps |
| T895 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.3382473425 |
|
|
Mar 10 02:40:59 PM PDT 24 |
Mar 10 03:02:50 PM PDT 24 |
3921328245 ps |
| T896 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.2524540527 |
|
|
Mar 10 02:38:47 PM PDT 24 |
Mar 10 03:08:26 PM PDT 24 |
10991438309 ps |
| T897 |
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3312768823 |
|
|
Mar 10 02:41:20 PM PDT 24 |
Mar 10 02:48:21 PM PDT 24 |
17238408475 ps |
| T898 |
/workspace/coverage/default/36.sram_ctrl_partial_access.789218493 |
|
|
Mar 10 02:39:34 PM PDT 24 |
Mar 10 02:40:20 PM PDT 24 |
1923349064 ps |
| T899 |
/workspace/coverage/default/45.sram_ctrl_partial_access.3453013504 |
|
|
Mar 10 02:40:59 PM PDT 24 |
Mar 10 02:41:16 PM PDT 24 |
1740304690 ps |
| T900 |
/workspace/coverage/default/34.sram_ctrl_mem_partial_access.3227515216 |
|
|
Mar 10 02:39:23 PM PDT 24 |
Mar 10 02:39:26 PM PDT 24 |
1118313129 ps |
| T901 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3318851797 |
|
|
Mar 10 02:41:29 PM PDT 24 |
Mar 10 02:46:28 PM PDT 24 |
6973043471 ps |
| T902 |
/workspace/coverage/default/48.sram_ctrl_mem_walk.1336290508 |
|
|
Mar 10 02:41:35 PM PDT 24 |
Mar 10 02:41:45 PM PDT 24 |
2290056081 ps |
| T903 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.3473036767 |
|
|
Mar 10 02:37:00 PM PDT 24 |
Mar 10 02:39:42 PM PDT 24 |
1747467459 ps |
| T904 |
/workspace/coverage/default/22.sram_ctrl_alert_test.4029044676 |
|
|
Mar 10 02:37:40 PM PDT 24 |
Mar 10 02:37:42 PM PDT 24 |
23904906 ps |
| T905 |
/workspace/coverage/default/1.sram_ctrl_smoke.1088571493 |
|
|
Mar 10 02:34:47 PM PDT 24 |
Mar 10 02:35:05 PM PDT 24 |
896742823 ps |
| T906 |
/workspace/coverage/default/10.sram_ctrl_multiple_keys.1037730330 |
|
|
Mar 10 02:35:51 PM PDT 24 |
Mar 10 02:49:28 PM PDT 24 |
36166860728 ps |
| T907 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.2729724591 |
|
|
Mar 10 02:37:36 PM PDT 24 |
Mar 10 02:42:21 PM PDT 24 |
61864643043 ps |
| T908 |
/workspace/coverage/default/16.sram_ctrl_regwen.1694565534 |
|
|
Mar 10 02:36:47 PM PDT 24 |
Mar 10 02:58:57 PM PDT 24 |
53565331526 ps |
| T909 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.3413613650 |
|
|
Mar 10 02:35:55 PM PDT 24 |
Mar 10 02:37:47 PM PDT 24 |
501782235 ps |
| T910 |
/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2205636032 |
|
|
Mar 10 02:36:41 PM PDT 24 |
Mar 10 02:37:03 PM PDT 24 |
519953080 ps |
| T911 |
/workspace/coverage/default/27.sram_ctrl_bijection.1612012668 |
|
|
Mar 10 02:38:20 PM PDT 24 |
Mar 10 02:39:01 PM PDT 24 |
26988963050 ps |
| T912 |
/workspace/coverage/default/14.sram_ctrl_executable.277273290 |
|
|
Mar 10 02:36:28 PM PDT 24 |
Mar 10 02:40:51 PM PDT 24 |
7464678714 ps |
| T913 |
/workspace/coverage/default/43.sram_ctrl_partial_access.3825709764 |
|
|
Mar 10 02:40:43 PM PDT 24 |
Mar 10 02:41:05 PM PDT 24 |
2748058273 ps |
| T914 |
/workspace/coverage/default/28.sram_ctrl_bijection.815494730 |
|
|
Mar 10 02:38:22 PM PDT 24 |
Mar 10 02:39:18 PM PDT 24 |
4483973007 ps |
| T915 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.642839793 |
|
|
Mar 10 02:39:52 PM PDT 24 |
Mar 10 02:40:10 PM PDT 24 |
795080483 ps |
| T916 |
/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.3961866506 |
|
|
Mar 10 02:35:01 PM PDT 24 |
Mar 10 02:36:18 PM PDT 24 |
469996720 ps |
| T917 |
/workspace/coverage/default/42.sram_ctrl_executable.3202199401 |
|
|
Mar 10 02:40:36 PM PDT 24 |
Mar 10 02:59:06 PM PDT 24 |
19147748827 ps |
| T92 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3910208280 |
|
|
Mar 10 01:18:49 PM PDT 24 |
Mar 10 01:18:51 PM PDT 24 |
800342493 ps |
| T103 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2146407989 |
|
|
Mar 10 01:18:53 PM PDT 24 |
Mar 10 01:18:56 PM PDT 24 |
576803587 ps |
| T62 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2662742233 |
|
|
Mar 10 01:19:02 PM PDT 24 |
Mar 10 01:19:03 PM PDT 24 |
31493066 ps |
| T93 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2184786491 |
|
|
Mar 10 01:19:02 PM PDT 24 |
Mar 10 01:19:03 PM PDT 24 |
36682708 ps |
| T63 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2302994318 |
|
|
Mar 10 01:18:48 PM PDT 24 |
Mar 10 01:18:49 PM PDT 24 |
91246686 ps |
| T918 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.91816305 |
|
|
Mar 10 01:19:00 PM PDT 24 |
Mar 10 01:19:02 PM PDT 24 |
243258957 ps |
| T919 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2166126894 |
|
|
Mar 10 01:18:51 PM PDT 24 |
Mar 10 01:18:53 PM PDT 24 |
112385718 ps |
| T920 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2775429305 |
|
|
Mar 10 01:18:58 PM PDT 24 |
Mar 10 01:19:00 PM PDT 24 |
67226239 ps |
| T921 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3286155922 |
|
|
Mar 10 01:18:48 PM PDT 24 |
Mar 10 01:18:50 PM PDT 24 |
130323506 ps |
| T922 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.4082448686 |
|
|
Mar 10 01:19:09 PM PDT 24 |
Mar 10 01:19:10 PM PDT 24 |
136608523 ps |
| T923 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.567438595 |
|
|
Mar 10 01:18:54 PM PDT 24 |
Mar 10 01:18:55 PM PDT 24 |
35426255 ps |
| T64 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3538684472 |
|
|
Mar 10 01:19:01 PM PDT 24 |
Mar 10 01:19:05 PM PDT 24 |
326681134 ps |
| T94 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2856077177 |
|
|
Mar 10 01:18:57 PM PDT 24 |
Mar 10 01:18:58 PM PDT 24 |
83053742 ps |
| T924 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3683652812 |
|
|
Mar 10 01:18:58 PM PDT 24 |
Mar 10 01:19:01 PM PDT 24 |
131210454 ps |
| T65 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1942284104 |
|
|
Mar 10 01:19:09 PM PDT 24 |
Mar 10 01:19:11 PM PDT 24 |
400300738 ps |
| T66 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2059188009 |
|
|
Mar 10 01:19:05 PM PDT 24 |
Mar 10 01:19:08 PM PDT 24 |
496102751 ps |
| T925 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.4140698988 |
|
|
Mar 10 01:18:45 PM PDT 24 |
Mar 10 01:18:46 PM PDT 24 |
119074469 ps |
| T67 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1028901288 |
|
|
Mar 10 01:18:38 PM PDT 24 |
Mar 10 01:18:39 PM PDT 24 |
20484178 ps |
| T926 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1368923434 |
|
|
Mar 10 01:19:04 PM PDT 24 |
Mar 10 01:19:05 PM PDT 24 |
41851142 ps |
| T104 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1364438627 |
|
|
Mar 10 01:19:03 PM PDT 24 |
Mar 10 01:19:04 PM PDT 24 |
455468125 ps |
| T105 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.935731847 |
|
|
Mar 10 01:18:45 PM PDT 24 |
Mar 10 01:18:47 PM PDT 24 |
230388119 ps |
| T95 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2945788475 |
|
|
Mar 10 01:18:44 PM PDT 24 |
Mar 10 01:18:48 PM PDT 24 |
1729015116 ps |
| T927 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2020598418 |
|
|
Mar 10 01:18:49 PM PDT 24 |
Mar 10 01:18:54 PM PDT 24 |
121607558 ps |
| T928 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.75375823 |
|
|
Mar 10 01:19:03 PM PDT 24 |
Mar 10 01:19:06 PM PDT 24 |
338455503 ps |
| T929 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1463907409 |
|
|
Mar 10 01:18:58 PM PDT 24 |
Mar 10 01:18:59 PM PDT 24 |
16733004 ps |
| T930 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.4121215905 |
|
|
Mar 10 01:19:00 PM PDT 24 |
Mar 10 01:19:01 PM PDT 24 |
52818892 ps |
| T123 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2224558076 |
|
|
Mar 10 01:18:52 PM PDT 24 |
Mar 10 01:18:54 PM PDT 24 |
673726197 ps |
| T931 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3331056338 |
|
|
Mar 10 01:19:01 PM PDT 24 |
Mar 10 01:19:03 PM PDT 24 |
108775072 ps |
| T68 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.311405245 |
|
|
Mar 10 01:18:57 PM PDT 24 |
Mar 10 01:19:00 PM PDT 24 |
1696418443 ps |
| T932 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1841616070 |
|
|
Mar 10 01:19:01 PM PDT 24 |
Mar 10 01:19:02 PM PDT 24 |
170600673 ps |
| T933 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2839528164 |
|
|
Mar 10 01:19:09 PM PDT 24 |
Mar 10 01:19:10 PM PDT 24 |
102447264 ps |
| T69 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2155480382 |
|
|
Mar 10 01:18:56 PM PDT 24 |
Mar 10 01:18:57 PM PDT 24 |
13788132 ps |
| T934 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3539405934 |
|
|
Mar 10 01:18:49 PM PDT 24 |
Mar 10 01:18:51 PM PDT 24 |
34638528 ps |
| T935 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3910994282 |
|
|
Mar 10 01:18:38 PM PDT 24 |
Mar 10 01:18:40 PM PDT 24 |
60230223 ps |
| T70 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2341207110 |
|
|
Mar 10 01:18:50 PM PDT 24 |
Mar 10 01:18:54 PM PDT 24 |
437426875 ps |
| T71 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.4061966045 |
|
|
Mar 10 01:18:50 PM PDT 24 |
Mar 10 01:18:52 PM PDT 24 |
163546566 ps |
| T73 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1711910749 |
|
|
Mar 10 01:18:51 PM PDT 24 |
Mar 10 01:18:54 PM PDT 24 |
1557866880 ps |
| T124 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2648370157 |
|
|
Mar 10 01:19:04 PM PDT 24 |
Mar 10 01:19:05 PM PDT 24 |
120682790 ps |
| T74 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3908745441 |
|
|
Mar 10 01:19:01 PM PDT 24 |
Mar 10 01:19:04 PM PDT 24 |
947262082 ps |
| T936 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3965623808 |
|
|
Mar 10 01:18:59 PM PDT 24 |
Mar 10 01:19:01 PM PDT 24 |
1659375669 ps |
| T937 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3251753974 |
|
|
Mar 10 01:18:39 PM PDT 24 |
Mar 10 01:18:41 PM PDT 24 |
34038759 ps |
| T131 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.81277835 |
|
|
Mar 10 01:18:52 PM PDT 24 |
Mar 10 01:18:53 PM PDT 24 |
92728883 ps |
| T75 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3022509362 |
|
|
Mar 10 01:19:01 PM PDT 24 |
Mar 10 01:19:06 PM PDT 24 |
6357216368 ps |
| T938 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.305693837 |
|
|
Mar 10 01:18:56 PM PDT 24 |
Mar 10 01:18:57 PM PDT 24 |
22550665 ps |
| T939 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1438357783 |
|
|
Mar 10 01:18:42 PM PDT 24 |
Mar 10 01:18:43 PM PDT 24 |
41479067 ps |
| T127 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1777037091 |
|
|
Mar 10 01:18:50 PM PDT 24 |
Mar 10 01:18:52 PM PDT 24 |
2097278843 ps |
| T940 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.745144290 |
|
|
Mar 10 01:18:52 PM PDT 24 |
Mar 10 01:18:53 PM PDT 24 |
12573838 ps |
| T941 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.179069014 |
|
|
Mar 10 01:18:53 PM PDT 24 |
Mar 10 01:18:55 PM PDT 24 |
76234274 ps |
| T76 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.4167410179 |
|
|
Mar 10 01:18:57 PM PDT 24 |
Mar 10 01:19:01 PM PDT 24 |
3373703837 ps |
| T942 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1589400889 |
|
|
Mar 10 01:19:01 PM PDT 24 |
Mar 10 01:19:03 PM PDT 24 |
83828297 ps |
| T943 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2442920561 |
|
|
Mar 10 01:18:37 PM PDT 24 |
Mar 10 01:18:38 PM PDT 24 |
15312022 ps |
| T944 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3580489881 |
|
|
Mar 10 01:19:01 PM PDT 24 |
Mar 10 01:19:05 PM PDT 24 |
38987160 ps |
| T945 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.577646484 |
|
|
Mar 10 01:18:56 PM PDT 24 |
Mar 10 01:18:58 PM PDT 24 |
43761176 ps |
| T946 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1142927513 |
|
|
Mar 10 01:19:03 PM PDT 24 |
Mar 10 01:19:04 PM PDT 24 |
128074502 ps |
| T947 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1016128399 |
|
|
Mar 10 01:19:05 PM PDT 24 |
Mar 10 01:19:08 PM PDT 24 |
36181137 ps |
| T948 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.158521886 |
|
|
Mar 10 01:18:43 PM PDT 24 |
Mar 10 01:18:44 PM PDT 24 |
16272078 ps |
| T949 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2083453187 |
|
|
Mar 10 01:18:44 PM PDT 24 |
Mar 10 01:18:45 PM PDT 24 |
20918269 ps |
| T128 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3702800699 |
|
|
Mar 10 01:18:37 PM PDT 24 |
Mar 10 01:18:39 PM PDT 24 |
243832770 ps |
| T950 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2992765591 |
|
|
Mar 10 01:18:54 PM PDT 24 |
Mar 10 01:18:55 PM PDT 24 |
16167570 ps |
| T951 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.559279254 |
|
|
Mar 10 01:19:03 PM PDT 24 |
Mar 10 01:19:04 PM PDT 24 |
111755193 ps |
| T952 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1544680297 |
|
|
Mar 10 01:18:41 PM PDT 24 |
Mar 10 01:18:43 PM PDT 24 |
38142845 ps |
| T953 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.215172162 |
|
|
Mar 10 01:19:04 PM PDT 24 |
Mar 10 01:19:05 PM PDT 24 |
14829757 ps |
| T77 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1133862603 |
|
|
Mar 10 01:18:59 PM PDT 24 |
Mar 10 01:19:03 PM PDT 24 |
1421981077 ps |
| T954 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.239075382 |
|
|
Mar 10 01:18:43 PM PDT 24 |
Mar 10 01:18:45 PM PDT 24 |
101920733 ps |
| T955 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2145280091 |
|
|
Mar 10 01:18:38 PM PDT 24 |
Mar 10 01:18:39 PM PDT 24 |
119872464 ps |
| T956 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3166890851 |
|
|
Mar 10 01:18:59 PM PDT 24 |
Mar 10 01:19:01 PM PDT 24 |
176646807 ps |
| T957 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1037274399 |
|
|
Mar 10 01:18:42 PM PDT 24 |
Mar 10 01:18:43 PM PDT 24 |
38692330 ps |
| T78 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3803310331 |
|
|
Mar 10 01:18:55 PM PDT 24 |
Mar 10 01:18:56 PM PDT 24 |
19053691 ps |
| T130 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.4061853675 |
|
|
Mar 10 01:19:07 PM PDT 24 |
Mar 10 01:19:10 PM PDT 24 |
408483154 ps |
| T958 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3919108552 |
|
|
Mar 10 01:18:56 PM PDT 24 |
Mar 10 01:18:59 PM PDT 24 |
98383875 ps |
| T959 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.902728414 |
|
|
Mar 10 01:18:43 PM PDT 24 |
Mar 10 01:18:49 PM PDT 24 |
596061925 ps |
| T960 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3230604932 |
|
|
Mar 10 01:18:38 PM PDT 24 |
Mar 10 01:18:38 PM PDT 24 |
12725236 ps |
| T961 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3297656003 |
|
|
Mar 10 01:18:38 PM PDT 24 |
Mar 10 01:18:40 PM PDT 24 |
77365061 ps |
| T129 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3475473968 |
|
|
Mar 10 01:18:59 PM PDT 24 |
Mar 10 01:19:01 PM PDT 24 |
584187393 ps |
| T89 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.794363805 |
|
|
Mar 10 01:18:52 PM PDT 24 |
Mar 10 01:18:55 PM PDT 24 |
803231126 ps |
| T962 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.367544590 |
|
|
Mar 10 01:18:43 PM PDT 24 |
Mar 10 01:18:45 PM PDT 24 |
102248747 ps |
| T963 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.83954613 |
|
|
Mar 10 01:18:40 PM PDT 24 |
Mar 10 01:18:42 PM PDT 24 |
854343064 ps |
| T964 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1848100254 |
|
|
Mar 10 01:18:46 PM PDT 24 |
Mar 10 01:18:50 PM PDT 24 |
363120145 ps |
| T86 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2822911772 |
|
|
Mar 10 01:18:44 PM PDT 24 |
Mar 10 01:18:48 PM PDT 24 |
578893550 ps |
| T965 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3509512996 |
|
|
Mar 10 01:18:58 PM PDT 24 |
Mar 10 01:19:00 PM PDT 24 |
59627982 ps |
| T966 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3931682099 |
|
|
Mar 10 01:18:48 PM PDT 24 |
Mar 10 01:18:50 PM PDT 24 |
19662856 ps |
| T87 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2278202938 |
|
|
Mar 10 01:18:58 PM PDT 24 |
Mar 10 01:19:01 PM PDT 24 |
320044169 ps |
| T967 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.235572751 |
|
|
Mar 10 01:18:57 PM PDT 24 |
Mar 10 01:18:58 PM PDT 24 |
47967738 ps |
| T968 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.630416876 |
|
|
Mar 10 01:18:37 PM PDT 24 |
Mar 10 01:18:40 PM PDT 24 |
382356381 ps |
| T969 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1366800015 |
|
|
Mar 10 01:18:43 PM PDT 24 |
Mar 10 01:18:45 PM PDT 24 |
73005278 ps |
| T970 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.359279285 |
|
|
Mar 10 01:18:43 PM PDT 24 |
Mar 10 01:18:45 PM PDT 24 |
43375272 ps |
| T971 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1511185589 |
|
|
Mar 10 01:18:58 PM PDT 24 |
Mar 10 01:18:59 PM PDT 24 |
26343587 ps |
| T972 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2971734036 |
|
|
Mar 10 01:19:12 PM PDT 24 |
Mar 10 01:19:12 PM PDT 24 |
10602107 ps |
| T973 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3245929132 |
|
|
Mar 10 01:19:02 PM PDT 24 |
Mar 10 01:19:05 PM PDT 24 |
785044201 ps |
| T974 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.537723175 |
|
|
Mar 10 01:18:57 PM PDT 24 |
Mar 10 01:19:01 PM PDT 24 |
79148226 ps |
| T125 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.332515508 |
|
|
Mar 10 01:18:44 PM PDT 24 |
Mar 10 01:18:47 PM PDT 24 |
524496795 ps |
| T88 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.428437625 |
|
|
Mar 10 01:18:43 PM PDT 24 |
Mar 10 01:18:46 PM PDT 24 |
148529100 ps |
| T975 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1012104848 |
|
|
Mar 10 01:19:05 PM PDT 24 |
Mar 10 01:19:08 PM PDT 24 |
107820174 ps |
| T976 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3868283811 |
|
|
Mar 10 01:18:59 PM PDT 24 |
Mar 10 01:19:00 PM PDT 24 |
13253341 ps |
| T126 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3525850717 |
|
|
Mar 10 01:18:58 PM PDT 24 |
Mar 10 01:19:00 PM PDT 24 |
156053255 ps |
| T977 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3985375084 |
|
|
Mar 10 01:18:54 PM PDT 24 |
Mar 10 01:18:57 PM PDT 24 |
71576022 ps |
| T978 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3897449590 |
|
|
Mar 10 01:18:49 PM PDT 24 |
Mar 10 01:18:50 PM PDT 24 |
17761726 ps |
| T979 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.4274943109 |
|
|
Mar 10 01:18:44 PM PDT 24 |
Mar 10 01:18:45 PM PDT 24 |
30610419 ps |
| T980 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1827670830 |
|
|
Mar 10 01:18:55 PM PDT 24 |
Mar 10 01:18:56 PM PDT 24 |
39734603 ps |
| T981 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2987873851 |
|
|
Mar 10 01:18:43 PM PDT 24 |
Mar 10 01:18:44 PM PDT 24 |
43813421 ps |
| T982 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.209053184 |
|
|
Mar 10 01:19:02 PM PDT 24 |
Mar 10 01:19:04 PM PDT 24 |
19103376 ps |
| T983 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1391715370 |
|
|
Mar 10 01:18:58 PM PDT 24 |
Mar 10 01:18:59 PM PDT 24 |
44557820 ps |
| T984 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2345388675 |
|
|
Mar 10 01:18:58 PM PDT 24 |
Mar 10 01:18:59 PM PDT 24 |
31357394 ps |
| T985 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1087783477 |
|
|
Mar 10 01:18:37 PM PDT 24 |
Mar 10 01:18:39 PM PDT 24 |
433390442 ps |
| T986 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3990307208 |
|
|
Mar 10 01:18:45 PM PDT 24 |
Mar 10 01:18:46 PM PDT 24 |
25699800 ps |
| T987 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1475578913 |
|
|
Mar 10 01:18:53 PM PDT 24 |
Mar 10 01:18:55 PM PDT 24 |
62958970 ps |
| T988 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2513680099 |
|
|
Mar 10 01:19:03 PM PDT 24 |
Mar 10 01:19:05 PM PDT 24 |
237476083 ps |
| T989 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.97606134 |
|
|
Mar 10 01:18:39 PM PDT 24 |
Mar 10 01:18:43 PM PDT 24 |
1162828323 ps |
| T990 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3939718382 |
|
|
Mar 10 01:19:04 PM PDT 24 |
Mar 10 01:19:06 PM PDT 24 |
993969164 ps |
| T991 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1813817056 |
|
|
Mar 10 01:19:03 PM PDT 24 |
Mar 10 01:19:04 PM PDT 24 |
246035149 ps |
| T992 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.4113465706 |
|
|
Mar 10 01:18:49 PM PDT 24 |
Mar 10 01:18:50 PM PDT 24 |
18725986 ps |
| T132 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.81389945 |
|
|
Mar 10 01:18:50 PM PDT 24 |
Mar 10 01:18:52 PM PDT 24 |
741545480 ps |
| T133 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3645125497 |
|
|
Mar 10 01:19:00 PM PDT 24 |
Mar 10 01:19:04 PM PDT 24 |
490010859 ps |
| T993 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.162701407 |
|
|
Mar 10 01:18:52 PM PDT 24 |
Mar 10 01:18:54 PM PDT 24 |
495711530 ps |
| T994 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.671818399 |
|
|
Mar 10 01:18:42 PM PDT 24 |
Mar 10 01:18:43 PM PDT 24 |
30913784 ps |
| T995 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3094469163 |
|
|
Mar 10 01:18:57 PM PDT 24 |
Mar 10 01:18:58 PM PDT 24 |
19893247 ps |
| T996 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.20796220 |
|
|
Mar 10 01:18:43 PM PDT 24 |
Mar 10 01:18:47 PM PDT 24 |
422669479 ps |
| T997 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2812548089 |
|
|
Mar 10 01:18:49 PM PDT 24 |
Mar 10 01:18:53 PM PDT 24 |
116357880 ps |
| T998 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2009770241 |
|
|
Mar 10 01:19:08 PM PDT 24 |
Mar 10 01:19:09 PM PDT 24 |
23915360 ps |
| T999 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2668126877 |
|
|
Mar 10 01:18:38 PM PDT 24 |
Mar 10 01:18:39 PM PDT 24 |
56902285 ps |
| T1000 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2068863596 |
|
|
Mar 10 01:18:50 PM PDT 24 |
Mar 10 01:18:51 PM PDT 24 |
36288637 ps |