Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13532960

1

T1

8664

T2

721

T3

5727

full_word

51678311

1

T1

87541

T2

7174

T3

1250

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	65210971	1			T1	96205		T2	7895		T3	6977
auto[TlIntgErrCmd]	92	1			T106	3		T107	3		T108	6
auto[TlIntgErrData]	114	1			T106	6		T107	3		T108	7
auto[TlIntgErrBoth]	94	1			T106	1		T107	4		T108	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29885692

1

T1

36395

T2

3930

T3

3548

auto[1]

35325579

1

T1

59810

T2

3965

T3

3429

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6471619	1			T1	3317		T2	345		T3	2905
auto[TlIntgErrNone]	partial	auto[1]	7061069	1			T1	5347		T2	376		T3	2822
auto[TlIntgErrNone]	full_word	auto[0]	23413943	1			T1	33078		T2	3585		T3	643
auto[TlIntgErrNone]	full_word	auto[1]	28264340	1			T1	54463		T2	3589		T3	607
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T106	1		T107	2		T108	3
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T106	2		T107	1		T108	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T127	1		T128	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T123	2		T129	1		T130	1
auto[TlIntgErrData]	partial	auto[0]	51	1			T106	3		T107	2		T108	1
auto[TlIntgErrData]	partial	auto[1]	48	1			T106	3		T107	1		T108	5
auto[TlIntgErrData]	full_word	auto[0]	7	1			T120	1		T121	1		T131	2
auto[TlIntgErrData]	full_word	auto[1]	8	1			T108	1		T120	1		T122	2
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T106	1		T107	2		T108	2
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T107	2		T108	5		T120	5
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T132	1		T133	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T122	1		T134	1		T126	1