Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	736091	1			T3	1064		T14	19630		T15	9282
auto[1]	9870223	1			T1	327		T2	13		T3	900
auto[2]	597111	1			T3	920		T14	16719		T15	8288
auto[3]	9748177	1			T1	326		T2	24		T3	717

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13956687	1			T1	460		T2	31		T3	46
auto[1]	1967214	1			T1	91		T2	3		T3	478
auto[2]	1955978	1			T1	89		T2	3		T3	448
auto[3]	3071723	1			T1	13		T3	2629		T8	19532

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8091657

1

T1

653

T2

37

T3

3599

auto[1]

12859945

1

T3

2

T8

25652

T10

7

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	244256	1			T3	20		T15	7702		T63	1737
auto[0]	auto[0]	auto[1]	25232	1			T3	178		T15	764		T63	162
auto[0]	auto[0]	auto[2]	25187	1			T3	149		T15	730		T63	179
auto[0]	auto[0]	auto[3]	7993	1			T3	716		T15	80		T63	12
auto[0]	auto[1]	auto[0]	3072126	1			T1	239		T2	11		T3	4
auto[0]	auto[1]	auto[1]	324890	1			T1	67		T2	1		T3	154
auto[0]	auto[1]	auto[2]	310703	1			T1	14		T2	1		T3	24
auto[0]	auto[1]	auto[3]	76347	1			T1	7		T3	718		T10	50
auto[0]	auto[2]	auto[0]	209112	1			T3	22		T15	7000		T63	1503
auto[0]	auto[2]	auto[1]	21852	1			T3	138		T15	728		T63	173
auto[0]	auto[2]	auto[2]	19714	1			T3	144		T15	512		T63	114
auto[0]	auto[2]	auto[3]	6449	1			T3	616		T15	42		T63	8
auto[0]	auto[3]	auto[0]	3038183	1			T1	221		T2	20		T10	4037
auto[0]	auto[3]	auto[1]	307396	1			T1	24		T2	2		T3	7
auto[0]	auto[3]	auto[2]	322902	1			T1	75		T2	2		T3	131
auto[0]	auto[3]	auto[3]	79315	1			T1	6		T3	578		T10	36
auto[1]	auto[0]	auto[0]	14495	1			T14	632		T15	4		T63	2
auto[1]	auto[0]	auto[1]	64865	1			T3	1		T14	3043		T15	1
auto[1]	auto[0]	auto[2]	64794	1			T14	2895		T15	1		T5	1
auto[1]	auto[0]	auto[3]	289269	1			T14	13060		T83	3		T104	16051
auto[1]	auto[1]	auto[0]	3682794	1			T8	171		T10	3		T11	2
auto[1]	auto[1]	auto[1]	610320	1			T8	2167		T11	1		T12	1489
auto[1]	auto[1]	auto[2]	566073	1			T8	732		T11	1		T12	577
auto[1]	auto[1]	auto[3]	1226970	1			T8	9839		T12	6589		T13	499
auto[1]	auto[2]	auto[0]	12524	1			T14	619		T15	4		T63	2
auto[1]	auto[2]	auto[1]	54586	1			T14	2730		T104	3253		T33	2
auto[1]	auto[2]	auto[2]	49771	1			T14	2476		T15	2		T104	2394
auto[1]	auto[2]	auto[3]	223103	1			T14	10894		T104	10635		T141	1
auto[1]	auto[3]	auto[0]	3683197	1			T8	171		T10	4		T11	4
auto[1]	auto[3]	auto[1]	558073	1			T8	724		T12	533		T13	5687
auto[1]	auto[3]	auto[2]	596834	1			T8	2155		T12	1470		T13	5122
auto[1]	auto[3]	auto[3]	1162277	1			T3	1		T8	9693		T12	6619