Unified Coverage Report :: Module :: sram_ctrl_regs_reg_top

Module : sram_ctrl_regs_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl_regs_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg_regs	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.92	100.00	99.58	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.26	100.00	94.62	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_ctrl0_qe	100.00	100.00				100.00
u_ctrl_init	100.00	100.00	100.00			100.00
u_ctrl_regwen	100.00	100.00	100.00			100.00
u_ctrl_renew_scr_key	100.00	100.00	100.00			100.00
u_exec	100.00	100.00	100.00			100.00
u_exec_regwen	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	99.69	100.00	98.75			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_scr_key_rotated	100.00	100.00	100.00			100.00
u_status_bus_integ_error	100.00	100.00	100.00			100.00
u_status_escalated	100.00	100.00	100.00			100.00
u_status_init_done	100.00	100.00	100.00			100.00
u_status_init_error	100.00	100.00	100.00			100.00
u_status_scr_key_seed_valid	100.00	100.00	100.00			100.00
u_status_scr_key_valid	100.00	100.00	100.00			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : sram_ctrl_regs_reg_top

	Line No.	Total	Covered	Percent
TOTAL		63	63	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	364	1	1	100.00
CONT_ASSIGN	434	1	1	100.00
CONT_ASSIGN	461	1	1	100.00
CONT_ASSIGN	489	1	1	100.00
ALWAYS	523	8	8	100.00
CONT_ASSIGN	533	1	1	100.00
ALWAYS	537	1	1	100.00
CONT_ASSIGN	548	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	554	1	1	100.00
CONT_ASSIGN	556	1	1	100.00
CONT_ASSIGN	557	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	560	1	1	100.00
CONT_ASSIGN	562	1	1	100.00
CONT_ASSIGN	564	1	1	100.00
CONT_ASSIGN	565	1	1	100.00
CONT_ASSIGN	567	1	1	100.00
ALWAYS	571	8	8	100.00
ALWAYS	583	15	15	100.00
CONT_ASSIGN	630	0	0
CONT_ASSIGN	638	1	1	100.00
CONT_ASSIGN	639	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl_regs_reg_top.sv' or '../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl_regs_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
77	1	1
89	1	1
90	1	1
118	1	1
119	1	1
152	1	1
166	1	1
364	1	1
434	1	1
461	1	1
489	1	1
523	1	1
524	1	1
525	1	1
526	1	1
527	1	1
528	1	1
529	1	1
530	1	1
533	1	1
537	1	1
548	1	1
550	1	1
551	1	1
553	1	1
554	1	1
556	1	1
557	1	1
559	1	1
560	1	1
562	1	1
564	1	1
565	1	1
567	1	1
571	1	1
572	1	1
573	1	1
574	1	1
575	1	1
576	1	1
577	1	1
578	1	1
583	1	1
584	1	1
586	1	1
590	1	1
591	1	1
592	1	1
593	1	1
594	1	1
595	1	1
599	1	1
603	1	1
607	1	1
611	1	1
612	1	1
616	1	1
630		unreachable
638	1	1
639	1	1

---

Cond Coverage for Module : sram_ctrl_regs_reg_top

	Total	Covered	Percent
Conditions	95	95	100.00
Logical	95	95	100.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T31,T35,T36
1	1	Covered	T1,T2,T3

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T26,T27,T28
1	0	Covered	T106,T107,T108

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T26,T27,T28
0	1	0	Covered	T106,T107,T108
1	0	0	Covered	T26,T27,T28

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T106,T107,T108
0	1	0	Covered	T31,T35,T36
1	0	0	Covered	T31,T35,T36

 LINE       364
 EXPRESSION (exec_we & exec_regwen_qs)
             ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T31,T15
1	1	Covered	T1,T10,T18

 LINE       434
 EXPRESSION (ctrl_we & ctrl_regwen_qs)
             ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T31,T15
1	1	Covered	T1,T2,T3

 LINE       524
 EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_ALERT_TEST_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T18,T31,T60

 LINE       525
 EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_STATUS_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T4,T31

 LINE       526
 EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_EXEC_REGWEN_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T11

 LINE       527
 EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_EXEC_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T10,T18

 LINE       528
 EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_CTRL_REGWEN_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T31

 LINE       529
 EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_CTRL_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       530
 EXPRESSION (reg_addr == sram_ctrl_reg_pkg::SRAM_CTRL_SCR_KEY_ROTATED_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T34,T18,T14

 LINE       533
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       533
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T31

 LINE       537
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T34
1	0	Covered	T1,T2,T3
1	1	Covered	T31,T35,T36

 LINE       537
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))))

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	0	1	Covered	T34,T18,T14
0	0	0	0	0	1	0	Covered	T1,T18,T14
0	0	0	0	1	0	0	Covered	T31,T35,T36
0	0	0	1	0	0	0	Covered	T31,T35,T36
0	0	1	0	0	0	0	Covered	T11,T34,T31
0	1	0	0	0	0	0	Covered	T4,T31,T5
1	0	0	0	0	0	0	Covered	T31,T35,T36

 LINE       537
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T34
1	0	Covered	T18,T31,T60
1	1	Covered	T31,T35,T36

 LINE       537
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T34
1	0	Covered	T14,T4,T31
1	1	Covered	T4,T31,T5

 LINE       537
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T34,T18
1	0	Covered	T1,T2,T18
1	1	Covered	T11,T34,T31

 LINE       537
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T34
1	0	Covered	T1,T10,T18
1	1	Covered	T31,T35,T36

 LINE       537
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T34
1	0	Covered	T1,T2,T31
1	1	Covered	T31,T35,T36

 LINE       537
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T11,T34,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T18,T14

 LINE       537
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T34
1	0	Covered	T18,T31,T64
1	1	Covered	T34,T18,T14

 LINE       548
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T18,T31,T60
1	1	0	Covered	T31,T35,T36
1	1	1	Covered	T22,T25,T23

 LINE       551
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T11
1	1	0	Covered	T31,T35,T36
1	1	1	Covered	T1,T31,T15

 LINE       554
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T31,T35,T36
1	1	1	Covered	T1,T10,T18

 LINE       557
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T18
1	1	0	Covered	T31,T35,T36
1	1	1	Covered	T1,T31,T15

 LINE       560
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T10,T18
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T31,T35,T36
1	1	1	Covered	T1,T2,T3

 LINE       565
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T11,T34,T18
1	1	0	Covered	T31,T35,T36
1	1	1	Covered	T68,T106,T69

---

Branch Coverage for Module : sram_ctrl_regs_reg_top

	Line No.	Total	Covered	Percent
Branches		13	13	100.00
TERNARY	533	2	2	100.00
IF	68	3	3	100.00
CASE	584	8	8	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl_regs_reg_top.sv' or '../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl_regs_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	533	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	68	if ((!rst_ni))
-2-:	70	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T26,T27,T28
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	584	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T3,T7
addr_hit[1]	Covered	T1,T3,T7
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T3,T7
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T3,T7
default	Covered	T1,T3,T7

---

Assert Coverage for Module : sram_ctrl_regs_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	314963327	46070	0	0
reAfterRv	314963327	46070	0	0
rePulse	314963327	18800	0	0
wePulse	314963327	27270	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	314963327	46070	0	0
T1	777388	49	0	0
T2	18403	1	0	0
T3	52281	1	0	0
T7	29498	0	0	0
T8	143472	6	0	0
T9	65761	0	0	0
T10	163770	20	0	0
T11	7984	2	0	0
T12	108876	4	0	0
T13	192050	3	0	0
T16	0	2	0	0
T17	0	2	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	314963327	46070	0	0
T1	777388	49	0	0
T2	18403	1	0	0
T3	52281	1	0	0
T7	29498	0	0	0
T8	143472	6	0	0
T9	65761	0	0	0
T10	163770	20	0	0
T11	7984	2	0	0
T12	108876	4	0	0
T13	192050	3	0	0
T16	0	2	0	0
T17	0	2	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	314963327	18800	0	0
T1	777388	9	0	0
T2	18403	0	0	0
T3	52281	0	0	0
T4	0	49	0	0
T5	0	45	0	0
T6	0	19	0	0
T7	29498	0	0	0
T8	143472	0	0	0
T9	65761	0	0	0
T10	163770	0	0	0
T11	7984	0	0	0
T12	108876	0	0	0
T13	192050	0	0	0
T15	0	24	0	0
T31	0	160	0	0
T32	0	3	0	0
T33	0	121	0	0
T35	0	45	0	0
T65	0	12	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	314963327	27270	0	0
T1	777388	40	0	0
T2	18403	1	0	0
T3	52281	1	0	0
T7	29498	0	0	0
T8	143472	6	0	0
T9	65761	0	0	0
T10	163770	20	0	0
T11	7984	2	0	0
T12	108876	4	0	0
T13	192050	3	0	0
T16	0	2	0	0
T17	0	2	0	0