Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.26	100.00	94.62	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	314963327	143601	0	0
ctrl_regwen_rd_A	314963327	8516	0	0
exec_rd_A	314963327	7879	0	0
exec_regwen_rd_A	314963327	8791	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314963327	143601	0	0
T15	521582	0	0	0
T31	198042	6414	0	0
T32	239191	0	0	0
T35	0	1292	0	0
T36	0	2619	0	0
T38	2331	0	0	0
T39	1854	0	0	0
T53	0	3340	0	0
T54	0	843	0	0
T55	0	4923	0	0
T56	0	3081	0	0
T57	0	5927	0	0
T58	0	1777	0	0
T59	0	2134	0	0
T60	6720	0	0	0
T61	7801	0	0	0
T62	8055	0	0	0
T63	449307	0	0	0
T64	30030	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314963327	8516	0	0
T6	36802	0	0	0
T33	339835	0	0	0
T35	38921	237	0	0
T57	0	543	0	0
T66	172033	0	0	0
T102	259590	0	0	0
T103	172467	0	0	0
T104	161636	0	0	0
T109	0	449	0	0
T110	0	567	0	0
T111	0	360	0	0
T112	0	536	0	0
T113	0	800	0	0
T114	0	855	0	0
T115	0	151	0	0
T116	0	94	0	0
T117	414148	0	0	0
T118	6088	0	0	0
T119	120139	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314963327	7879	0	0
T6	36802	0	0	0
T33	339835	0	0	0
T35	38921	190	0	0
T57	0	403	0	0
T66	172033	0	0	0
T102	259590	0	0	0
T103	172467	0	0	0
T104	161636	0	0	0
T109	0	355	0	0
T110	0	599	0	0
T111	0	323	0	0
T112	0	507	0	0
T113	0	735	0	0
T114	0	736	0	0
T115	0	148	0	0
T116	0	136	0	0
T117	414148	0	0	0
T118	6088	0	0	0
T119	120139	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314963327	8791	0	0
T6	36802	0	0	0
T33	339835	0	0	0
T35	38921	298	0	0
T57	0	690	0	0
T66	172033	0	0	0
T102	259590	0	0	0
T103	172467	0	0	0
T104	161636	0	0	0
T109	0	449	0	0
T110	0	649	0	0
T111	0	362	0	0
T112	0	558	0	0
T113	0	838	0	0
T114	0	712	0	0
T115	0	142	0	0
T116	0	125	0	0
T117	414148	0	0	0
T118	6088	0	0	0
T119	120139	0	0	0