| T795 |
/workspace/coverage/default/2.sram_ctrl_regwen.1943961945 |
|
|
Mar 12 02:59:49 PM PDT 24 |
Mar 12 03:10:41 PM PDT 24 |
43000696504 ps |
| T796 |
/workspace/coverage/default/11.sram_ctrl_executable.3554932475 |
|
|
Mar 12 02:59:50 PM PDT 24 |
Mar 12 03:14:49 PM PDT 24 |
126170219534 ps |
| T797 |
/workspace/coverage/default/36.sram_ctrl_ram_cfg.3708074009 |
|
|
Mar 12 03:02:39 PM PDT 24 |
Mar 12 03:02:40 PM PDT 24 |
33388865 ps |
| T798 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.2966701350 |
|
|
Mar 12 02:59:51 PM PDT 24 |
Mar 12 03:04:09 PM PDT 24 |
2753718300 ps |
| T799 |
/workspace/coverage/default/47.sram_ctrl_stress_all.581029424 |
|
|
Mar 12 03:04:28 PM PDT 24 |
Mar 12 04:18:38 PM PDT 24 |
55890562106 ps |
| T800 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2212938761 |
|
|
Mar 12 03:03:58 PM PDT 24 |
Mar 12 03:05:22 PM PDT 24 |
129777098 ps |
| T801 |
/workspace/coverage/default/35.sram_ctrl_executable.1211476088 |
|
|
Mar 12 03:02:33 PM PDT 24 |
Mar 12 03:25:32 PM PDT 24 |
10412119355 ps |
| T802 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.3100268390 |
|
|
Mar 12 03:05:34 PM PDT 24 |
Mar 12 03:05:35 PM PDT 24 |
26585441 ps |
| T803 |
/workspace/coverage/default/28.sram_ctrl_executable.2176732492 |
|
|
Mar 12 03:01:34 PM PDT 24 |
Mar 12 03:24:31 PM PDT 24 |
12672625366 ps |
| T804 |
/workspace/coverage/default/18.sram_ctrl_access_during_key_req.1485092728 |
|
|
Mar 12 03:00:04 PM PDT 24 |
Mar 12 03:12:06 PM PDT 24 |
16525949836 ps |
| T805 |
/workspace/coverage/default/28.sram_ctrl_stress_pipeline.746753437 |
|
|
Mar 12 03:01:22 PM PDT 24 |
Mar 12 03:06:40 PM PDT 24 |
6927747359 ps |
| T806 |
/workspace/coverage/default/4.sram_ctrl_regwen.1033198694 |
|
|
Mar 12 02:59:29 PM PDT 24 |
Mar 12 03:00:51 PM PDT 24 |
1067572677 ps |
| T807 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.3609354434 |
|
|
Mar 12 03:01:36 PM PDT 24 |
Mar 12 03:03:10 PM PDT 24 |
32421915905 ps |
| T808 |
/workspace/coverage/default/29.sram_ctrl_bijection.2920874545 |
|
|
Mar 12 03:01:31 PM PDT 24 |
Mar 12 03:02:11 PM PDT 24 |
2544016176 ps |
| T809 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1171234095 |
|
|
Mar 12 03:04:12 PM PDT 24 |
Mar 12 03:04:37 PM PDT 24 |
90678218 ps |
| T810 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.1338177538 |
|
|
Mar 12 02:59:49 PM PDT 24 |
Mar 12 03:07:28 PM PDT 24 |
21390585993 ps |
| T811 |
/workspace/coverage/default/14.sram_ctrl_bijection.661616529 |
|
|
Mar 12 02:59:59 PM PDT 24 |
Mar 12 03:01:06 PM PDT 24 |
1085090247 ps |
| T812 |
/workspace/coverage/default/34.sram_ctrl_alert_test.3236396430 |
|
|
Mar 12 03:02:21 PM PDT 24 |
Mar 12 03:02:22 PM PDT 24 |
16249998 ps |
| T813 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.410079369 |
|
|
Mar 12 03:02:54 PM PDT 24 |
Mar 12 03:03:32 PM PDT 24 |
423491391 ps |
| T814 |
/workspace/coverage/default/9.sram_ctrl_partial_access.448886376 |
|
|
Mar 12 02:59:51 PM PDT 24 |
Mar 12 03:00:06 PM PDT 24 |
947130815 ps |
| T815 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.3281561097 |
|
|
Mar 12 03:03:51 PM PDT 24 |
Mar 12 03:06:34 PM PDT 24 |
33501518825 ps |
| T816 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.2955419825 |
|
|
Mar 12 02:59:39 PM PDT 24 |
Mar 12 02:59:44 PM PDT 24 |
681765293 ps |
| T817 |
/workspace/coverage/default/34.sram_ctrl_max_throughput.1255957129 |
|
|
Mar 12 03:02:21 PM PDT 24 |
Mar 12 03:02:52 PM PDT 24 |
168636413 ps |
| T818 |
/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1829762758 |
|
|
Mar 12 02:59:56 PM PDT 24 |
Mar 12 03:00:38 PM PDT 24 |
110792594 ps |
| T819 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.830172455 |
|
|
Mar 12 02:59:49 PM PDT 24 |
Mar 12 03:01:47 PM PDT 24 |
276373568 ps |
| T820 |
/workspace/coverage/default/21.sram_ctrl_bijection.86824468 |
|
|
Mar 12 03:00:28 PM PDT 24 |
Mar 12 03:01:24 PM PDT 24 |
13343200621 ps |
| T821 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.3047150536 |
|
|
Mar 12 02:59:48 PM PDT 24 |
Mar 12 03:15:58 PM PDT 24 |
3312946879 ps |
| T822 |
/workspace/coverage/default/17.sram_ctrl_stress_pipeline.314789403 |
|
|
Mar 12 02:59:59 PM PDT 24 |
Mar 12 03:03:55 PM PDT 24 |
2441962312 ps |
| T823 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.3089200968 |
|
|
Mar 12 03:03:51 PM PDT 24 |
Mar 12 03:17:25 PM PDT 24 |
8753163043 ps |
| T824 |
/workspace/coverage/default/24.sram_ctrl_max_throughput.906866266 |
|
|
Mar 12 03:00:43 PM PDT 24 |
Mar 12 03:00:47 PM PDT 24 |
94677775 ps |
| T825 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.3083510893 |
|
|
Mar 12 03:03:43 PM PDT 24 |
Mar 12 03:03:48 PM PDT 24 |
809521558 ps |
| T826 |
/workspace/coverage/default/4.sram_ctrl_smoke.1072789868 |
|
|
Mar 12 02:59:48 PM PDT 24 |
Mar 12 03:02:22 PM PDT 24 |
918161793 ps |
| T827 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.2856248880 |
|
|
Mar 12 03:03:02 PM PDT 24 |
Mar 12 03:03:07 PM PDT 24 |
595352936 ps |
| T828 |
/workspace/coverage/default/32.sram_ctrl_mem_walk.1046590759 |
|
|
Mar 12 03:02:03 PM PDT 24 |
Mar 12 03:02:11 PM PDT 24 |
680811310 ps |
| T829 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3071726489 |
|
|
Mar 12 02:59:52 PM PDT 24 |
Mar 12 03:06:37 PM PDT 24 |
6273657791 ps |
| T830 |
/workspace/coverage/default/10.sram_ctrl_executable.1174349918 |
|
|
Mar 12 02:59:48 PM PDT 24 |
Mar 12 03:10:54 PM PDT 24 |
9891157443 ps |
| T831 |
/workspace/coverage/default/37.sram_ctrl_regwen.1660870208 |
|
|
Mar 12 03:02:54 PM PDT 24 |
Mar 12 03:23:41 PM PDT 24 |
26155944090 ps |
| T832 |
/workspace/coverage/default/39.sram_ctrl_bijection.2459657778 |
|
|
Mar 12 03:03:02 PM PDT 24 |
Mar 12 03:04:03 PM PDT 24 |
931364267 ps |
| T833 |
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.524120801 |
|
|
Mar 12 03:02:21 PM PDT 24 |
Mar 12 03:05:42 PM PDT 24 |
2175906992 ps |
| T834 |
/workspace/coverage/default/25.sram_ctrl_regwen.1743198493 |
|
|
Mar 12 03:00:49 PM PDT 24 |
Mar 12 03:14:00 PM PDT 24 |
62390282398 ps |
| T835 |
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.491612733 |
|
|
Mar 12 02:59:50 PM PDT 24 |
Mar 12 03:01:13 PM PDT 24 |
479489324 ps |
| T836 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.3432591013 |
|
|
Mar 12 02:59:53 PM PDT 24 |
Mar 12 02:59:58 PM PDT 24 |
1322572414 ps |
| T837 |
/workspace/coverage/default/45.sram_ctrl_partial_access.1910351275 |
|
|
Mar 12 03:03:52 PM PDT 24 |
Mar 12 03:04:16 PM PDT 24 |
288903819 ps |
| T838 |
/workspace/coverage/default/31.sram_ctrl_ram_cfg.2167274545 |
|
|
Mar 12 03:01:55 PM PDT 24 |
Mar 12 03:01:56 PM PDT 24 |
74674002 ps |
| T839 |
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.553244388 |
|
|
Mar 12 02:59:52 PM PDT 24 |
Mar 12 03:06:05 PM PDT 24 |
3874055855 ps |
| T840 |
/workspace/coverage/default/8.sram_ctrl_bijection.1580644423 |
|
|
Mar 12 02:59:35 PM PDT 24 |
Mar 12 03:00:27 PM PDT 24 |
887722896 ps |
| T841 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.2998452532 |
|
|
Mar 12 03:00:18 PM PDT 24 |
Mar 12 03:00:31 PM PDT 24 |
586851893 ps |
| T842 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.667050071 |
|
|
Mar 12 03:00:11 PM PDT 24 |
Mar 12 03:00:26 PM PDT 24 |
946077649 ps |
| T843 |
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.2477851241 |
|
|
Mar 12 03:03:34 PM PDT 24 |
Mar 12 03:05:18 PM PDT 24 |
3390108549 ps |
| T844 |
/workspace/coverage/default/10.sram_ctrl_bijection.1635200615 |
|
|
Mar 12 02:59:52 PM PDT 24 |
Mar 12 03:01:08 PM PDT 24 |
6784043353 ps |
| T845 |
/workspace/coverage/default/18.sram_ctrl_lc_escalation.3601561047 |
|
|
Mar 12 03:00:04 PM PDT 24 |
Mar 12 03:00:11 PM PDT 24 |
443406846 ps |
| T846 |
/workspace/coverage/default/4.sram_ctrl_stress_all.2737393729 |
|
|
Mar 12 02:59:45 PM PDT 24 |
Mar 12 03:43:43 PM PDT 24 |
17821615479 ps |
| T847 |
/workspace/coverage/default/37.sram_ctrl_mem_walk.3386834519 |
|
|
Mar 12 03:02:53 PM PDT 24 |
Mar 12 03:02:59 PM PDT 24 |
602282457 ps |
| T848 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.2839819918 |
|
|
Mar 12 03:04:20 PM PDT 24 |
Mar 12 03:08:35 PM PDT 24 |
37447177983 ps |
| T849 |
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2232744616 |
|
|
Mar 12 02:59:39 PM PDT 24 |
Mar 12 03:05:47 PM PDT 24 |
31920601711 ps |
| T850 |
/workspace/coverage/default/44.sram_ctrl_max_throughput.2028960168 |
|
|
Mar 12 03:03:52 PM PDT 24 |
Mar 12 03:04:39 PM PDT 24 |
130702754 ps |
| T851 |
/workspace/coverage/default/24.sram_ctrl_smoke.2752603916 |
|
|
Mar 12 03:00:40 PM PDT 24 |
Mar 12 03:04:03 PM PDT 24 |
761407616 ps |
| T852 |
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.3536030314 |
|
|
Mar 12 03:00:43 PM PDT 24 |
Mar 12 03:00:44 PM PDT 24 |
70093092 ps |
| T853 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.1223976787 |
|
|
Mar 12 03:00:41 PM PDT 24 |
Mar 12 03:00:44 PM PDT 24 |
100474134 ps |
| T854 |
/workspace/coverage/default/19.sram_ctrl_alert_test.4117745979 |
|
|
Mar 12 03:00:20 PM PDT 24 |
Mar 12 03:00:21 PM PDT 24 |
16522026 ps |
| T855 |
/workspace/coverage/default/29.sram_ctrl_lc_escalation.1404023191 |
|
|
Mar 12 03:01:36 PM PDT 24 |
Mar 12 03:01:38 PM PDT 24 |
556148379 ps |
| T856 |
/workspace/coverage/default/15.sram_ctrl_lc_escalation.775917142 |
|
|
Mar 12 03:00:02 PM PDT 24 |
Mar 12 03:00:06 PM PDT 24 |
281969114 ps |
| T857 |
/workspace/coverage/default/8.sram_ctrl_smoke.3625577364 |
|
|
Mar 12 02:59:41 PM PDT 24 |
Mar 12 03:01:08 PM PDT 24 |
698997024 ps |
| T858 |
/workspace/coverage/default/43.sram_ctrl_alert_test.3363358421 |
|
|
Mar 12 03:03:41 PM PDT 24 |
Mar 12 03:03:43 PM PDT 24 |
42813815 ps |
| T859 |
/workspace/coverage/default/32.sram_ctrl_executable.3749724629 |
|
|
Mar 12 03:02:04 PM PDT 24 |
Mar 12 03:24:46 PM PDT 24 |
13425908136 ps |
| T860 |
/workspace/coverage/default/11.sram_ctrl_smoke.2746330177 |
|
|
Mar 12 02:59:47 PM PDT 24 |
Mar 12 02:59:49 PM PDT 24 |
135054985 ps |
| T861 |
/workspace/coverage/default/27.sram_ctrl_partial_access.2159945567 |
|
|
Mar 12 03:01:14 PM PDT 24 |
Mar 12 03:03:42 PM PDT 24 |
227804808 ps |
| T862 |
/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.3786239734 |
|
|
Mar 12 03:02:12 PM PDT 24 |
Mar 12 03:02:41 PM PDT 24 |
433027811 ps |
| T863 |
/workspace/coverage/default/19.sram_ctrl_partial_access.2607581560 |
|
|
Mar 12 03:00:22 PM PDT 24 |
Mar 12 03:00:44 PM PDT 24 |
1366427881 ps |
| T864 |
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.4223462235 |
|
|
Mar 12 02:59:35 PM PDT 24 |
Mar 12 03:02:39 PM PDT 24 |
901377787 ps |
| T865 |
/workspace/coverage/default/4.sram_ctrl_executable.112790856 |
|
|
Mar 12 02:59:38 PM PDT 24 |
Mar 12 03:03:27 PM PDT 24 |
2992470013 ps |
| T866 |
/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.1283880244 |
|
|
Mar 12 03:02:40 PM PDT 24 |
Mar 12 03:08:08 PM PDT 24 |
3268779630 ps |
| T867 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.3927601582 |
|
|
Mar 12 02:59:56 PM PDT 24 |
Mar 12 02:59:59 PM PDT 24 |
158495028 ps |
| T868 |
/workspace/coverage/default/1.sram_ctrl_smoke.2021663143 |
|
|
Mar 12 02:59:24 PM PDT 24 |
Mar 12 02:59:58 PM PDT 24 |
1456258196 ps |
| T869 |
/workspace/coverage/default/34.sram_ctrl_stress_all.3471170921 |
|
|
Mar 12 03:02:22 PM PDT 24 |
Mar 12 03:56:39 PM PDT 24 |
37305816827 ps |
| T870 |
/workspace/coverage/default/20.sram_ctrl_stress_all.1416055833 |
|
|
Mar 12 03:00:27 PM PDT 24 |
Mar 12 04:22:36 PM PDT 24 |
20511231238 ps |
| T871 |
/workspace/coverage/default/34.sram_ctrl_mem_partial_access.3041140932 |
|
|
Mar 12 03:02:21 PM PDT 24 |
Mar 12 03:02:24 PM PDT 24 |
57816875 ps |
| T872 |
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.2807102951 |
|
|
Mar 12 03:00:29 PM PDT 24 |
Mar 12 03:04:43 PM PDT 24 |
2623449383 ps |
| T873 |
/workspace/coverage/default/0.sram_ctrl_partial_access.2093402176 |
|
|
Mar 12 02:59:14 PM PDT 24 |
Mar 12 02:59:28 PM PDT 24 |
420960972 ps |
| T874 |
/workspace/coverage/default/21.sram_ctrl_executable.2384468620 |
|
|
Mar 12 03:00:43 PM PDT 24 |
Mar 12 03:02:05 PM PDT 24 |
1126600558 ps |
| T875 |
/workspace/coverage/default/10.sram_ctrl_mem_walk.1663945605 |
|
|
Mar 12 02:59:47 PM PDT 24 |
Mar 12 02:59:58 PM PDT 24 |
2632210637 ps |
| T876 |
/workspace/coverage/default/3.sram_ctrl_partial_access.2318793592 |
|
|
Mar 12 02:59:22 PM PDT 24 |
Mar 12 02:59:33 PM PDT 24 |
533923215 ps |
| T877 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.907682281 |
|
|
Mar 12 03:02:54 PM PDT 24 |
Mar 12 03:03:03 PM PDT 24 |
1827249910 ps |
| T878 |
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.321068637 |
|
|
Mar 12 03:03:35 PM PDT 24 |
Mar 12 03:05:56 PM PDT 24 |
2801302162 ps |
| T879 |
/workspace/coverage/default/15.sram_ctrl_smoke.1363462239 |
|
|
Mar 12 02:59:56 PM PDT 24 |
Mar 12 03:01:59 PM PDT 24 |
267937409 ps |
| T880 |
/workspace/coverage/default/10.sram_ctrl_partial_access.4166348099 |
|
|
Mar 12 02:59:42 PM PDT 24 |
Mar 12 02:59:53 PM PDT 24 |
394622895 ps |
| T881 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.1627927086 |
|
|
Mar 12 03:04:35 PM PDT 24 |
Mar 12 03:08:09 PM PDT 24 |
8634270991 ps |
| T882 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.1194735584 |
|
|
Mar 12 02:59:38 PM PDT 24 |
Mar 12 02:59:39 PM PDT 24 |
37465960 ps |
| T883 |
/workspace/coverage/default/11.sram_ctrl_alert_test.111157605 |
|
|
Mar 12 02:59:54 PM PDT 24 |
Mar 12 02:59:55 PM PDT 24 |
18047937 ps |
| T884 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.3038608085 |
|
|
Mar 12 03:00:43 PM PDT 24 |
Mar 12 03:00:47 PM PDT 24 |
244905692 ps |
| T885 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.3989483929 |
|
|
Mar 12 02:59:46 PM PDT 24 |
Mar 12 02:59:47 PM PDT 24 |
62406352 ps |
| T886 |
/workspace/coverage/default/10.sram_ctrl_smoke.1305252265 |
|
|
Mar 12 02:59:42 PM PDT 24 |
Mar 12 02:59:52 PM PDT 24 |
464443670 ps |
| T887 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.296074861 |
|
|
Mar 12 02:59:54 PM PDT 24 |
Mar 12 03:01:51 PM PDT 24 |
263835166 ps |
| T888 |
/workspace/coverage/default/4.sram_ctrl_multiple_keys.1630623319 |
|
|
Mar 12 02:59:40 PM PDT 24 |
Mar 12 03:02:12 PM PDT 24 |
5423610206 ps |
| T889 |
/workspace/coverage/default/37.sram_ctrl_smoke.2417368746 |
|
|
Mar 12 03:02:41 PM PDT 24 |
Mar 12 03:02:54 PM PDT 24 |
1364969612 ps |
| T890 |
/workspace/coverage/default/14.sram_ctrl_smoke.3062729190 |
|
|
Mar 12 02:59:50 PM PDT 24 |
Mar 12 03:00:08 PM PDT 24 |
89367952 ps |
| T891 |
/workspace/coverage/default/48.sram_ctrl_executable.2684393463 |
|
|
Mar 12 03:04:34 PM PDT 24 |
Mar 12 03:16:30 PM PDT 24 |
3271425251 ps |
| T892 |
/workspace/coverage/default/21.sram_ctrl_mem_walk.3650779091 |
|
|
Mar 12 03:00:41 PM PDT 24 |
Mar 12 03:00:46 PM PDT 24 |
350101294 ps |
| T893 |
/workspace/coverage/default/22.sram_ctrl_alert_test.2991115591 |
|
|
Mar 12 03:00:43 PM PDT 24 |
Mar 12 03:00:44 PM PDT 24 |
92572491 ps |
| T894 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.2288914278 |
|
|
Mar 12 02:59:51 PM PDT 24 |
Mar 12 02:59:52 PM PDT 24 |
27036624 ps |
| T895 |
/workspace/coverage/default/20.sram_ctrl_lc_escalation.660835542 |
|
|
Mar 12 03:00:28 PM PDT 24 |
Mar 12 03:00:35 PM PDT 24 |
1583683110 ps |
| T896 |
/workspace/coverage/default/29.sram_ctrl_executable.1210877162 |
|
|
Mar 12 03:01:35 PM PDT 24 |
Mar 12 03:21:13 PM PDT 24 |
6322664500 ps |
| T897 |
/workspace/coverage/default/17.sram_ctrl_access_during_key_req.3971003779 |
|
|
Mar 12 03:00:03 PM PDT 24 |
Mar 12 03:17:43 PM PDT 24 |
15562355670 ps |
| T898 |
/workspace/coverage/default/48.sram_ctrl_lc_escalation.1599840209 |
|
|
Mar 12 03:04:33 PM PDT 24 |
Mar 12 03:04:37 PM PDT 24 |
857386153 ps |
| T899 |
/workspace/coverage/default/36.sram_ctrl_mem_walk.3947967121 |
|
|
Mar 12 03:02:40 PM PDT 24 |
Mar 12 03:02:46 PM PDT 24 |
1324293449 ps |
| T900 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.4009473920 |
|
|
Mar 12 03:02:54 PM PDT 24 |
Mar 12 03:02:57 PM PDT 24 |
164357851 ps |
| T901 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.1715612372 |
|
|
Mar 12 02:59:56 PM PDT 24 |
Mar 12 03:04:54 PM PDT 24 |
12883181493 ps |
| T902 |
/workspace/coverage/default/8.sram_ctrl_multiple_keys.4238116780 |
|
|
Mar 12 02:59:42 PM PDT 24 |
Mar 12 03:21:04 PM PDT 24 |
25760023928 ps |
| T903 |
/workspace/coverage/default/4.sram_ctrl_partial_access.1339555220 |
|
|
Mar 12 02:59:27 PM PDT 24 |
Mar 12 02:59:41 PM PDT 24 |
270278042 ps |
| T904 |
/workspace/coverage/default/37.sram_ctrl_stress_all.3738937859 |
|
|
Mar 12 03:03:04 PM PDT 24 |
Mar 12 03:26:03 PM PDT 24 |
45319660424 ps |
| T905 |
/workspace/coverage/default/20.sram_ctrl_bijection.2741809859 |
|
|
Mar 12 03:00:30 PM PDT 24 |
Mar 12 03:00:48 PM PDT 24 |
1024915787 ps |
| T906 |
/workspace/coverage/default/39.sram_ctrl_regwen.783821357 |
|
|
Mar 12 03:03:01 PM PDT 24 |
Mar 12 03:20:04 PM PDT 24 |
3867433371 ps |
| T907 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.372462321 |
|
|
Mar 12 03:00:30 PM PDT 24 |
Mar 12 03:00:33 PM PDT 24 |
55539611 ps |
| T908 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.2524305082 |
|
|
Mar 12 03:03:53 PM PDT 24 |
Mar 12 03:07:48 PM PDT 24 |
5098235077 ps |
| T909 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.1267416679 |
|
|
Mar 12 02:59:54 PM PDT 24 |
Mar 12 03:00:35 PM PDT 24 |
108518319 ps |
| T910 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.2918247074 |
|
|
Mar 12 03:02:39 PM PDT 24 |
Mar 12 03:04:02 PM PDT 24 |
111613890 ps |
| T911 |
/workspace/coverage/default/40.sram_ctrl_smoke.735035348 |
|
|
Mar 12 03:03:10 PM PDT 24 |
Mar 12 03:03:15 PM PDT 24 |
494092976 ps |
| T912 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.2620051543 |
|
|
Mar 12 02:59:36 PM PDT 24 |
Mar 12 02:59:40 PM PDT 24 |
78161002 ps |
| T913 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.1325504691 |
|
|
Mar 12 02:59:50 PM PDT 24 |
Mar 12 02:59:56 PM PDT 24 |
1185518561 ps |
| T914 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.3875253874 |
|
|
Mar 12 03:00:00 PM PDT 24 |
Mar 12 03:07:01 PM PDT 24 |
10490478580 ps |
| T915 |
/workspace/coverage/default/40.sram_ctrl_max_throughput.297294749 |
|
|
Mar 12 03:03:09 PM PDT 24 |
Mar 12 03:03:59 PM PDT 24 |
362453345 ps |
| T916 |
/workspace/coverage/default/22.sram_ctrl_multiple_keys.3012913112 |
|
|
Mar 12 03:00:40 PM PDT 24 |
Mar 12 03:10:43 PM PDT 24 |
143184020708 ps |
| T917 |
/workspace/coverage/default/36.sram_ctrl_stress_all.148300843 |
|
|
Mar 12 03:02:41 PM PDT 24 |
Mar 12 04:28:29 PM PDT 24 |
294931563724 ps |
| T918 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.2543833399 |
|
|
Mar 12 03:03:45 PM PDT 24 |
Mar 12 03:08:08 PM PDT 24 |
11253013794 ps |
| T919 |
/workspace/coverage/default/37.sram_ctrl_bijection.632533988 |
|
|
Mar 12 03:02:39 PM PDT 24 |
Mar 12 03:03:17 PM PDT 24 |
22927473797 ps |
| T920 |
/workspace/coverage/default/41.sram_ctrl_mem_walk.2293527306 |
|
|
Mar 12 03:03:28 PM PDT 24 |
Mar 12 03:03:38 PM PDT 24 |
862373060 ps |
| T921 |
/workspace/coverage/default/9.sram_ctrl_stress_all.1982684482 |
|
|
Mar 12 02:59:46 PM PDT 24 |
Mar 12 03:51:43 PM PDT 24 |
194681073295 ps |
| T922 |
/workspace/coverage/default/48.sram_ctrl_smoke.1026146024 |
|
|
Mar 12 03:04:26 PM PDT 24 |
Mar 12 03:04:43 PM PDT 24 |
1279030651 ps |
| T923 |
/workspace/coverage/default/49.sram_ctrl_regwen.1491848521 |
|
|
Mar 12 03:04:43 PM PDT 24 |
Mar 12 03:16:56 PM PDT 24 |
12804881311 ps |
| T68 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2367169748 |
|
|
Mar 12 12:45:38 PM PDT 24 |
Mar 12 12:45:39 PM PDT 24 |
44919483 ps |
| T106 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1164476145 |
|
|
Mar 12 12:45:38 PM PDT 24 |
Mar 12 12:45:39 PM PDT 24 |
315022037 ps |
| T924 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1711427596 |
|
|
Mar 12 12:45:38 PM PDT 24 |
Mar 12 12:45:42 PM PDT 24 |
133040113 ps |
| T69 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.823712975 |
|
|
Mar 12 12:45:28 PM PDT 24 |
Mar 12 12:45:29 PM PDT 24 |
59653194 ps |
| T70 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.342617153 |
|
|
Mar 12 12:45:38 PM PDT 24 |
Mar 12 12:45:39 PM PDT 24 |
41257616 ps |
| T107 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.811310949 |
|
|
Mar 12 12:45:40 PM PDT 24 |
Mar 12 12:45:42 PM PDT 24 |
670371165 ps |
| T925 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2092235079 |
|
|
Mar 12 12:45:36 PM PDT 24 |
Mar 12 12:45:38 PM PDT 24 |
94585117 ps |
| T71 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1936209792 |
|
|
Mar 12 12:45:33 PM PDT 24 |
Mar 12 12:45:33 PM PDT 24 |
19935602 ps |
| T108 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1742066579 |
|
|
Mar 12 12:45:34 PM PDT 24 |
Mar 12 12:45:36 PM PDT 24 |
452789997 ps |
| T926 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.4181141308 |
|
|
Mar 12 12:45:38 PM PDT 24 |
Mar 12 12:45:39 PM PDT 24 |
68866513 ps |
| T927 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1743884289 |
|
|
Mar 12 12:45:37 PM PDT 24 |
Mar 12 12:45:38 PM PDT 24 |
94827334 ps |
| T98 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2181347220 |
|
|
Mar 12 12:45:38 PM PDT 24 |
Mar 12 12:45:39 PM PDT 24 |
39545321 ps |
| T120 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1028747353 |
|
|
Mar 12 12:45:32 PM PDT 24 |
Mar 12 12:45:34 PM PDT 24 |
194810069 ps |
| T928 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3499336329 |
|
|
Mar 12 12:46:03 PM PDT 24 |
Mar 12 12:46:05 PM PDT 24 |
419974602 ps |
| T929 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3701836498 |
|
|
Mar 12 12:45:37 PM PDT 24 |
Mar 12 12:45:41 PM PDT 24 |
512018280 ps |
| T930 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.605731490 |
|
|
Mar 12 12:45:34 PM PDT 24 |
Mar 12 12:45:37 PM PDT 24 |
101893040 ps |
| T931 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.4090451916 |
|
|
Mar 12 12:45:38 PM PDT 24 |
Mar 12 12:45:39 PM PDT 24 |
42399139 ps |
| T105 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2464256671 |
|
|
Mar 12 12:45:23 PM PDT 24 |
Mar 12 12:45:24 PM PDT 24 |
34196004 ps |
| T72 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3678559481 |
|
|
Mar 12 12:45:27 PM PDT 24 |
Mar 12 12:45:29 PM PDT 24 |
282664674 ps |
| T73 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1801075814 |
|
|
Mar 12 12:45:49 PM PDT 24 |
Mar 12 12:45:52 PM PDT 24 |
552463316 ps |
| T99 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3376987771 |
|
|
Mar 12 12:45:46 PM PDT 24 |
Mar 12 12:45:46 PM PDT 24 |
19742057 ps |
| T74 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1721632150 |
|
|
Mar 12 12:45:49 PM PDT 24 |
Mar 12 12:45:50 PM PDT 24 |
24679834 ps |
| T932 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3491237901 |
|
|
Mar 12 12:45:49 PM PDT 24 |
Mar 12 12:45:51 PM PDT 24 |
304130510 ps |
| T933 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2549753081 |
|
|
Mar 12 12:45:47 PM PDT 24 |
Mar 12 12:45:49 PM PDT 24 |
53170222 ps |
| T934 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1411579454 |
|
|
Mar 12 12:45:37 PM PDT 24 |
Mar 12 12:45:37 PM PDT 24 |
12504737 ps |
| T935 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.357122235 |
|
|
Mar 12 12:45:23 PM PDT 24 |
Mar 12 12:45:25 PM PDT 24 |
43490801 ps |
| T936 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3284773197 |
|
|
Mar 12 12:45:50 PM PDT 24 |
Mar 12 12:45:51 PM PDT 24 |
86592371 ps |
| T937 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.491306292 |
|
|
Mar 12 12:45:39 PM PDT 24 |
Mar 12 12:45:40 PM PDT 24 |
54655436 ps |
| T938 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2017967271 |
|
|
Mar 12 12:45:26 PM PDT 24 |
Mar 12 12:45:31 PM PDT 24 |
161118736 ps |
| T122 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3962028543 |
|
|
Mar 12 12:45:31 PM PDT 24 |
Mar 12 12:45:34 PM PDT 24 |
906293534 ps |
| T939 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2699357379 |
|
|
Mar 12 12:45:36 PM PDT 24 |
Mar 12 12:45:37 PM PDT 24 |
126131687 ps |
| T940 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1287552510 |
|
|
Mar 12 12:45:28 PM PDT 24 |
Mar 12 12:45:30 PM PDT 24 |
848499858 ps |
| T134 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3518882915 |
|
|
Mar 12 12:45:41 PM PDT 24 |
Mar 12 12:45:45 PM PDT 24 |
3849144117 ps |
| T941 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2898312845 |
|
|
Mar 12 12:45:33 PM PDT 24 |
Mar 12 12:45:35 PM PDT 24 |
28821657 ps |
| T942 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2872492145 |
|
|
Mar 12 12:45:32 PM PDT 24 |
Mar 12 12:45:36 PM PDT 24 |
133881478 ps |
| T121 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1176726589 |
|
|
Mar 12 12:45:37 PM PDT 24 |
Mar 12 12:45:39 PM PDT 24 |
77756732 ps |
| T100 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.4291847973 |
|
|
Mar 12 12:45:36 PM PDT 24 |
Mar 12 12:45:37 PM PDT 24 |
13785640 ps |
| T75 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3793742585 |
|
|
Mar 12 12:45:36 PM PDT 24 |
Mar 12 12:45:37 PM PDT 24 |
31705921 ps |
| T943 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3666222288 |
|
|
Mar 12 12:45:48 PM PDT 24 |
Mar 12 12:45:49 PM PDT 24 |
154559013 ps |
| T76 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2431222170 |
|
|
Mar 12 12:45:38 PM PDT 24 |
Mar 12 12:45:40 PM PDT 24 |
841367224 ps |
| T77 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.666403093 |
|
|
Mar 12 12:45:35 PM PDT 24 |
Mar 12 12:45:37 PM PDT 24 |
533661409 ps |
| T944 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.4178545729 |
|
|
Mar 12 12:45:33 PM PDT 24 |
Mar 12 12:45:34 PM PDT 24 |
22803026 ps |
| T90 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2661880795 |
|
|
Mar 12 12:45:46 PM PDT 24 |
Mar 12 12:45:50 PM PDT 24 |
801906415 ps |
| T945 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1283596265 |
|
|
Mar 12 12:45:30 PM PDT 24 |
Mar 12 12:45:34 PM PDT 24 |
183244142 ps |
| T946 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.160835604 |
|
|
Mar 12 12:45:39 PM PDT 24 |
Mar 12 12:45:40 PM PDT 24 |
55902923 ps |
| T947 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3532957583 |
|
|
Mar 12 12:45:24 PM PDT 24 |
Mar 12 12:45:25 PM PDT 24 |
101878418 ps |
| T948 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.558300822 |
|
|
Mar 12 12:45:46 PM PDT 24 |
Mar 12 12:45:47 PM PDT 24 |
12067209 ps |
| T949 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2961166520 |
|
|
Mar 12 12:45:29 PM PDT 24 |
Mar 12 12:45:31 PM PDT 24 |
117483135 ps |
| T131 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.804033559 |
|
|
Mar 12 12:45:32 PM PDT 24 |
Mar 12 12:45:33 PM PDT 24 |
864095764 ps |
| T950 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.47871653 |
|
|
Mar 12 12:45:41 PM PDT 24 |
Mar 12 12:45:41 PM PDT 24 |
13985039 ps |
| T951 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3480094768 |
|
|
Mar 12 12:45:51 PM PDT 24 |
Mar 12 12:45:51 PM PDT 24 |
13280733 ps |
| T124 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3164175024 |
|
|
Mar 12 12:45:46 PM PDT 24 |
Mar 12 12:45:49 PM PDT 24 |
609592914 ps |
| T952 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.553787769 |
|
|
Mar 12 12:45:43 PM PDT 24 |
Mar 12 12:45:45 PM PDT 24 |
523574845 ps |
| T79 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1778810631 |
|
|
Mar 12 12:45:38 PM PDT 24 |
Mar 12 12:45:41 PM PDT 24 |
421958455 ps |
| T953 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.515230715 |
|
|
Mar 12 12:45:46 PM PDT 24 |
Mar 12 12:45:48 PM PDT 24 |
249382360 ps |
| T954 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2181195716 |
|
|
Mar 12 12:45:33 PM PDT 24 |
Mar 12 12:45:36 PM PDT 24 |
141014355 ps |
| T125 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.396535254 |
|
|
Mar 12 12:45:47 PM PDT 24 |
Mar 12 12:45:48 PM PDT 24 |
312802917 ps |
| T955 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3564918387 |
|
|
Mar 12 12:45:40 PM PDT 24 |
Mar 12 12:45:41 PM PDT 24 |
41731338 ps |
| T956 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2294363454 |
|
|
Mar 12 12:45:37 PM PDT 24 |
Mar 12 12:45:39 PM PDT 24 |
257060860 ps |
| T957 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3464795302 |
|
|
Mar 12 12:45:36 PM PDT 24 |
Mar 12 12:45:36 PM PDT 24 |
13345283 ps |
| T958 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1449343760 |
|
|
Mar 12 12:45:48 PM PDT 24 |
Mar 12 12:45:49 PM PDT 24 |
35036539 ps |
| T80 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2288668233 |
|
|
Mar 12 12:45:38 PM PDT 24 |
Mar 12 12:45:40 PM PDT 24 |
920512077 ps |
| T959 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1037366092 |
|
|
Mar 12 12:45:39 PM PDT 24 |
Mar 12 12:45:40 PM PDT 24 |
126811917 ps |
| T960 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1355957181 |
|
|
Mar 12 12:45:25 PM PDT 24 |
Mar 12 12:45:27 PM PDT 24 |
282860847 ps |
| T961 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2108736976 |
|
|
Mar 12 12:45:35 PM PDT 24 |
Mar 12 12:45:35 PM PDT 24 |
27486569 ps |
| T81 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.953727564 |
|
|
Mar 12 12:45:38 PM PDT 24 |
Mar 12 12:45:40 PM PDT 24 |
863324629 ps |
| T962 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1012397870 |
|
|
Mar 12 12:45:29 PM PDT 24 |
Mar 12 12:45:30 PM PDT 24 |
21507546 ps |
| T963 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1300612853 |
|
|
Mar 12 12:45:46 PM PDT 24 |
Mar 12 12:45:48 PM PDT 24 |
117926201 ps |
| T132 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2818772858 |
|
|
Mar 12 12:45:48 PM PDT 24 |
Mar 12 12:45:49 PM PDT 24 |
319836951 ps |
| T964 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.862999509 |
|
|
Mar 12 12:45:35 PM PDT 24 |
Mar 12 12:45:37 PM PDT 24 |
105098048 ps |
| T965 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2595759222 |
|
|
Mar 12 12:45:40 PM PDT 24 |
Mar 12 12:45:41 PM PDT 24 |
35453802 ps |
| T82 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3445158708 |
|
|
Mar 12 12:45:38 PM PDT 24 |
Mar 12 12:45:40 PM PDT 24 |
259172872 ps |
| T126 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1134610780 |
|
|
Mar 12 12:45:37 PM PDT 24 |
Mar 12 12:45:40 PM PDT 24 |
704935667 ps |
| T966 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3801916212 |
|
|
Mar 12 12:45:34 PM PDT 24 |
Mar 12 12:45:35 PM PDT 24 |
21917506 ps |
| T967 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1389466343 |
|
|
Mar 12 12:45:50 PM PDT 24 |
Mar 12 12:45:53 PM PDT 24 |
105694278 ps |
| T968 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3044325722 |
|
|
Mar 12 12:45:50 PM PDT 24 |
Mar 12 12:45:51 PM PDT 24 |
17748435 ps |
| T969 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.456525736 |
|
|
Mar 12 12:45:40 PM PDT 24 |
Mar 12 12:45:41 PM PDT 24 |
64941093 ps |
| T91 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3528390397 |
|
|
Mar 12 12:45:35 PM PDT 24 |
Mar 12 12:45:37 PM PDT 24 |
3996818387 ps |
| T970 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3897228805 |
|
|
Mar 12 12:45:33 PM PDT 24 |
Mar 12 12:45:35 PM PDT 24 |
189138353 ps |
| T127 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.408920114 |
|
|
Mar 12 12:45:37 PM PDT 24 |
Mar 12 12:45:39 PM PDT 24 |
868536722 ps |
| T92 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1145183799 |
|
|
Mar 12 12:45:39 PM PDT 24 |
Mar 12 12:45:41 PM PDT 24 |
223837135 ps |
| T971 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.17068999 |
|
|
Mar 12 12:45:40 PM PDT 24 |
Mar 12 12:45:43 PM PDT 24 |
68271868 ps |
| T972 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1350008730 |
|
|
Mar 12 12:45:34 PM PDT 24 |
Mar 12 12:45:36 PM PDT 24 |
305103818 ps |
| T93 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3698673701 |
|
|
Mar 12 12:45:23 PM PDT 24 |
Mar 12 12:45:25 PM PDT 24 |
419451946 ps |
| T97 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3565128800 |
|
|
Mar 12 12:45:24 PM PDT 24 |
Mar 12 12:45:25 PM PDT 24 |
10630260 ps |
| T973 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2362057146 |
|
|
Mar 12 12:45:45 PM PDT 24 |
Mar 12 12:45:46 PM PDT 24 |
80908892 ps |
| T94 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.183431342 |
|
|
Mar 12 12:45:45 PM PDT 24 |
Mar 12 12:45:47 PM PDT 24 |
829590802 ps |
| T974 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2442272154 |
|
|
Mar 12 12:45:40 PM PDT 24 |
Mar 12 12:45:41 PM PDT 24 |
23957660 ps |
| T123 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.546597819 |
|
|
Mar 12 12:45:37 PM PDT 24 |
Mar 12 12:45:38 PM PDT 24 |
340867159 ps |
| T975 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3576250717 |
|
|
Mar 12 12:45:46 PM PDT 24 |
Mar 12 12:45:48 PM PDT 24 |
56088389 ps |
| T95 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3635942111 |
|
|
Mar 12 12:45:47 PM PDT 24 |
Mar 12 12:45:50 PM PDT 24 |
1654656198 ps |
| T976 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1292275670 |
|
|
Mar 12 12:45:40 PM PDT 24 |
Mar 12 12:45:41 PM PDT 24 |
77992703 ps |
| T977 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1111632767 |
|
|
Mar 12 12:45:40 PM PDT 24 |
Mar 12 12:45:42 PM PDT 24 |
359429102 ps |
| T133 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1662764086 |
|
|
Mar 12 12:45:47 PM PDT 24 |
Mar 12 12:45:49 PM PDT 24 |
239172329 ps |
| T978 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.842505482 |
|
|
Mar 12 12:45:39 PM PDT 24 |
Mar 12 12:45:43 PM PDT 24 |
633223365 ps |
| T979 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.4031467972 |
|
|
Mar 12 12:45:34 PM PDT 24 |
Mar 12 12:45:35 PM PDT 24 |
17291811 ps |
| T980 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.4156545029 |
|
|
Mar 12 12:45:28 PM PDT 24 |
Mar 12 12:45:30 PM PDT 24 |
365620429 ps |
| T981 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2020507803 |
|
|
Mar 12 12:45:24 PM PDT 24 |
Mar 12 12:45:25 PM PDT 24 |
42194642 ps |
| T982 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.647331761 |
|
|
Mar 12 12:45:29 PM PDT 24 |
Mar 12 12:45:29 PM PDT 24 |
21620226 ps |
| T983 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.925081395 |
|
|
Mar 12 12:45:42 PM PDT 24 |
Mar 12 12:45:43 PM PDT 24 |
40348588 ps |
| T984 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1478340532 |
|
|
Mar 12 12:45:32 PM PDT 24 |
Mar 12 12:45:33 PM PDT 24 |
19858772 ps |
| T985 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.581040708 |
|
|
Mar 12 12:45:37 PM PDT 24 |
Mar 12 12:45:38 PM PDT 24 |
12858655 ps |
| T96 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.112776495 |
|
|
Mar 12 12:45:48 PM PDT 24 |
Mar 12 12:45:52 PM PDT 24 |
3612766276 ps |
| T986 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.433864760 |
|
|
Mar 12 12:45:46 PM PDT 24 |
Mar 12 12:45:48 PM PDT 24 |
60980904 ps |
| T987 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.69749692 |
|
|
Mar 12 12:45:48 PM PDT 24 |
Mar 12 12:45:49 PM PDT 24 |
16644309 ps |
| T988 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.227619810 |
|
|
Mar 12 12:45:37 PM PDT 24 |
Mar 12 12:45:38 PM PDT 24 |
30926648 ps |
| T989 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2953569890 |
|
|
Mar 12 12:45:34 PM PDT 24 |
Mar 12 12:45:37 PM PDT 24 |
90980766 ps |
| T990 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2793875024 |
|
|
Mar 12 12:45:28 PM PDT 24 |
Mar 12 12:45:30 PM PDT 24 |
59677505 ps |
| T991 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1265219939 |
|
|
Mar 12 12:45:36 PM PDT 24 |
Mar 12 12:45:37 PM PDT 24 |
25200995 ps |
| T992 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1610058817 |
|
|
Mar 12 12:45:28 PM PDT 24 |
Mar 12 12:45:29 PM PDT 24 |
94739137 ps |
| T993 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.174730554 |
|
|
Mar 12 12:45:47 PM PDT 24 |
Mar 12 12:45:48 PM PDT 24 |
34088220 ps |
| T994 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1935238644 |
|
|
Mar 12 12:45:23 PM PDT 24 |
Mar 12 12:45:25 PM PDT 24 |
64545390 ps |
| T129 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1505612978 |
|
|
Mar 12 12:45:26 PM PDT 24 |
Mar 12 12:45:29 PM PDT 24 |
686934334 ps |
| T995 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2519765396 |
|
|
Mar 12 12:45:39 PM PDT 24 |
Mar 12 12:45:44 PM PDT 24 |
931611463 ps |
| T996 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.4111573330 |
|
|
Mar 12 12:45:39 PM PDT 24 |
Mar 12 12:45:40 PM PDT 24 |
24349809 ps |
| T997 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3086522822 |
|
|
Mar 12 12:45:27 PM PDT 24 |
Mar 12 12:45:28 PM PDT 24 |
17301646 ps |
| T130 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.964102534 |
|
|
Mar 12 12:45:28 PM PDT 24 |
Mar 12 12:45:31 PM PDT 24 |
298059570 ps |
| T998 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1373404406 |
|
|
Mar 12 12:45:34 PM PDT 24 |
Mar 12 12:45:35 PM PDT 24 |
38495511 ps |
| T999 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1214585049 |
|
|
Mar 12 12:45:46 PM PDT 24 |
Mar 12 12:45:48 PM PDT 24 |
230825074 ps |
| T1000 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2253175713 |
|
|
Mar 12 12:45:30 PM PDT 24 |
Mar 12 12:45:33 PM PDT 24 |
466331333 ps |
| T1001 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2273556614 |
|
|
Mar 12 12:45:37 PM PDT 24 |
Mar 12 12:45:38 PM PDT 24 |
40933189 ps |