Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::key_seed_valid_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::key_seed_valid_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::key_seed_valid_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	1	3	75.00
Crosses	4	2	2	50.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::key_seed_valid_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
escalated_cp	2	1	1	50.00	100	1	1	2
key_seed_valid_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::key_seed_valid_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
key_seed_valid_cross	4	2	2	50.00	100	1	1	0

Summary for Variable escalated_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for escalated_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

383

1

T2

2

T4

3

T6

11

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Summary for Variable key_seed_valid_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_seed_valid_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

189

1

T2

2

T4

1

T6

6

auto[1]

194

1

T4

2

T6

5

T7

10

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Summary for Cross key_seed_valid_cross

Samples crossed: key_seed_valid_cp escalated_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for key_seed_valid_cross

Element holes

key_seed_valid_cp	escalated_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

key_seed_valid_cp

escalated_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

189

1

T2

2

T4

1

T6

6

auto[1]

auto[0]

194

1

T4

2

T6

5

T7

10