Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
47.68 25.95 32.17 70.74 0.00 28.53 98.47 77.92


Total tests in report: 133
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
41.26 41.26 24.59 24.59 26.36 26.36 79.21 79.21 0.00 0.00 25.65 25.65 95.92 95.92 37.11 37.11 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1375506037
46.32 5.06 25.95 1.36 31.10 4.74 81.87 2.66 0.00 0.00 28.53 2.88 95.92 0.00 60.85 23.75 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3923673153
49.34 3.03 25.95 0.00 31.10 0.00 95.86 13.99 0.00 0.00 28.53 0.00 98.47 2.55 65.49 4.64 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.4049928194
50.69 1.34 25.95 0.00 31.52 0.42 97.24 1.38 0.00 0.00 28.53 0.00 98.47 0.00 73.10 7.61 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1948138075
51.05 0.36 25.95 0.00 31.66 0.14 97.24 0.00 0.00 0.00 28.53 0.00 98.47 0.00 75.51 2.41 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3351822972
51.24 0.19 25.95 0.00 31.66 0.00 97.44 0.20 0.00 0.00 28.53 0.00 98.47 0.00 76.62 1.11 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1525941892
51.41 0.17 25.95 0.00 31.94 0.28 97.44 0.00 0.00 0.00 28.53 0.00 98.47 0.00 77.55 0.93 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1888449682
51.46 0.05 25.95 0.00 32.08 0.14 97.44 0.00 0.00 0.00 28.53 0.00 98.47 0.00 77.74 0.19 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2346231902
51.48 0.03 25.95 0.00 32.08 0.00 97.44 0.00 0.00 0.00 28.53 0.00 98.47 0.00 77.92 0.19 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2262776014
51.50 0.02 25.95 0.00 32.22 0.14 97.44 0.00 0.00 0.00 28.53 0.00 98.47 0.00 77.92 0.00 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1054254826

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3713002478
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1203558088
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.126068719
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1187458956
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1744833743
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1172776929
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3149715113
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2319324179
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2102641854
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2708190519
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.4002618890
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1333504124
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3997880864
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2318873701
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1855656640
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1315523995
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1172011193
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2036868650
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2459464267
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.826135644
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.4240423634
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3267833579
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1655646406
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.79273753
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2101838741
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.683012110
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.482775863
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1053215275
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2551702640
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2751532014
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3527679128
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2028906089
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3982162238
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2912495771
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.288148147
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2799317885
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2674122793
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.75075179
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2315869052
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1903478220
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.4069515124
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3366144130
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3208613251
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3578774099
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.588380416
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3998900469
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3121696993
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2825860509
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2144099645
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.317548602
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3537298355
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3318006349
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1886771585
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1785677281
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3760122374
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1475964080
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.4061317678
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3658246992
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.4113300151
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.69404808
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1452512090
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.4206225689
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2729825785
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2675399865
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1613540491
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2789949437
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2324057405
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3949403399
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3579522903
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.854724078
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3269263688
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1435837295
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2913428404
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1005983418
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.288454098
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2832051690
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1868584946
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3683221296
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3635696771
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.767947896
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1158084504
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2863474021
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.655130246
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1988464402
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1239523007
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2782897208
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.4262335454
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.165924987
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1319206418
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.183611423
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3141662697
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.4106622679
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2192889468
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.396662907
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2506003310
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3551840703
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2219299924
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3466106659
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3423003564
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2094271258
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2934727418
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3259746334
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1635446475
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3239908365
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.883835534
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3728149679
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2314744875
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.4170279653
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.625742700
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1933839215
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.4013423754
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3596000007
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3033084808
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3322173670
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3917876388
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2946181313
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3310278816
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.206655123
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.797307953
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.203455799
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1429815757
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1875532479
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3362111504



Total test records in report: 133
tests.html | tests1.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1948138075 Mar 14 12:26:03 PM PDT 24 Mar 14 12:26:07 PM PDT 24 562254510 ps
T2 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2262776014 Mar 14 12:26:44 PM PDT 24 Mar 14 12:26:46 PM PDT 24 30723296 ps
T3 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2675399865 Mar 14 12:26:01 PM PDT 24 Mar 14 12:26:02 PM PDT 24 110928475 ps
T5 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3033084808 Mar 14 12:25:58 PM PDT 24 Mar 14 12:25:59 PM PDT 24 11898858 ps
T4 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1375506037 Mar 14 12:25:41 PM PDT 24 Mar 14 12:25:42 PM PDT 24 141415986 ps
T10 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2318873701 Mar 14 12:25:42 PM PDT 24 Mar 14 12:25:43 PM PDT 24 15828255 ps
T13 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3269263688 Mar 14 12:27:02 PM PDT 24 Mar 14 12:27:02 PM PDT 24 53577839 ps
T11 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3579522903 Mar 14 12:25:59 PM PDT 24 Mar 14 12:26:00 PM PDT 24 20943302 ps
T9 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3923673153 Mar 14 12:25:58 PM PDT 24 Mar 14 12:25:59 PM PDT 24 442755495 ps
T6 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.588380416 Mar 14 12:25:32 PM PDT 24 Mar 14 12:25:34 PM PDT 24 264953989 ps
T21 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.883835534 Mar 14 12:26:02 PM PDT 24 Mar 14 12:26:03 PM PDT 24 77495460 ps
T7 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3239908365 Mar 14 12:26:01 PM PDT 24 Mar 14 12:26:04 PM PDT 24 1936833282 ps
T12 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3267833579 Mar 14 12:25:50 PM PDT 24 Mar 14 12:25:51 PM PDT 24 42698361 ps
T14 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3596000007 Mar 14 12:25:51 PM PDT 24 Mar 14 12:25:53 PM PDT 24 134998423 ps
T8 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.4049928194 Mar 14 12:25:57 PM PDT 24 Mar 14 12:26:00 PM PDT 24 1281587965 ps
T22 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3141662697 Mar 14 12:27:11 PM PDT 24 Mar 14 12:27:11 PM PDT 24 19384645 ps
T29 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1172011193 Mar 14 12:26:02 PM PDT 24 Mar 14 12:26:03 PM PDT 24 16294197 ps
T15 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2094271258 Mar 14 12:26:02 PM PDT 24 Mar 14 12:26:04 PM PDT 24 1014981091 ps
T30 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.797307953 Mar 14 12:25:54 PM PDT 24 Mar 14 12:25:55 PM PDT 24 24821749 ps
T16 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3527679128 Mar 14 12:27:02 PM PDT 24 Mar 14 12:27:05 PM PDT 24 67415164 ps
T37 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3578774099 Mar 14 12:26:03 PM PDT 24 Mar 14 12:26:04 PM PDT 24 10974675 ps
T17 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2346231902 Mar 14 12:24:05 PM PDT 24 Mar 14 12:24:08 PM PDT 24 885437224 ps
T32 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1635446475 Mar 14 12:25:53 PM PDT 24 Mar 14 12:25:54 PM PDT 24 25036842 ps
T46 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1158084504 Mar 14 12:25:51 PM PDT 24 Mar 14 12:25:54 PM PDT 24 433900099 ps
T18 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2144099645 Mar 14 12:25:58 PM PDT 24 Mar 14 12:26:01 PM PDT 24 36230452 ps
T19 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3208613251 Mar 14 12:25:35 PM PDT 24 Mar 14 12:25:37 PM PDT 24 43862105 ps
T65 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1435837295 Mar 14 12:26:00 PM PDT 24 Mar 14 12:26:02 PM PDT 24 466910182 ps
T66 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.183611423 Mar 14 12:26:02 PM PDT 24 Mar 14 12:26:05 PM PDT 24 580209115 ps
T20 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.826135644 Mar 14 12:26:04 PM PDT 24 Mar 14 12:26:07 PM PDT 24 72456031 ps
T31 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1613540491 Mar 14 12:26:02 PM PDT 24 Mar 14 12:26:04 PM PDT 24 358343600 ps
T50 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3259746334 Mar 14 12:27:02 PM PDT 24 Mar 14 12:27:04 PM PDT 24 75119120 ps
T64 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3466106659 Mar 14 12:26:45 PM PDT 24 Mar 14 12:26:47 PM PDT 24 251031109 ps
T67 /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3998900469 Mar 14 12:25:40 PM PDT 24 Mar 14 12:25:41 PM PDT 24 52840925 ps
T33 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2459464267 Mar 14 12:27:02 PM PDT 24 Mar 14 12:27:03 PM PDT 24 36331105 ps
T68 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2192889468 Mar 14 12:25:47 PM PDT 24 Mar 14 12:25:48 PM PDT 24 15600357 ps
T51 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.683012110 Mar 14 12:25:46 PM PDT 24 Mar 14 12:25:49 PM PDT 24 88555149 ps
T69 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1888449682 Mar 14 12:26:20 PM PDT 24 Mar 14 12:26:24 PM PDT 24 145958805 ps
T70 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1187458956 Mar 14 12:23:40 PM PDT 24 Mar 14 12:23:42 PM PDT 24 31048022 ps
T71 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.4106622679 Mar 14 12:25:58 PM PDT 24 Mar 14 12:25:59 PM PDT 24 100631714 ps
T52 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1988464402 Mar 14 12:26:36 PM PDT 24 Mar 14 12:26:38 PM PDT 24 12361592 ps
T23 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3949403399 Mar 14 12:25:56 PM PDT 24 Mar 14 12:25:59 PM PDT 24 776370267 ps
T72 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1172776929 Mar 14 12:21:19 PM PDT 24 Mar 14 12:21:20 PM PDT 24 40673643 ps
T34 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3423003564 Mar 14 12:26:54 PM PDT 24 Mar 14 12:26:55 PM PDT 24 41504759 ps
T73 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3318006349 Mar 14 12:27:05 PM PDT 24 Mar 14 12:27:06 PM PDT 24 55246212 ps
T74 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3982162238 Mar 14 12:26:45 PM PDT 24 Mar 14 12:26:46 PM PDT 24 20032807 ps
T47 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3351822972 Mar 14 12:25:41 PM PDT 24 Mar 14 12:25:44 PM PDT 24 297931426 ps
T75 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3760122374 Mar 14 12:26:05 PM PDT 24 Mar 14 12:26:06 PM PDT 24 57950942 ps
T53 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3310278816 Mar 14 12:25:58 PM PDT 24 Mar 14 12:26:00 PM PDT 24 379561777 ps
T76 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3713002478 Mar 14 12:23:33 PM PDT 24 Mar 14 12:23:34 PM PDT 24 17662309 ps
T48 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1054254826 Mar 14 12:19:10 PM PDT 24 Mar 14 12:19:11 PM PDT 24 14308309 ps
T77 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1203558088 Mar 14 12:20:31 PM PDT 24 Mar 14 12:20:34 PM PDT 24 401418610 ps
T78 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.206655123 Mar 14 12:27:03 PM PDT 24 Mar 14 12:27:04 PM PDT 24 101164849 ps
T79 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1333504124 Mar 14 12:25:53 PM PDT 24 Mar 14 12:25:54 PM PDT 24 41189099 ps
T60 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.165924987 Mar 14 12:26:02 PM PDT 24 Mar 14 12:26:05 PM PDT 24 327774900 ps
T80 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.4113300151 Mar 14 12:25:53 PM PDT 24 Mar 14 12:25:58 PM PDT 24 582535755 ps
T59 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.69404808 Mar 14 12:26:03 PM PDT 24 Mar 14 12:26:06 PM PDT 24 174849014 ps
T24 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3997880864 Mar 14 12:24:33 PM PDT 24 Mar 14 12:24:37 PM PDT 24 4832327879 ps
T25 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2832051690 Mar 14 12:25:36 PM PDT 24 Mar 14 12:25:38 PM PDT 24 842285580 ps
T26 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.203455799 Mar 14 12:26:05 PM PDT 24 Mar 14 12:26:12 PM PDT 24 367377802 ps
T27 /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2729825785 Mar 14 12:26:36 PM PDT 24 Mar 14 12:26:41 PM PDT 24 1589698263 ps
T81 /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1868584946 Mar 14 12:27:03 PM PDT 24 Mar 14 12:27:03 PM PDT 24 20441746 ps
T82 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1875532479 Mar 14 12:27:05 PM PDT 24 Mar 14 12:27:08 PM PDT 24 140056877 ps
T83 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.655130246 Mar 14 12:27:05 PM PDT 24 Mar 14 12:27:07 PM PDT 24 117936156 ps
T84 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2674122793 Mar 14 12:26:02 PM PDT 24 Mar 14 12:26:04 PM PDT 24 106141976 ps
T28 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2315869052 Mar 14 12:25:58 PM PDT 24 Mar 14 12:26:01 PM PDT 24 454797517 ps
T85 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1005983418 Mar 14 12:25:54 PM PDT 24 Mar 14 12:25:55 PM PDT 24 101080841 ps
T86 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3728149679 Mar 14 12:25:46 PM PDT 24 Mar 14 12:25:50 PM PDT 24 142009410 ps
T87 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2782897208 Mar 14 12:26:02 PM PDT 24 Mar 14 12:26:03 PM PDT 24 124616445 ps
T35 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1319206418 Mar 14 12:26:03 PM PDT 24 Mar 14 12:26:04 PM PDT 24 17693202 ps
T54 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1785677281 Mar 14 12:25:39 PM PDT 24 Mar 14 12:25:41 PM PDT 24 710475114 ps
T88 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1855656640 Mar 14 12:25:59 PM PDT 24 Mar 14 12:26:03 PM PDT 24 46930228 ps
T89 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.126068719 Mar 14 12:19:11 PM PDT 24 Mar 14 12:19:14 PM PDT 24 106828268 ps
T55 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3366144130 Mar 14 12:25:48 PM PDT 24 Mar 14 12:25:50 PM PDT 24 331783536 ps
T90 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.4170279653 Mar 14 12:25:58 PM PDT 24 Mar 14 12:26:01 PM PDT 24 37688294 ps
T91 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2799317885 Mar 14 12:26:46 PM PDT 24 Mar 14 12:26:50 PM PDT 24 391311375 ps
T92 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.288454098 Mar 14 12:26:05 PM PDT 24 Mar 14 12:26:11 PM PDT 24 37813086 ps
T93 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3551840703 Mar 14 12:26:03 PM PDT 24 Mar 14 12:26:05 PM PDT 24 28050580 ps
T56 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3635696771 Mar 14 12:26:06 PM PDT 24 Mar 14 12:26:13 PM PDT 24 314933320 ps
T94 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1429815757 Mar 14 12:26:02 PM PDT 24 Mar 14 12:26:03 PM PDT 24 21869663 ps
T63 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2314744875 Mar 14 12:25:59 PM PDT 24 Mar 14 12:26:01 PM PDT 24 1064411094 ps
T95 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2946181313 Mar 14 12:25:58 PM PDT 24 Mar 14 12:26:01 PM PDT 24 44832693 ps
T96 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.482775863 Mar 14 12:26:03 PM PDT 24 Mar 14 12:26:04 PM PDT 24 375646486 ps
T97 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.317548602 Mar 14 12:25:58 PM PDT 24 Mar 14 12:25:59 PM PDT 24 11810482 ps
T57 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2789949437 Mar 14 12:25:55 PM PDT 24 Mar 14 12:25:57 PM PDT 24 744202823 ps
T98 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.75075179 Mar 14 12:25:41 PM PDT 24 Mar 14 12:25:42 PM PDT 24 51209964 ps
T38 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3537298355 Mar 14 12:27:03 PM PDT 24 Mar 14 12:27:06 PM PDT 24 880538478 ps
T99 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2751532014 Mar 14 12:27:04 PM PDT 24 Mar 14 12:27:05 PM PDT 24 48558318 ps
T100 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3658246992 Mar 14 12:25:55 PM PDT 24 Mar 14 12:25:56 PM PDT 24 22194039 ps
T39 /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1239523007 Mar 14 12:25:40 PM PDT 24 Mar 14 12:25:42 PM PDT 24 1806336318 ps
T101 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3121696993 Mar 14 12:26:01 PM PDT 24 Mar 14 12:26:04 PM PDT 24 58828953 ps
T102 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2219299924 Mar 14 12:26:02 PM PDT 24 Mar 14 12:26:04 PM PDT 24 329482025 ps
T49 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2913428404 Mar 14 12:25:39 PM PDT 24 Mar 14 12:25:45 PM PDT 24 16948212 ps
T103 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1903478220 Mar 14 12:26:09 PM PDT 24 Mar 14 12:26:10 PM PDT 24 81936081 ps
T40 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.625742700 Mar 14 12:26:01 PM PDT 24 Mar 14 12:26:02 PM PDT 24 18960092 ps
T62 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.4240423634 Mar 14 12:27:03 PM PDT 24 Mar 14 12:27:05 PM PDT 24 158695373 ps
T58 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1525941892 Mar 14 12:26:44 PM PDT 24 Mar 14 12:26:47 PM PDT 24 426678280 ps
T104 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1744833743 Mar 14 12:23:17 PM PDT 24 Mar 14 12:23:21 PM PDT 24 885353988 ps
T105 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2506003310 Mar 14 12:26:02 PM PDT 24 Mar 14 12:26:03 PM PDT 24 25432957 ps
T106 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1053215275 Mar 14 12:26:44 PM PDT 24 Mar 14 12:26:45 PM PDT 24 21231575 ps
T107 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3362111504 Mar 14 12:27:01 PM PDT 24 Mar 14 12:27:04 PM PDT 24 948606802 ps
T108 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2863474021 Mar 14 12:27:05 PM PDT 24 Mar 14 12:27:06 PM PDT 24 120389492 ps
T109 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.288148147 Mar 14 12:26:44 PM PDT 24 Mar 14 12:26:45 PM PDT 24 20333181 ps
T110 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1475964080 Mar 14 12:25:54 PM PDT 24 Mar 14 12:25:55 PM PDT 24 37788343 ps
T111 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1655646406 Mar 14 12:25:48 PM PDT 24 Mar 14 12:25:48 PM PDT 24 31923096 ps
T36 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2324057405 Mar 14 12:26:13 PM PDT 24 Mar 14 12:26:14 PM PDT 24 20830188 ps
T112 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.4069515124 Mar 14 12:25:45 PM PDT 24 Mar 14 12:25:49 PM PDT 24 127500645 ps
T41 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2551702640 Mar 14 12:25:40 PM PDT 24 Mar 14 12:25:44 PM PDT 24 1695609157 ps
T45 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3322173670 Mar 14 12:25:45 PM PDT 24 Mar 14 12:25:47 PM PDT 24 219390085 ps
T113 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.79273753 Mar 14 12:25:54 PM PDT 24 Mar 14 12:25:57 PM PDT 24 1519387734 ps
T114 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3149715113 Mar 14 12:19:18 PM PDT 24 Mar 14 12:19:21 PM PDT 24 164528883 ps
T42 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2912495771 Mar 14 12:25:58 PM PDT 24 Mar 14 12:26:00 PM PDT 24 734855617 ps
T115 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.767947896 Mar 14 12:27:02 PM PDT 24 Mar 14 12:27:03 PM PDT 24 94584918 ps
T43 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2036868650 Mar 14 12:27:05 PM PDT 24 Mar 14 12:27:08 PM PDT 24 2199696025 ps
T116 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.4206225689 Mar 14 12:25:50 PM PDT 24 Mar 14 12:25:50 PM PDT 24 27089168 ps
T117 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2102641854 Mar 14 12:25:59 PM PDT 24 Mar 14 12:26:00 PM PDT 24 185633480 ps
T118 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.396662907 Mar 14 12:26:02 PM PDT 24 Mar 14 12:26:06 PM PDT 24 1521027662 ps
T44 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.4061317678 Mar 14 12:26:02 PM PDT 24 Mar 14 12:26:05 PM PDT 24 2265588630 ps
T119 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.4013423754 Mar 14 12:25:57 PM PDT 24 Mar 14 12:25:59 PM PDT 24 164581250 ps
T61 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2825860509 Mar 14 12:25:53 PM PDT 24 Mar 14 12:25:56 PM PDT 24 694662331 ps
T120 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2934727418 Mar 14 12:26:46 PM PDT 24 Mar 14 12:26:47 PM PDT 24 40909839 ps
T121 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2708190519 Mar 14 12:25:56 PM PDT 24 Mar 14 12:25:57 PM PDT 24 13154272 ps
T122 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2101838741 Mar 14 12:25:47 PM PDT 24 Mar 14 12:25:48 PM PDT 24 13360425 ps
T123 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3683221296 Mar 14 12:26:59 PM PDT 24 Mar 14 12:27:01 PM PDT 24 70957535 ps
T124 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1452512090 Mar 14 12:25:58 PM PDT 24 Mar 14 12:25:59 PM PDT 24 31630201 ps
T125 /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1933839215 Mar 14 12:26:02 PM PDT 24 Mar 14 12:26:03 PM PDT 24 21965265 ps
T126 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2319324179 Mar 14 12:25:44 PM PDT 24 Mar 14 12:25:45 PM PDT 24 38327277 ps
T127 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1315523995 Mar 14 12:25:59 PM PDT 24 Mar 14 12:26:00 PM PDT 24 223412304 ps
T128 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.854724078 Mar 14 12:25:57 PM PDT 24 Mar 14 12:26:00 PM PDT 24 318882136 ps
T129 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3917876388 Mar 14 12:27:04 PM PDT 24 Mar 14 12:27:05 PM PDT 24 32636159 ps
T130 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.4002618890 Mar 14 12:25:56 PM PDT 24 Mar 14 12:25:58 PM PDT 24 39070901 ps
T131 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1886771585 Mar 14 12:25:58 PM PDT 24 Mar 14 12:26:00 PM PDT 24 293392498 ps
T132 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2028906089 Mar 14 12:26:46 PM PDT 24 Mar 14 12:26:48 PM PDT 24 69960663 ps
T133 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.4262335454 Mar 14 12:25:54 PM PDT 24 Mar 14 12:25:58 PM PDT 24 105814780 ps

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1375506037
Short name T4
Test name
Test status
Simulation time 141415986 ps
CPU time 1.23 seconds
Started Mar 14 12:25:41 PM PDT 24
Finished Mar 14 12:25:42 PM PDT 24
Peak memory 209944 kb
Host smart-bd6817a7-27e4-4ecf-ba5c-45628073bc2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375506037 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.1375506037
Directory /workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3923673153
Short name T9
Test name
Test status
Simulation time 442755495 ps
CPU time 1.31 seconds
Started Mar 14 12:25:58 PM PDT 24
Finished Mar 14 12:25:59 PM PDT 24
Peak memory 201996 kb
Host smart-120f2030-292a-42ef-829c-a2370ee86daf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923673153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 12.sram_ctrl_tl_intg_err.3923673153
Directory /workspace/12.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.4049928194
Short name T8
Test name
Test status
Simulation time 1281587965 ps
CPU time 2.97 seconds
Started Mar 14 12:25:57 PM PDT 24
Finished Mar 14 12:26:00 PM PDT 24
Peak memory 202080 kb
Host smart-55c9a0a2-8133-4843-9f8f-d144509e3f3f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049928194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.4049928194
Directory /workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1948138075
Short name T1
Test name
Test status
Simulation time 562254510 ps
CPU time 3.02 seconds
Started Mar 14 12:26:03 PM PDT 24
Finished Mar 14 12:26:07 PM PDT 24
Peak memory 201960 kb
Host smart-96f07361-6a97-4708-96ef-8253f3bd7b12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948138075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.sram_ctrl_tl_errors.1948138075
Directory /workspace/7.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3351822972
Short name T47
Test name
Test status
Simulation time 297931426 ps
CPU time 2.15 seconds
Started Mar 14 12:25:41 PM PDT 24
Finished Mar 14 12:25:44 PM PDT 24
Peak memory 201916 kb
Host smart-11dc34b9-d5ca-44e6-aaf3-8a9870b4c40f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351822972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 5.sram_ctrl_tl_intg_err.3351822972
Directory /workspace/5.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1525941892
Short name T58
Test name
Test status
Simulation time 426678280 ps
CPU time 2.38 seconds
Started Mar 14 12:26:44 PM PDT 24
Finished Mar 14 12:26:47 PM PDT 24
Peak memory 200940 kb
Host smart-866365c6-d584-4bfe-9053-a7930bf14bb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525941892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 13.sram_ctrl_tl_intg_err.1525941892
Directory /workspace/13.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1888449682
Short name T69
Test name
Test status
Simulation time 145958805 ps
CPU time 3.49 seconds
Started Mar 14 12:26:20 PM PDT 24
Finished Mar 14 12:26:24 PM PDT 24
Peak memory 201952 kb
Host smart-9d829977-5a20-4bed-89d3-ca7b4a6956da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888449682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 19.sram_ctrl_tl_errors.1888449682
Directory /workspace/19.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2346231902
Short name T17
Test name
Test status
Simulation time 885437224 ps
CPU time 2.1 seconds
Started Mar 14 12:24:05 PM PDT 24
Finished Mar 14 12:24:08 PM PDT 24
Peak memory 201300 kb
Host smart-42315635-9742-4d19-bbec-65df82453b2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346231902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 0.sram_ctrl_tl_intg_err.2346231902
Directory /workspace/0.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2262776014
Short name T2
Test name
Test status
Simulation time 30723296 ps
CPU time 0.97 seconds
Started Mar 14 12:26:44 PM PDT 24
Finished Mar 14 12:26:46 PM PDT 24
Peak memory 209796 kb
Host smart-8a33e834-87fb-438f-a508-41f12a555622
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262776014 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.2262776014
Directory /workspace/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1054254826
Short name T48
Test name
Test status
Simulation time 14308309 ps
CPU time 0.65 seconds
Started Mar 14 12:19:10 PM PDT 24
Finished Mar 14 12:19:11 PM PDT 24
Peak memory 201724 kb
Host smart-9e5180fd-0021-4f4c-80c5-5d37651f365d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054254826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_hw_reset.1054254826
Directory /workspace/0.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3713002478
Short name T76
Test name
Test status
Simulation time 17662309 ps
CPU time 0.71 seconds
Started Mar 14 12:23:33 PM PDT 24
Finished Mar 14 12:23:34 PM PDT 24
Peak memory 200320 kb
Host smart-2adb3246-a8ae-4cfa-8805-9a7f30435068
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713002478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_aliasing.3713002478
Directory /workspace/0.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1203558088
Short name T77
Test name
Test status
Simulation time 401418610 ps
CPU time 1.97 seconds
Started Mar 14 12:20:31 PM PDT 24
Finished Mar 14 12:20:34 PM PDT 24
Peak memory 201912 kb
Host smart-dfac47d1-8462-40a1-809a-bb1cebe80180
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203558088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_bit_bash.1203558088
Directory /workspace/0.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.126068719
Short name T89
Test name
Test status
Simulation time 106828268 ps
CPU time 2.19 seconds
Started Mar 14 12:19:11 PM PDT 24
Finished Mar 14 12:19:14 PM PDT 24
Peak memory 210112 kb
Host smart-30093293-1f69-458e-8e5e-e394c8b2f3fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126068719 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.126068719
Directory /workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1187458956
Short name T70
Test name
Test status
Simulation time 31048022 ps
CPU time 0.7 seconds
Started Mar 14 12:23:40 PM PDT 24
Finished Mar 14 12:23:42 PM PDT 24
Peak memory 200888 kb
Host smart-7bab4f45-6e31-4a9c-a8d7-d176a4cc0ef9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187458956 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 0.sram_ctrl_csr_rw.1187458956
Directory /workspace/0.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1744833743
Short name T104
Test name
Test status
Simulation time 885353988 ps
CPU time 3.04 seconds
Started Mar 14 12:23:17 PM PDT 24
Finished Mar 14 12:23:21 PM PDT 24
Peak memory 201216 kb
Host smart-dcdcb037-a831-4f86-b52c-9d5b05b62609
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744833743 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.1744833743
Directory /workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1172776929
Short name T72
Test name
Test status
Simulation time 40673643 ps
CPU time 0.83 seconds
Started Mar 14 12:21:19 PM PDT 24
Finished Mar 14 12:21:20 PM PDT 24
Peak memory 201824 kb
Host smart-9dd16337-0dcf-4227-bd88-37fd0f7ba770
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172776929 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.1172776929
Directory /workspace/0.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3149715113
Short name T114
Test name
Test status
Simulation time 164528883 ps
CPU time 3.25 seconds
Started Mar 14 12:19:18 PM PDT 24
Finished Mar 14 12:19:21 PM PDT 24
Peak memory 202356 kb
Host smart-eaf8db91-9535-47b8-9e50-4db84be6627f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149715113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.sram_ctrl_tl_errors.3149715113
Directory /workspace/0.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2319324179
Short name T126
Test name
Test status
Simulation time 38327277 ps
CPU time 0.72 seconds
Started Mar 14 12:25:44 PM PDT 24
Finished Mar 14 12:25:45 PM PDT 24
Peak memory 201672 kb
Host smart-52f243b6-7687-4fb1-a311-78bdd5f1d548
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319324179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_aliasing.2319324179
Directory /workspace/1.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2102641854
Short name T117
Test name
Test status
Simulation time 185633480 ps
CPU time 1.27 seconds
Started Mar 14 12:25:59 PM PDT 24
Finished Mar 14 12:26:00 PM PDT 24
Peak memory 201852 kb
Host smart-03a5c1d4-2cee-4c4c-a777-0080b15a8444
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102641854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_bit_bash.2102641854
Directory /workspace/1.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2708190519
Short name T121
Test name
Test status
Simulation time 13154272 ps
CPU time 0.63 seconds
Started Mar 14 12:25:56 PM PDT 24
Finished Mar 14 12:25:57 PM PDT 24
Peak memory 201688 kb
Host smart-338a724e-c86a-45f5-9563-132ac7fd3949
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708190519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_hw_reset.2708190519
Directory /workspace/1.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.4002618890
Short name T130
Test name
Test status
Simulation time 39070901 ps
CPU time 1.23 seconds
Started Mar 14 12:25:56 PM PDT 24
Finished Mar 14 12:25:58 PM PDT 24
Peak memory 210964 kb
Host smart-23df9d76-b29c-4c4f-87dc-fae169f51ad6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002618890 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.4002618890
Directory /workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1333504124
Short name T79
Test name
Test status
Simulation time 41189099 ps
CPU time 0.74 seconds
Started Mar 14 12:25:53 PM PDT 24
Finished Mar 14 12:25:54 PM PDT 24
Peak memory 201796 kb
Host smart-8dcac7c2-e362-4f29-b429-c4e160d29939
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333504124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 1.sram_ctrl_csr_rw.1333504124
Directory /workspace/1.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3997880864
Short name T24
Test name
Test status
Simulation time 4832327879 ps
CPU time 3.85 seconds
Started Mar 14 12:24:33 PM PDT 24
Finished Mar 14 12:24:37 PM PDT 24
Peak memory 202100 kb
Host smart-c7a234c4-2d76-4980-a42a-900a1ee2ebc8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997880864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.3997880864
Directory /workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2318873701
Short name T10
Test name
Test status
Simulation time 15828255 ps
CPU time 0.66 seconds
Started Mar 14 12:25:42 PM PDT 24
Finished Mar 14 12:25:43 PM PDT 24
Peak memory 201576 kb
Host smart-900d189d-e830-44b0-b64a-53721e9e0e9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318873701 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.2318873701
Directory /workspace/1.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1855656640
Short name T88
Test name
Test status
Simulation time 46930228 ps
CPU time 4.04 seconds
Started Mar 14 12:25:59 PM PDT 24
Finished Mar 14 12:26:03 PM PDT 24
Peak memory 201904 kb
Host smart-413b34f6-0142-4649-9898-348ec979a340
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855656640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.sram_ctrl_tl_errors.1855656640
Directory /workspace/1.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1315523995
Short name T127
Test name
Test status
Simulation time 223412304 ps
CPU time 1.52 seconds
Started Mar 14 12:25:59 PM PDT 24
Finished Mar 14 12:26:00 PM PDT 24
Peak memory 201880 kb
Host smart-82e4de37-5941-4ea7-a666-8b3368175db5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315523995 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 1.sram_ctrl_tl_intg_err.1315523995
Directory /workspace/1.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1172011193
Short name T29
Test name
Test status
Simulation time 16294197 ps
CPU time 0.66 seconds
Started Mar 14 12:26:02 PM PDT 24
Finished Mar 14 12:26:03 PM PDT 24
Peak memory 201696 kb
Host smart-74bb0f67-3006-4c15-ae17-1c9412d4f1d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172011193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 10.sram_ctrl_csr_rw.1172011193
Directory /workspace/10.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2036868650
Short name T43
Test name
Test status
Simulation time 2199696025 ps
CPU time 3.04 seconds
Started Mar 14 12:27:05 PM PDT 24
Finished Mar 14 12:27:08 PM PDT 24
Peak memory 202144 kb
Host smart-8c6a0a16-a420-433f-b64e-59cf1ee27533
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036868650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.2036868650
Directory /workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2459464267
Short name T33
Test name
Test status
Simulation time 36331105 ps
CPU time 0.74 seconds
Started Mar 14 12:27:02 PM PDT 24
Finished Mar 14 12:27:03 PM PDT 24
Peak memory 201728 kb
Host smart-dc3dcf2d-e296-40cd-be16-d09607017572
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459464267 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.2459464267
Directory /workspace/10.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.826135644
Short name T20
Test name
Test status
Simulation time 72456031 ps
CPU time 2.94 seconds
Started Mar 14 12:26:04 PM PDT 24
Finished Mar 14 12:26:07 PM PDT 24
Peak memory 201948 kb
Host smart-11e36f37-e142-46a1-bcdc-abf0e48f84d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826135644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
10.sram_ctrl_tl_errors.826135644
Directory /workspace/10.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.4240423634
Short name T62
Test name
Test status
Simulation time 158695373 ps
CPU time 2.02 seconds
Started Mar 14 12:27:03 PM PDT 24
Finished Mar 14 12:27:05 PM PDT 24
Peak memory 201952 kb
Host smart-439fdc1c-939e-4210-9919-b166c94c60bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240423634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 10.sram_ctrl_tl_intg_err.4240423634
Directory /workspace/10.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3267833579
Short name T12
Test name
Test status
Simulation time 42698361 ps
CPU time 0.94 seconds
Started Mar 14 12:25:50 PM PDT 24
Finished Mar 14 12:25:51 PM PDT 24
Peak memory 209952 kb
Host smart-5556c1af-14a6-4f17-bca6-89f5f3e9b992
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267833579 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.3267833579
Directory /workspace/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1655646406
Short name T111
Test name
Test status
Simulation time 31923096 ps
CPU time 0.62 seconds
Started Mar 14 12:25:48 PM PDT 24
Finished Mar 14 12:25:48 PM PDT 24
Peak memory 201616 kb
Host smart-d5e129dc-cc57-44cd-b85d-b2e7a451d358
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655646406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 11.sram_ctrl_csr_rw.1655646406
Directory /workspace/11.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.79273753
Short name T113
Test name
Test status
Simulation time 1519387734 ps
CPU time 3.04 seconds
Started Mar 14 12:25:54 PM PDT 24
Finished Mar 14 12:25:57 PM PDT 24
Peak memory 202100 kb
Host smart-e8af8e89-1b6c-4670-8c92-b4797cdf509f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79273753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base
_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.79273753
Directory /workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2101838741
Short name T122
Test name
Test status
Simulation time 13360425 ps
CPU time 0.69 seconds
Started Mar 14 12:25:47 PM PDT 24
Finished Mar 14 12:25:48 PM PDT 24
Peak memory 201652 kb
Host smart-e451422d-6c8b-42ef-aa9b-11ddd79eeef4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101838741 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.2101838741
Directory /workspace/11.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.683012110
Short name T51
Test name
Test status
Simulation time 88555149 ps
CPU time 3.02 seconds
Started Mar 14 12:25:46 PM PDT 24
Finished Mar 14 12:25:49 PM PDT 24
Peak memory 202028 kb
Host smart-518f5cfa-0a8f-4462-83b5-18f619a0d9fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683012110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
11.sram_ctrl_tl_errors.683012110
Directory /workspace/11.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.482775863
Short name T96
Test name
Test status
Simulation time 375646486 ps
CPU time 1.41 seconds
Started Mar 14 12:26:03 PM PDT 24
Finished Mar 14 12:26:04 PM PDT 24
Peak memory 202024 kb
Host smart-2369d646-551f-40ef-b049-fb03adfc7a05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482775863 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 11.sram_ctrl_tl_intg_err.482775863
Directory /workspace/11.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1053215275
Short name T106
Test name
Test status
Simulation time 21231575 ps
CPU time 0.63 seconds
Started Mar 14 12:26:44 PM PDT 24
Finished Mar 14 12:26:45 PM PDT 24
Peak memory 201428 kb
Host smart-32a05858-9a70-4516-b1be-0fdc68d259a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053215275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 12.sram_ctrl_csr_rw.1053215275
Directory /workspace/12.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2551702640
Short name T41
Test name
Test status
Simulation time 1695609157 ps
CPU time 3.17 seconds
Started Mar 14 12:25:40 PM PDT 24
Finished Mar 14 12:25:44 PM PDT 24
Peak memory 202008 kb
Host smart-93580970-8302-437d-9c1f-5b8b26672579
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551702640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.2551702640
Directory /workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2751532014
Short name T99
Test name
Test status
Simulation time 48558318 ps
CPU time 0.79 seconds
Started Mar 14 12:27:04 PM PDT 24
Finished Mar 14 12:27:05 PM PDT 24
Peak memory 201716 kb
Host smart-f3daa333-47c8-4c1a-a649-4c8d7621fdab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751532014 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.2751532014
Directory /workspace/12.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3527679128
Short name T16
Test name
Test status
Simulation time 67415164 ps
CPU time 2.32 seconds
Started Mar 14 12:27:02 PM PDT 24
Finished Mar 14 12:27:05 PM PDT 24
Peak memory 202016 kb
Host smart-1f4f3144-584f-4eb6-8201-57eb88e5982c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527679128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.sram_ctrl_tl_errors.3527679128
Directory /workspace/12.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2028906089
Short name T132
Test name
Test status
Simulation time 69960663 ps
CPU time 1.24 seconds
Started Mar 14 12:26:46 PM PDT 24
Finished Mar 14 12:26:48 PM PDT 24
Peak memory 201532 kb
Host smart-dc40c2e9-df53-4d0a-bc49-da04afb230a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028906089 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.2028906089
Directory /workspace/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3982162238
Short name T74
Test name
Test status
Simulation time 20032807 ps
CPU time 0.61 seconds
Started Mar 14 12:26:45 PM PDT 24
Finished Mar 14 12:26:46 PM PDT 24
Peak memory 201584 kb
Host smart-eebe2a86-6a7c-4647-b799-a58be68e0d00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982162238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.sram_ctrl_csr_rw.3982162238
Directory /workspace/13.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2912495771
Short name T42
Test name
Test status
Simulation time 734855617 ps
CPU time 2.14 seconds
Started Mar 14 12:25:58 PM PDT 24
Finished Mar 14 12:26:00 PM PDT 24
Peak memory 201792 kb
Host smart-7dce804d-404a-4e52-b998-95c788acfebb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912495771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.2912495771
Directory /workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.288148147
Short name T109
Test name
Test status
Simulation time 20333181 ps
CPU time 0.73 seconds
Started Mar 14 12:26:44 PM PDT 24
Finished Mar 14 12:26:45 PM PDT 24
Peak memory 200440 kb
Host smart-17c8f994-4584-4eb6-a4d8-00a3efda923d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288148147 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.288148147
Directory /workspace/13.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2799317885
Short name T91
Test name
Test status
Simulation time 391311375 ps
CPU time 3.71 seconds
Started Mar 14 12:26:46 PM PDT 24
Finished Mar 14 12:26:50 PM PDT 24
Peak memory 201928 kb
Host smart-021aab99-fa91-4c86-a7ca-1453fbbacabe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799317885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.sram_ctrl_tl_errors.2799317885
Directory /workspace/13.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2674122793
Short name T84
Test name
Test status
Simulation time 106141976 ps
CPU time 1.93 seconds
Started Mar 14 12:26:02 PM PDT 24
Finished Mar 14 12:26:04 PM PDT 24
Peak memory 211216 kb
Host smart-cab46ba1-e198-434f-bda5-86f6d68ef1de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674122793 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.2674122793
Directory /workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.75075179
Short name T98
Test name
Test status
Simulation time 51209964 ps
CPU time 0.64 seconds
Started Mar 14 12:25:41 PM PDT 24
Finished Mar 14 12:25:42 PM PDT 24
Peak memory 201712 kb
Host smart-294b5db3-3f8c-4120-bb44-e463ccc05dc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75075179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.sram_ctrl_csr_rw.75075179
Directory /workspace/14.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2315869052
Short name T28
Test name
Test status
Simulation time 454797517 ps
CPU time 2.77 seconds
Started Mar 14 12:25:58 PM PDT 24
Finished Mar 14 12:26:01 PM PDT 24
Peak memory 202180 kb
Host smart-e4d27a9f-faae-47ef-b451-7340fb44d93b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315869052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.2315869052
Directory /workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1903478220
Short name T103
Test name
Test status
Simulation time 81936081 ps
CPU time 0.7 seconds
Started Mar 14 12:26:09 PM PDT 24
Finished Mar 14 12:26:10 PM PDT 24
Peak memory 201740 kb
Host smart-a491afd3-7ff1-402c-9b1b-3a15386f86ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903478220 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.1903478220
Directory /workspace/14.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.4069515124
Short name T112
Test name
Test status
Simulation time 127500645 ps
CPU time 4.57 seconds
Started Mar 14 12:25:45 PM PDT 24
Finished Mar 14 12:25:49 PM PDT 24
Peak memory 201980 kb
Host smart-9b6acf7e-51d3-4956-97b2-4c25afe01492
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069515124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 14.sram_ctrl_tl_errors.4069515124
Directory /workspace/14.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3366144130
Short name T55
Test name
Test status
Simulation time 331783536 ps
CPU time 2.1 seconds
Started Mar 14 12:25:48 PM PDT 24
Finished Mar 14 12:25:50 PM PDT 24
Peak memory 201968 kb
Host smart-94b7fdfb-ba10-43b7-80d6-36cdd65eca1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366144130 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 14.sram_ctrl_tl_intg_err.3366144130
Directory /workspace/14.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3208613251
Short name T19
Test name
Test status
Simulation time 43862105 ps
CPU time 1.87 seconds
Started Mar 14 12:25:35 PM PDT 24
Finished Mar 14 12:25:37 PM PDT 24
Peak memory 210156 kb
Host smart-dc2e30c8-63f0-4139-9b42-1d01e5ac712b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208613251 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.3208613251
Directory /workspace/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3578774099
Short name T37
Test name
Test status
Simulation time 10974675 ps
CPU time 0.64 seconds
Started Mar 14 12:26:03 PM PDT 24
Finished Mar 14 12:26:04 PM PDT 24
Peak memory 201716 kb
Host smart-8d633ac0-2920-4cc6-b541-bc82706e53ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578774099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 15.sram_ctrl_csr_rw.3578774099
Directory /workspace/15.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.588380416
Short name T6
Test name
Test status
Simulation time 264953989 ps
CPU time 1.93 seconds
Started Mar 14 12:25:32 PM PDT 24
Finished Mar 14 12:25:34 PM PDT 24
Peak memory 201876 kb
Host smart-5b81a4d2-55d0-4811-bd69-4b2711c3b99d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588380416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.588380416
Directory /workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3998900469
Short name T67
Test name
Test status
Simulation time 52840925 ps
CPU time 0.72 seconds
Started Mar 14 12:25:40 PM PDT 24
Finished Mar 14 12:25:41 PM PDT 24
Peak memory 201724 kb
Host smart-4cef8684-a533-4644-bf5e-ecb357516e88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998900469 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.3998900469
Directory /workspace/15.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3121696993
Short name T101
Test name
Test status
Simulation time 58828953 ps
CPU time 2.09 seconds
Started Mar 14 12:26:01 PM PDT 24
Finished Mar 14 12:26:04 PM PDT 24
Peak memory 201964 kb
Host smart-c762380e-c397-45ae-b7e2-3e64d61fc095
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121696993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.sram_ctrl_tl_errors.3121696993
Directory /workspace/15.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2825860509
Short name T61
Test name
Test status
Simulation time 694662331 ps
CPU time 2.23 seconds
Started Mar 14 12:25:53 PM PDT 24
Finished Mar 14 12:25:56 PM PDT 24
Peak memory 202032 kb
Host smart-b5733877-90ef-4f3f-9263-10574b6356f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825860509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 15.sram_ctrl_tl_intg_err.2825860509
Directory /workspace/15.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2144099645
Short name T18
Test name
Test status
Simulation time 36230452 ps
CPU time 2.35 seconds
Started Mar 14 12:25:58 PM PDT 24
Finished Mar 14 12:26:01 PM PDT 24
Peak memory 211148 kb
Host smart-023bb321-d2d0-4202-9553-c0ab7acc35f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144099645 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.2144099645
Directory /workspace/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.317548602
Short name T97
Test name
Test status
Simulation time 11810482 ps
CPU time 0.64 seconds
Started Mar 14 12:25:58 PM PDT 24
Finished Mar 14 12:25:59 PM PDT 24
Peak memory 201416 kb
Host smart-3cba49ab-c2c8-452d-8d77-ef3f5366d94d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317548602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 16.sram_ctrl_csr_rw.317548602
Directory /workspace/16.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3537298355
Short name T38
Test name
Test status
Simulation time 880538478 ps
CPU time 3.25 seconds
Started Mar 14 12:27:03 PM PDT 24
Finished Mar 14 12:27:06 PM PDT 24
Peak memory 202040 kb
Host smart-b2a761a6-bf22-4b71-bae8-d31321997dce
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537298355 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.3537298355
Directory /workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3318006349
Short name T73
Test name
Test status
Simulation time 55246212 ps
CPU time 0.75 seconds
Started Mar 14 12:27:05 PM PDT 24
Finished Mar 14 12:27:06 PM PDT 24
Peak memory 201720 kb
Host smart-4463256c-db7c-4578-9c33-fc4ef70ecbce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318006349 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.3318006349
Directory /workspace/16.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1886771585
Short name T131
Test name
Test status
Simulation time 293392498 ps
CPU time 2.34 seconds
Started Mar 14 12:25:58 PM PDT 24
Finished Mar 14 12:26:00 PM PDT 24
Peak memory 201892 kb
Host smart-f0c70b41-dcd0-4e26-9382-6a1600a7161f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886771585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.sram_ctrl_tl_errors.1886771585
Directory /workspace/16.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1785677281
Short name T54
Test name
Test status
Simulation time 710475114 ps
CPU time 2.26 seconds
Started Mar 14 12:25:39 PM PDT 24
Finished Mar 14 12:25:41 PM PDT 24
Peak memory 210116 kb
Host smart-cbe30192-9813-4fd1-acb8-770b43755c59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785677281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 16.sram_ctrl_tl_intg_err.1785677281
Directory /workspace/16.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3760122374
Short name T75
Test name
Test status
Simulation time 57950942 ps
CPU time 1.08 seconds
Started Mar 14 12:26:05 PM PDT 24
Finished Mar 14 12:26:06 PM PDT 24
Peak memory 209972 kb
Host smart-def47792-62b6-4051-9e7f-8356eb7dce79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760122374 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.3760122374
Directory /workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1475964080
Short name T110
Test name
Test status
Simulation time 37788343 ps
CPU time 0.62 seconds
Started Mar 14 12:25:54 PM PDT 24
Finished Mar 14 12:25:55 PM PDT 24
Peak memory 201744 kb
Host smart-56a22b64-7f58-4497-9f91-63963f662663
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475964080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 17.sram_ctrl_csr_rw.1475964080
Directory /workspace/17.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.4061317678
Short name T44
Test name
Test status
Simulation time 2265588630 ps
CPU time 2.49 seconds
Started Mar 14 12:26:02 PM PDT 24
Finished Mar 14 12:26:05 PM PDT 24
Peak memory 201908 kb
Host smart-564e8087-65b3-43fd-84b7-662e05a6d77d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061317678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.4061317678
Directory /workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3658246992
Short name T100
Test name
Test status
Simulation time 22194039 ps
CPU time 0.77 seconds
Started Mar 14 12:25:55 PM PDT 24
Finished Mar 14 12:25:56 PM PDT 24
Peak memory 201768 kb
Host smart-cc17d0e5-1691-4da9-8ff3-d16b2c28910f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658246992 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.3658246992
Directory /workspace/17.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.4113300151
Short name T80
Test name
Test status
Simulation time 582535755 ps
CPU time 4.31 seconds
Started Mar 14 12:25:53 PM PDT 24
Finished Mar 14 12:25:58 PM PDT 24
Peak memory 202032 kb
Host smart-d7b8e4d9-cee5-4f9b-96f7-1705a307429e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113300151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.sram_ctrl_tl_errors.4113300151
Directory /workspace/17.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.69404808
Short name T59
Test name
Test status
Simulation time 174849014 ps
CPU time 2.08 seconds
Started Mar 14 12:26:03 PM PDT 24
Finished Mar 14 12:26:06 PM PDT 24
Peak memory 201948 kb
Host smart-2e2eea2b-1997-48d8-9a5e-a3987ac752d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69404808 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_te
st +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.sram_ctrl_tl_intg_err.69404808
Directory /workspace/17.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1452512090
Short name T124
Test name
Test status
Simulation time 31630201 ps
CPU time 0.98 seconds
Started Mar 14 12:25:58 PM PDT 24
Finished Mar 14 12:25:59 PM PDT 24
Peak memory 209964 kb
Host smart-63a84a1c-7d5c-4d46-b397-020e0b909192
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452512090 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.1452512090
Directory /workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.4206225689
Short name T116
Test name
Test status
Simulation time 27089168 ps
CPU time 0.64 seconds
Started Mar 14 12:25:50 PM PDT 24
Finished Mar 14 12:25:50 PM PDT 24
Peak memory 201640 kb
Host smart-f4446516-1414-40be-926b-b4d19f4a4f84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206225689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 18.sram_ctrl_csr_rw.4206225689
Directory /workspace/18.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2729825785
Short name T27
Test name
Test status
Simulation time 1589698263 ps
CPU time 3.02 seconds
Started Mar 14 12:26:36 PM PDT 24
Finished Mar 14 12:26:41 PM PDT 24
Peak memory 200968 kb
Host smart-2f43015a-6efd-4c05-b1ff-e9a22a1db292
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729825785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.2729825785
Directory /workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2675399865
Short name T3
Test name
Test status
Simulation time 110928475 ps
CPU time 0.76 seconds
Started Mar 14 12:26:01 PM PDT 24
Finished Mar 14 12:26:02 PM PDT 24
Peak memory 201776 kb
Host smart-986303e4-e552-439e-9a84-8d0f61532a11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675399865 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.2675399865
Directory /workspace/18.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1613540491
Short name T31
Test name
Test status
Simulation time 358343600 ps
CPU time 2.41 seconds
Started Mar 14 12:26:02 PM PDT 24
Finished Mar 14 12:26:04 PM PDT 24
Peak memory 201984 kb
Host smart-91720558-a61a-4e71-b3fb-1ae5d46a9cbb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613540491 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.sram_ctrl_tl_errors.1613540491
Directory /workspace/18.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2789949437
Short name T57
Test name
Test status
Simulation time 744202823 ps
CPU time 2.21 seconds
Started Mar 14 12:25:55 PM PDT 24
Finished Mar 14 12:25:57 PM PDT 24
Peak memory 201996 kb
Host smart-a7958c65-43de-4b00-a574-001cc8c22099
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789949437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 18.sram_ctrl_tl_intg_err.2789949437
Directory /workspace/18.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2324057405
Short name T36
Test name
Test status
Simulation time 20830188 ps
CPU time 0.65 seconds
Started Mar 14 12:26:13 PM PDT 24
Finished Mar 14 12:26:14 PM PDT 24
Peak memory 201708 kb
Host smart-e1550299-023f-4965-8ff3-f0f7d8ddf91d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324057405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 19.sram_ctrl_csr_rw.2324057405
Directory /workspace/19.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3949403399
Short name T23
Test name
Test status
Simulation time 776370267 ps
CPU time 2.94 seconds
Started Mar 14 12:25:56 PM PDT 24
Finished Mar 14 12:25:59 PM PDT 24
Peak memory 202072 kb
Host smart-cfce725f-3efa-479f-ba5e-de19d8b4b492
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949403399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.3949403399
Directory /workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3579522903
Short name T11
Test name
Test status
Simulation time 20943302 ps
CPU time 0.67 seconds
Started Mar 14 12:25:59 PM PDT 24
Finished Mar 14 12:26:00 PM PDT 24
Peak memory 201688 kb
Host smart-4c17ae54-ea60-4036-85b5-3e5f5effe48b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579522903 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.3579522903
Directory /workspace/19.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.854724078
Short name T128
Test name
Test status
Simulation time 318882136 ps
CPU time 2.27 seconds
Started Mar 14 12:25:57 PM PDT 24
Finished Mar 14 12:26:00 PM PDT 24
Peak memory 201944 kb
Host smart-b40ee47f-e071-418d-ae7d-e07ed28c51f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854724078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 19.sram_ctrl_tl_intg_err.854724078
Directory /workspace/19.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3269263688
Short name T13
Test name
Test status
Simulation time 53577839 ps
CPU time 0.67 seconds
Started Mar 14 12:27:02 PM PDT 24
Finished Mar 14 12:27:02 PM PDT 24
Peak memory 201624 kb
Host smart-b6dba028-6782-4e21-afbe-22ae8f5f6df9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269263688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_aliasing.3269263688
Directory /workspace/2.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1435837295
Short name T65
Test name
Test status
Simulation time 466910182 ps
CPU time 2.08 seconds
Started Mar 14 12:26:00 PM PDT 24
Finished Mar 14 12:26:02 PM PDT 24
Peak memory 201952 kb
Host smart-48ae1b95-81d8-42f4-9661-84f028d8b99b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435837295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_bit_bash.1435837295
Directory /workspace/2.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2913428404
Short name T49
Test name
Test status
Simulation time 16948212 ps
CPU time 0.66 seconds
Started Mar 14 12:25:39 PM PDT 24
Finished Mar 14 12:25:45 PM PDT 24
Peak memory 201692 kb
Host smart-7600e7ba-b46e-4a24-b802-e8d556ed2cdb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913428404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_hw_reset.2913428404
Directory /workspace/2.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1005983418
Short name T85
Test name
Test status
Simulation time 101080841 ps
CPU time 0.95 seconds
Started Mar 14 12:25:54 PM PDT 24
Finished Mar 14 12:25:55 PM PDT 24
Peak memory 209984 kb
Host smart-4e435c3d-3729-4ca4-9fe8-035d184e6cd5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005983418 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.1005983418
Directory /workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.288454098
Short name T92
Test name
Test status
Simulation time 37813086 ps
CPU time 0.64 seconds
Started Mar 14 12:26:05 PM PDT 24
Finished Mar 14 12:26:11 PM PDT 24
Peak memory 201716 kb
Host smart-08f5061f-8a4b-47eb-98a4-c086e014b52e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288454098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.sram_ctrl_csr_rw.288454098
Directory /workspace/2.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2832051690
Short name T25
Test name
Test status
Simulation time 842285580 ps
CPU time 1.98 seconds
Started Mar 14 12:25:36 PM PDT 24
Finished Mar 14 12:25:38 PM PDT 24
Peak memory 201852 kb
Host smart-f68a2276-4cf2-4b46-93e6-fc0052149a14
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832051690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.2832051690
Directory /workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1868584946
Short name T81
Test name
Test status
Simulation time 20441746 ps
CPU time 0.67 seconds
Started Mar 14 12:27:03 PM PDT 24
Finished Mar 14 12:27:03 PM PDT 24
Peak memory 201740 kb
Host smart-187db3c0-4ddf-4ead-b0d6-6e1428929b34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868584946 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.1868584946
Directory /workspace/2.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3683221296
Short name T123
Test name
Test status
Simulation time 70957535 ps
CPU time 2.11 seconds
Started Mar 14 12:26:59 PM PDT 24
Finished Mar 14 12:27:01 PM PDT 24
Peak memory 201940 kb
Host smart-5bbe847b-0710-4995-b2c8-2ba6bf3b7b77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683221296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.sram_ctrl_tl_errors.3683221296
Directory /workspace/2.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3635696771
Short name T56
Test name
Test status
Simulation time 314933320 ps
CPU time 1.28 seconds
Started Mar 14 12:26:06 PM PDT 24
Finished Mar 14 12:26:13 PM PDT 24
Peak memory 201976 kb
Host smart-60f81e20-0fff-4659-9722-16c5d8ad611b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635696771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 2.sram_ctrl_tl_intg_err.3635696771
Directory /workspace/2.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.767947896
Short name T115
Test name
Test status
Simulation time 94584918 ps
CPU time 0.67 seconds
Started Mar 14 12:27:02 PM PDT 24
Finished Mar 14 12:27:03 PM PDT 24
Peak memory 201704 kb
Host smart-85a5e192-dcc1-436f-abb8-bbf5703fadef
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767947896 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.sram_ctrl_csr_aliasing.767947896
Directory /workspace/3.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1158084504
Short name T46
Test name
Test status
Simulation time 433900099 ps
CPU time 2.05 seconds
Started Mar 14 12:25:51 PM PDT 24
Finished Mar 14 12:25:54 PM PDT 24
Peak memory 201876 kb
Host smart-57e649df-dcb5-4bbc-b0f7-830af0a346f0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158084504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_bit_bash.1158084504
Directory /workspace/3.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2863474021
Short name T108
Test name
Test status
Simulation time 120389492 ps
CPU time 0.61 seconds
Started Mar 14 12:27:05 PM PDT 24
Finished Mar 14 12:27:06 PM PDT 24
Peak memory 201704 kb
Host smart-959b0761-08c1-4360-a67e-21e9a22d068a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863474021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_hw_reset.2863474021
Directory /workspace/3.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.655130246
Short name T83
Test name
Test status
Simulation time 117936156 ps
CPU time 0.97 seconds
Started Mar 14 12:27:05 PM PDT 24
Finished Mar 14 12:27:07 PM PDT 24
Peak memory 209944 kb
Host smart-d407b765-9426-4672-b67f-ebaf25928d7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655130246 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.655130246
Directory /workspace/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1988464402
Short name T52
Test name
Test status
Simulation time 12361592 ps
CPU time 0.67 seconds
Started Mar 14 12:26:36 PM PDT 24
Finished Mar 14 12:26:38 PM PDT 24
Peak memory 200452 kb
Host smart-5bd4f113-817c-400a-8fc4-c7ae99c12d3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988464402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 3.sram_ctrl_csr_rw.1988464402
Directory /workspace/3.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1239523007
Short name T39
Test name
Test status
Simulation time 1806336318 ps
CPU time 1.81 seconds
Started Mar 14 12:25:40 PM PDT 24
Finished Mar 14 12:25:42 PM PDT 24
Peak memory 201852 kb
Host smart-888fa37c-504d-470e-87bc-585976b4f002
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239523007 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.1239523007
Directory /workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2782897208
Short name T87
Test name
Test status
Simulation time 124616445 ps
CPU time 0.8 seconds
Started Mar 14 12:26:02 PM PDT 24
Finished Mar 14 12:26:03 PM PDT 24
Peak memory 201676 kb
Host smart-41429f89-8e1d-42d7-a116-8d7efe05ca00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782897208 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.2782897208
Directory /workspace/3.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.4262335454
Short name T133
Test name
Test status
Simulation time 105814780 ps
CPU time 3.4 seconds
Started Mar 14 12:25:54 PM PDT 24
Finished Mar 14 12:25:58 PM PDT 24
Peak memory 201972 kb
Host smart-ee069c4c-22c5-474e-95bc-fe59152ce3fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262335454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.sram_ctrl_tl_errors.4262335454
Directory /workspace/3.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.165924987
Short name T60
Test name
Test status
Simulation time 327774900 ps
CPU time 2.24 seconds
Started Mar 14 12:26:02 PM PDT 24
Finished Mar 14 12:26:05 PM PDT 24
Peak memory 201948 kb
Host smart-4d495b43-c6d1-4005-9c86-50886c07c134
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165924987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 3.sram_ctrl_tl_intg_err.165924987
Directory /workspace/3.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1319206418
Short name T35
Test name
Test status
Simulation time 17693202 ps
CPU time 0.72 seconds
Started Mar 14 12:26:03 PM PDT 24
Finished Mar 14 12:26:04 PM PDT 24
Peak memory 201724 kb
Host smart-20b6bec1-7d22-427c-973a-c9608fade3ef
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319206418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_aliasing.1319206418
Directory /workspace/4.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.183611423
Short name T66
Test name
Test status
Simulation time 580209115 ps
CPU time 2.08 seconds
Started Mar 14 12:26:02 PM PDT 24
Finished Mar 14 12:26:05 PM PDT 24
Peak memory 202020 kb
Host smart-b8972c34-aff2-4f63-80fb-d0da7f90d499
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183611423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.sram_ctrl_csr_bit_bash.183611423
Directory /workspace/4.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3141662697
Short name T22
Test name
Test status
Simulation time 19384645 ps
CPU time 0.59 seconds
Started Mar 14 12:27:11 PM PDT 24
Finished Mar 14 12:27:11 PM PDT 24
Peak memory 201720 kb
Host smart-dee94832-4ba3-4e0d-b2ac-39a5721d52ff
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141662697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_hw_reset.3141662697
Directory /workspace/4.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.4106622679
Short name T71
Test name
Test status
Simulation time 100631714 ps
CPU time 0.91 seconds
Started Mar 14 12:25:58 PM PDT 24
Finished Mar 14 12:25:59 PM PDT 24
Peak memory 201700 kb
Host smart-3e664a99-ed87-4cf3-9cf5-af565fb9abe6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106622679 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.4106622679
Directory /workspace/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2192889468
Short name T68
Test name
Test status
Simulation time 15600357 ps
CPU time 0.67 seconds
Started Mar 14 12:25:47 PM PDT 24
Finished Mar 14 12:25:48 PM PDT 24
Peak memory 201752 kb
Host smart-42986492-dcee-4407-b24b-3abc0843be3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192889468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 4.sram_ctrl_csr_rw.2192889468
Directory /workspace/4.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.396662907
Short name T118
Test name
Test status
Simulation time 1521027662 ps
CPU time 2.88 seconds
Started Mar 14 12:26:02 PM PDT 24
Finished Mar 14 12:26:06 PM PDT 24
Peak memory 202100 kb
Host smart-082fcce3-fce0-442a-b6a1-20d693870e78
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396662907 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.396662907
Directory /workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2506003310
Short name T105
Test name
Test status
Simulation time 25432957 ps
CPU time 0.71 seconds
Started Mar 14 12:26:02 PM PDT 24
Finished Mar 14 12:26:03 PM PDT 24
Peak memory 201728 kb
Host smart-3d840268-0b79-468d-bec5-8965217b43be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506003310 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.2506003310
Directory /workspace/4.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3551840703
Short name T93
Test name
Test status
Simulation time 28050580 ps
CPU time 2.23 seconds
Started Mar 14 12:26:03 PM PDT 24
Finished Mar 14 12:26:05 PM PDT 24
Peak memory 201980 kb
Host smart-a796d0ca-5d63-45e7-94ec-6e18ffaad306
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551840703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.sram_ctrl_tl_errors.3551840703
Directory /workspace/4.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2219299924
Short name T102
Test name
Test status
Simulation time 329482025 ps
CPU time 1.45 seconds
Started Mar 14 12:26:02 PM PDT 24
Finished Mar 14 12:26:04 PM PDT 24
Peak memory 202040 kb
Host smart-ed2fac9d-1a6e-4526-a93a-b83f9add3d89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219299924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 4.sram_ctrl_tl_intg_err.2219299924
Directory /workspace/4.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3466106659
Short name T64
Test name
Test status
Simulation time 251031109 ps
CPU time 1.63 seconds
Started Mar 14 12:26:45 PM PDT 24
Finished Mar 14 12:26:47 PM PDT 24
Peak memory 210344 kb
Host smart-a4d4dce8-b309-4ca1-a0ac-26c77c0b80ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466106659 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.3466106659
Directory /workspace/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3423003564
Short name T34
Test name
Test status
Simulation time 41504759 ps
CPU time 0.64 seconds
Started Mar 14 12:26:54 PM PDT 24
Finished Mar 14 12:26:55 PM PDT 24
Peak memory 201700 kb
Host smart-fc7a041c-dd85-4b1d-b377-cd530237eb9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423003564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 5.sram_ctrl_csr_rw.3423003564
Directory /workspace/5.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2094271258
Short name T15
Test name
Test status
Simulation time 1014981091 ps
CPU time 2.19 seconds
Started Mar 14 12:26:02 PM PDT 24
Finished Mar 14 12:26:04 PM PDT 24
Peak memory 201888 kb
Host smart-e38796de-60ea-41f7-9000-7d8961a59605
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094271258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.2094271258
Directory /workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2934727418
Short name T120
Test name
Test status
Simulation time 40909839 ps
CPU time 0.74 seconds
Started Mar 14 12:26:46 PM PDT 24
Finished Mar 14 12:26:47 PM PDT 24
Peak memory 201400 kb
Host smart-2ec53a91-4ff6-4216-9491-1fb29f1a70f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934727418 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.2934727418
Directory /workspace/5.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3259746334
Short name T50
Test name
Test status
Simulation time 75119120 ps
CPU time 1.89 seconds
Started Mar 14 12:27:02 PM PDT 24
Finished Mar 14 12:27:04 PM PDT 24
Peak memory 202012 kb
Host smart-682128ec-c787-470f-ab60-ffa48e2c0170
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259746334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 5.sram_ctrl_tl_errors.3259746334
Directory /workspace/5.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1635446475
Short name T32
Test name
Test status
Simulation time 25036842 ps
CPU time 0.61 seconds
Started Mar 14 12:25:53 PM PDT 24
Finished Mar 14 12:25:54 PM PDT 24
Peak memory 200764 kb
Host smart-4564a2d5-2850-4555-804b-804e345fcf24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635446475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 6.sram_ctrl_csr_rw.1635446475
Directory /workspace/6.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3239908365
Short name T7
Test name
Test status
Simulation time 1936833282 ps
CPU time 3.11 seconds
Started Mar 14 12:26:01 PM PDT 24
Finished Mar 14 12:26:04 PM PDT 24
Peak memory 202060 kb
Host smart-a802017e-e9bf-4709-9f36-4d7b0822f055
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239908365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.3239908365
Directory /workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.883835534
Short name T21
Test name
Test status
Simulation time 77495460 ps
CPU time 0.78 seconds
Started Mar 14 12:26:02 PM PDT 24
Finished Mar 14 12:26:03 PM PDT 24
Peak memory 201720 kb
Host smart-3e915ca3-e8b8-43bb-a95a-3efed48df59a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883835534 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.883835534
Directory /workspace/6.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3728149679
Short name T86
Test name
Test status
Simulation time 142009410 ps
CPU time 4.18 seconds
Started Mar 14 12:25:46 PM PDT 24
Finished Mar 14 12:25:50 PM PDT 24
Peak memory 201960 kb
Host smart-7aaf6529-5ec8-4347-9744-ec9cb1d4001a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728149679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.sram_ctrl_tl_errors.3728149679
Directory /workspace/6.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2314744875
Short name T63
Test name
Test status
Simulation time 1064411094 ps
CPU time 2.28 seconds
Started Mar 14 12:25:59 PM PDT 24
Finished Mar 14 12:26:01 PM PDT 24
Peak memory 201972 kb
Host smart-a8bd7077-004d-4cc5-a4cd-6e10f8a4f666
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314744875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 6.sram_ctrl_tl_intg_err.2314744875
Directory /workspace/6.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.4170279653
Short name T90
Test name
Test status
Simulation time 37688294 ps
CPU time 2.73 seconds
Started Mar 14 12:25:58 PM PDT 24
Finished Mar 14 12:26:01 PM PDT 24
Peak memory 210100 kb
Host smart-32999673-8601-414f-9a01-592b0087911f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170279653 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.4170279653
Directory /workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.625742700
Short name T40
Test name
Test status
Simulation time 18960092 ps
CPU time 0.64 seconds
Started Mar 14 12:26:01 PM PDT 24
Finished Mar 14 12:26:02 PM PDT 24
Peak memory 201640 kb
Host smart-39b60e67-37cd-4704-9f40-b426a81e4840
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625742700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 7.sram_ctrl_csr_rw.625742700
Directory /workspace/7.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1933839215
Short name T125
Test name
Test status
Simulation time 21965265 ps
CPU time 0.72 seconds
Started Mar 14 12:26:02 PM PDT 24
Finished Mar 14 12:26:03 PM PDT 24
Peak memory 201712 kb
Host smart-3be13244-ed37-4ebd-86b5-fd3b602aa69e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933839215 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.1933839215
Directory /workspace/7.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.4013423754
Short name T119
Test name
Test status
Simulation time 164581250 ps
CPU time 1.36 seconds
Started Mar 14 12:25:57 PM PDT 24
Finished Mar 14 12:25:59 PM PDT 24
Peak memory 201912 kb
Host smart-e9c1f302-83ea-4743-9f31-ce37a67270e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013423754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 7.sram_ctrl_tl_intg_err.4013423754
Directory /workspace/7.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3596000007
Short name T14
Test name
Test status
Simulation time 134998423 ps
CPU time 1.61 seconds
Started Mar 14 12:25:51 PM PDT 24
Finished Mar 14 12:25:53 PM PDT 24
Peak memory 210176 kb
Host smart-094f92d4-e51c-4ef9-b4e4-47d889bef696
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596000007 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.3596000007
Directory /workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3033084808
Short name T5
Test name
Test status
Simulation time 11898858 ps
CPU time 0.65 seconds
Started Mar 14 12:25:58 PM PDT 24
Finished Mar 14 12:25:59 PM PDT 24
Peak memory 201572 kb
Host smart-c690573f-250c-41ff-8183-834a32a79f82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033084808 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 8.sram_ctrl_csr_rw.3033084808
Directory /workspace/8.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3322173670
Short name T45
Test name
Test status
Simulation time 219390085 ps
CPU time 1.85 seconds
Started Mar 14 12:25:45 PM PDT 24
Finished Mar 14 12:25:47 PM PDT 24
Peak memory 201836 kb
Host smart-dc9e1608-b34d-4967-96be-e446c671fe1c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322173670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.3322173670
Directory /workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3917876388
Short name T129
Test name
Test status
Simulation time 32636159 ps
CPU time 0.72 seconds
Started Mar 14 12:27:04 PM PDT 24
Finished Mar 14 12:27:05 PM PDT 24
Peak memory 201724 kb
Host smart-a378bb39-278e-4961-a7c7-521dcdd28268
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917876388 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.3917876388
Directory /workspace/8.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2946181313
Short name T95
Test name
Test status
Simulation time 44832693 ps
CPU time 2.08 seconds
Started Mar 14 12:25:58 PM PDT 24
Finished Mar 14 12:26:01 PM PDT 24
Peak memory 201888 kb
Host smart-c6d1e885-6406-479d-958c-4e249ab53177
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946181313 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 8.sram_ctrl_tl_errors.2946181313
Directory /workspace/8.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3310278816
Short name T53
Test name
Test status
Simulation time 379561777 ps
CPU time 1.5 seconds
Started Mar 14 12:25:58 PM PDT 24
Finished Mar 14 12:26:00 PM PDT 24
Peak memory 201924 kb
Host smart-48a426db-f78f-4bf9-8cf3-29a675bd166b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310278816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 8.sram_ctrl_tl_intg_err.3310278816
Directory /workspace/8.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.206655123
Short name T78
Test name
Test status
Simulation time 101164849 ps
CPU time 0.93 seconds
Started Mar 14 12:27:03 PM PDT 24
Finished Mar 14 12:27:04 PM PDT 24
Peak memory 201744 kb
Host smart-e0bfa578-8808-445f-92da-6c732d200f94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206655123 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.206655123
Directory /workspace/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.797307953
Short name T30
Test name
Test status
Simulation time 24821749 ps
CPU time 0.63 seconds
Started Mar 14 12:25:54 PM PDT 24
Finished Mar 14 12:25:55 PM PDT 24
Peak memory 201668 kb
Host smart-ffa1d09b-d46c-4ef1-808b-647148cb73d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797307953 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 9.sram_ctrl_csr_rw.797307953
Directory /workspace/9.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.203455799
Short name T26
Test name
Test status
Simulation time 367377802 ps
CPU time 1.81 seconds
Started Mar 14 12:26:05 PM PDT 24
Finished Mar 14 12:26:12 PM PDT 24
Peak memory 201872 kb
Host smart-968689f6-cd62-4836-b01a-039adb0d6f98
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203455799 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.203455799
Directory /workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1429815757
Short name T94
Test name
Test status
Simulation time 21869663 ps
CPU time 0.69 seconds
Started Mar 14 12:26:02 PM PDT 24
Finished Mar 14 12:26:03 PM PDT 24
Peak memory 201724 kb
Host smart-04d3b461-5867-43c8-878e-447fbb653679
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429815757 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.1429815757
Directory /workspace/9.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1875532479
Short name T82
Test name
Test status
Simulation time 140056877 ps
CPU time 2.55 seconds
Started Mar 14 12:27:05 PM PDT 24
Finished Mar 14 12:27:08 PM PDT 24
Peak memory 202016 kb
Host smart-fe6bdadb-4ebd-4b8c-b6a0-35a6b739ba06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875532479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 9.sram_ctrl_tl_errors.1875532479
Directory /workspace/9.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3362111504
Short name T107
Test name
Test status
Simulation time 948606802 ps
CPU time 2.25 seconds
Started Mar 14 12:27:01 PM PDT 24
Finished Mar 14 12:27:04 PM PDT 24
Peak memory 201960 kb
Host smart-643b275c-1a86-4b88-bb8f-377ac622fe15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362111504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 9.sram_ctrl_tl_intg_err.3362111504
Directory /workspace/9.sram_ctrl_tl_intg_err/latest
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