Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14146772	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

58655267

1

T1

126310

T2

18432

T3

787

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36301544	1			T1	69435		T2	9216		T3	2125
values[0x0]	16838368	1			T1	33699		T2	4575		T3	757
values[0x1]	19662127	1			T1	35788		T2	4641		T3	1468

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7052178	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

65749861

1

T1

132624

T2

18432

T3

2560

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	293821	1			T2	65		T3	18		T4	985
valid_sources[0x01]	366467	1			T2	82		T3	13		T4	934
valid_sources[0x02]	266019	1			T2	71		T3	14		T4	849
valid_sources[0x03]	258546	1			T2	94		T3	26		T4	705
valid_sources[0x04]	292298	1			T2	63		T3	12		T4	923
valid_sources[0x05]	243306	1			T2	81		T3	17		T4	292
valid_sources[0x06]	238802	1			T2	74		T3	23		T4	1102
valid_sources[0x07]	264098	1			T2	63		T3	6		T4	728
valid_sources[0x08]	234624	1			T2	76		T3	19		T4	469
valid_sources[0x09]	282688	1			T2	65		T3	20		T4	661
valid_sources[0x0a]	305648	1			T2	66		T3	8		T4	1100
valid_sources[0x0b]	236520	1			T2	58		T3	15		T4	547
valid_sources[0x0c]	348981	1			T2	75		T3	11		T4	972
valid_sources[0x0d]	241213	1			T2	73		T3	6		T4	398
valid_sources[0x0e]	337968	1			T2	65		T3	19		T4	408
valid_sources[0x0f]	306220	1			T2	75		T3	12		T4	897
valid_sources[0x10]	255108	1			T2	78		T3	10		T4	1341
valid_sources[0x11]	333481	1			T2	89		T3	22		T4	531
valid_sources[0x12]	302244	1			T2	62		T3	6		T4	731
valid_sources[0x13]	256501	1			T2	61		T3	12		T4	763
valid_sources[0x14]	245228	1			T2	70		T3	11		T4	927
valid_sources[0x15]	338814	1			T2	64		T3	14		T4	434
valid_sources[0x16]	332527	1			T2	66		T3	13		T4	776
valid_sources[0x17]	289733	1			T2	70		T3	26		T4	1246
valid_sources[0x18]	314880	1			T2	85		T3	22		T4	702
valid_sources[0x19]	262591	1			T2	67		T3	26		T4	585
valid_sources[0x1a]	306596	1			T2	61		T3	21		T4	890
valid_sources[0x1b]	259382	1			T2	65		T3	9		T4	887
valid_sources[0x1c]	287254	1			T2	64		T3	15		T4	798
valid_sources[0x1d]	252135	1			T2	63		T3	19		T4	754
valid_sources[0x1e]	335597	1			T1	21493		T2	91		T3	19
valid_sources[0x1f]	254198	1			T2	72		T3	15		T4	213
valid_sources[0x20]	290733	1			T2	63		T3	20		T4	855
valid_sources[0x21]	253793	1			T2	78		T3	18		T4	385
valid_sources[0x22]	338141	1			T2	85		T3	11		T4	755
valid_sources[0x23]	355000	1			T2	81		T3	13		T4	894
valid_sources[0x24]	268115	1			T2	89		T3	14		T4	1017
valid_sources[0x25]	262750	1			T2	80		T3	29		T4	707
valid_sources[0x26]	350938	1			T2	87		T3	22		T4	975
valid_sources[0x27]	256289	1			T2	63		T3	18		T4	436
valid_sources[0x28]	246234	1			T2	73		T3	19		T4	705
valid_sources[0x29]	317129	1			T1	78		T2	82		T3	19
valid_sources[0x2a]	261336	1			T2	77		T3	19		T4	847
valid_sources[0x2b]	262983	1			T2	78		T3	9		T4	1037
valid_sources[0x2c]	288872	1			T2	81		T3	11		T4	1057
valid_sources[0x2d]	282171	1			T2	78		T3	26		T4	379
valid_sources[0x2e]	282369	1			T2	60		T3	10		T4	730
valid_sources[0x2f]	325478	1			T2	55		T3	18		T4	718
valid_sources[0x30]	263783	1			T2	76		T3	19		T4	1210
valid_sources[0x31]	291569	1			T2	71		T3	7		T4	824
valid_sources[0x32]	235782	1			T2	76		T3	19		T4	881
valid_sources[0x33]	353090	1			T1	355		T2	73		T3	18
valid_sources[0x34]	256913	1			T2	75		T3	13		T4	1009
valid_sources[0x35]	309670	1			T2	76		T3	22		T4	159
valid_sources[0x36]	264073	1			T2	70		T3	22		T4	643
valid_sources[0x37]	288364	1			T2	61		T3	29		T4	763
valid_sources[0x38]	294293	1			T2	77		T3	19		T4	677
valid_sources[0x39]	233174	1			T2	78		T3	19		T4	922
valid_sources[0x3a]	462547	1			T2	62		T3	14		T4	709
valid_sources[0x3b]	280204	1			T1	3790		T2	67		T3	9
valid_sources[0x3c]	279547	1			T2	69		T3	19		T4	1355
valid_sources[0x3d]	237403	1			T2	66		T3	7		T4	968
valid_sources[0x3e]	272424	1			T2	68		T3	16		T4	987
valid_sources[0x3f]	279444	1			T2	66		T3	20		T4	313
valid_sources[0x40]	278019	1			T2	81		T3	28		T4	582
valid_sources[0x41]	255647	1			T2	77		T3	20		T4	1105
valid_sources[0x42]	365009	1			T2	80		T3	8		T4	843
valid_sources[0x43]	269230	1			T2	71		T3	16		T4	839
valid_sources[0x44]	269760	1			T2	78		T3	20		T4	840
valid_sources[0x45]	245353	1			T2	70		T3	14		T4	488
valid_sources[0x46]	336147	1			T2	69		T3	13		T4	930
valid_sources[0x47]	337923	1			T2	80		T3	12		T4	560
valid_sources[0x48]	276802	1			T1	601		T2	69		T3	9
valid_sources[0x49]	351674	1			T2	73		T3	13		T4	305
valid_sources[0x4a]	285970	1			T2	76		T3	24		T4	772
valid_sources[0x4b]	247303	1			T2	67		T3	10		T4	965
valid_sources[0x4c]	290840	1			T2	79		T3	16		T4	489
valid_sources[0x4d]	312835	1			T1	19154		T2	80		T3	24
valid_sources[0x4e]	241494	1			T2	73		T3	11		T4	307
valid_sources[0x4f]	301110	1			T1	17315		T2	67		T3	21
valid_sources[0x50]	299368	1			T2	67		T3	21		T4	455
valid_sources[0x51]	272649	1			T2	81		T3	22		T4	309
valid_sources[0x52]	235829	1			T2	71		T3	20		T4	543
valid_sources[0x53]	293496	1			T2	78		T3	21		T4	601
valid_sources[0x54]	270452	1			T2	81		T3	21		T4	455
valid_sources[0x55]	312152	1			T2	78		T3	3		T4	830
valid_sources[0x56]	244894	1			T2	71		T3	20		T4	839
valid_sources[0x57]	232721	1			T2	60		T3	29		T4	1007
valid_sources[0x58]	256802	1			T2	72		T3	13		T4	1013
valid_sources[0x59]	255182	1			T2	71		T3	6		T4	499
valid_sources[0x5a]	279392	1			T2	85		T3	13		T4	742
valid_sources[0x5b]	282516	1			T2	64		T3	27		T4	340
valid_sources[0x5c]	323021	1			T1	12836		T2	76		T3	18
valid_sources[0x5d]	372770	1			T2	67		T3	17		T4	1259
valid_sources[0x5e]	267446	1			T1	20		T2	83		T3	19
valid_sources[0x5f]	273626	1			T2	64		T3	21		T4	759
valid_sources[0x60]	280388	1			T2	65		T3	22		T4	390
valid_sources[0x61]	258066	1			T2	76		T3	19		T4	497
valid_sources[0x62]	258902	1			T2	69		T3	23		T4	1377
valid_sources[0x63]	327328	1			T1	56		T2	77		T3	24
valid_sources[0x64]	241691	1			T2	80		T3	21		T4	832
valid_sources[0x65]	255292	1			T2	74		T3	26		T4	304
valid_sources[0x66]	335440	1			T2	82		T3	28		T4	758
valid_sources[0x67]	317902	1			T2	94		T3	22		T4	656
valid_sources[0x68]	323782	1			T2	71		T3	24		T4	541
valid_sources[0x69]	255269	1			T2	69		T3	18		T4	872
valid_sources[0x6a]	256404	1			T2	71		T3	5		T4	626
valid_sources[0x6b]	254863	1			T2	72		T3	11		T4	770
valid_sources[0x6c]	273524	1			T2	90		T3	14		T4	569
valid_sources[0x6d]	321243	1			T2	85		T3	15		T4	491
valid_sources[0x6e]	264050	1			T2	81		T3	23		T4	710
valid_sources[0x6f]	242759	1			T2	68		T3	11		T4	897
valid_sources[0x70]	254593	1			T2	72		T3	24		T4	675
valid_sources[0x71]	264570	1			T2	66		T3	12		T4	369
valid_sources[0x72]	271206	1			T2	57		T3	12		T4	813
valid_sources[0x73]	320414	1			T2	60		T3	18		T4	612
valid_sources[0x74]	369473	1			T2	71		T3	26		T4	747
valid_sources[0x75]	276059	1			T2	82		T3	16		T4	505
valid_sources[0x76]	294501	1			T2	71		T3	13		T4	1102
valid_sources[0x77]	336470	1			T2	59		T3	17		T4	575
valid_sources[0x78]	361231	1			T2	60		T3	12		T4	844
valid_sources[0x79]	342733	1			T2	63		T3	24		T4	745
valid_sources[0x7a]	274163	1			T2	69		T3	19		T4	1068
valid_sources[0x7b]	242828	1			T2	74		T3	12		T4	1273
valid_sources[0x7c]	318802	1			T2	74		T3	17		T4	513
valid_sources[0x7d]	253163	1			T2	78		T3	17		T4	487
valid_sources[0x7e]	248326	1			T2	83		T3	18		T4	440
valid_sources[0x7f]	258708	1			T2	75		T3	9		T4	355
valid_sources[0x80]	353737	1			T1	15		T2	72		T3	21

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29233995

1

T1

63114

T2

9216

T3

387

values[0x0]

all_enables

biggest_size

14713019

1

T1

31729

T2

4575

T3

192

values[0x1]

all_enables

biggest_size

14708253

1

T1

31467

T2

4641

T3

208

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32854	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

113001

1

T1

4

T2

1

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	43444	1			T7	22		T8	78		T31	8
values[0x0]	49864	1			T1	15		T2	8		T4	9
values[0x1]	52547	1			T1	12		T2	1		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25420	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

120435

1

T1

8

T2

1

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1072	1			T7	1		T29	22		T130	1
valid_sources[0x01]	389	1			T40	1		T27	6		T130	1
valid_sources[0x02]	387	1			T130	2		T43	19		T148	1
valid_sources[0x03]	551	1			T29	2		T131	2		T30	39
valid_sources[0x04]	344	1			T22	1		T139	2		T43	4
valid_sources[0x05]	314	1			T7	1		T29	2		T130	2
valid_sources[0x06]	354	1			T32	1		T7	2		T62	1
valid_sources[0x07]	496	1			T20	1		T28	3		T40	2
valid_sources[0x08]	541	1			T26	2		T134	5		T100	1
valid_sources[0x09]	689	1			T9	4		T21	3		T133	1
valid_sources[0x0a]	356	1			T19	1		T29	2		T51	1
valid_sources[0x0b]	686	1			T7	2		T29	3		T50	1
valid_sources[0x0c]	697	1			T1	1		T7	1		T50	1
valid_sources[0x0d]	941	1			T42	1		T149	107		T147	7
valid_sources[0x0e]	353	1			T7	2		T28	8		T135	1
valid_sources[0x0f]	826	1			T7	1		T34	1		T40	5
valid_sources[0x10]	413	1			T9	4		T130	3		T43	1
valid_sources[0x11]	967	1			T80	1		T100	4		T135	1
valid_sources[0x12]	461	1			T22	1		T133	1		T43	12
valid_sources[0x13]	530	1			T33	1		T7	1		T130	1
valid_sources[0x14]	787	1			T1	1		T18	1		T59	3
valid_sources[0x15]	364	1			T80	12		T135	2		T150	2
valid_sources[0x16]	405	1			T62	1		T40	5		T139	7
valid_sources[0x17]	414	1			T18	1		T40	8		T151	1
valid_sources[0x18]	442	1			T18	1		T62	2		T133	2
valid_sources[0x19]	595	1			T7	1		T29	2		T40	8
valid_sources[0x1a]	549	1			T11	1		T62	1		T110	2
valid_sources[0x1b]	792	1			T7	1		T29	135		T27	2
valid_sources[0x1c]	660	1			T73	1		T7	1		T29	2
valid_sources[0x1d]	640	1			T40	12		T152	1		T130	1
valid_sources[0x1e]	594	1			T28	1		T99	1		T133	1
valid_sources[0x1f]	522	1			T133	1		T130	2		T153	2
valid_sources[0x20]	426	1			T50	1		T28	1		T38	1
valid_sources[0x21]	881	1			T7	1		T29	67		T21	1
valid_sources[0x22]	504	1			T3	1		T7	3		T130	1
valid_sources[0x23]	544	1			T7	1		T27	3		T130	1
valid_sources[0x24]	761	1			T29	192		T27	10		T133	1
valid_sources[0x25]	898	1			T139	1		T154	1		T142	1
valid_sources[0x26]	531	1			T18	1		T29	2		T151	1
valid_sources[0x27]	663	1			T62	1		T133	1		T30	10
valid_sources[0x28]	410	1			T62	2		T29	1		T131	2
valid_sources[0x29]	551	1			T7	3		T29	100		T28	1
valid_sources[0x2a]	527	1			T1	3		T18	2		T7	2
valid_sources[0x2b]	481	1			T7	1		T62	1		T27	1
valid_sources[0x2c]	517	1			T18	4		T43	1		T148	1
valid_sources[0x2d]	425	1			T130	2		T30	48		T43	3
valid_sources[0x2e]	665	1			T18	4		T7	1		T29	1
valid_sources[0x2f]	522	1			T10	1		T29	96		T28	1
valid_sources[0x30]	445	1			T26	3		T27	2		T43	7
valid_sources[0x31]	491	1			T7	1		T133	2		T147	1
valid_sources[0x32]	574	1			T7	1		T15	1		T130	2
valid_sources[0x33]	744	1			T73	1		T7	1		T19	1
valid_sources[0x34]	429	1			T10	1		T7	1		T133	1
valid_sources[0x35]	567	1			T1	4		T7	1		T15	1
valid_sources[0x36]	555	1			T9	1		T42	5		T40	8
valid_sources[0x37]	653	1			T7	1		T29	126		T40	3
valid_sources[0x38]	379	1			T7	1		T29	1		T133	1
valid_sources[0x39]	558	1			T29	11		T40	1		T130	1
valid_sources[0x3a]	553	1			T19	1		T50	2		T26	85
valid_sources[0x3b]	512	1			T18	3		T29	2		T26	130
valid_sources[0x3c]	569	1			T7	5		T27	5		T131	2
valid_sources[0x3d]	404	1			T7	2		T29	5		T27	11
valid_sources[0x3e]	536	1			T73	1		T62	1		T29	1
valid_sources[0x3f]	501	1			T7	1		T30	1		T148	1
valid_sources[0x40]	483	1			T29	1		T28	1		T148	1
valid_sources[0x41]	473	1			T29	3		T148	2		T155	1
valid_sources[0x42]	404	1			T130	1		T139	4		T81	9
valid_sources[0x43]	550	1			T7	2		T62	1		T130	1
valid_sources[0x44]	934	1			T133	1		T139	1		T135	1
valid_sources[0x45]	475	1			T7	2		T61	1		T135	1
valid_sources[0x46]	437	1			T7	1		T19	1		T9	1
valid_sources[0x47]	433	1			T7	2		T42	11		T40	11
valid_sources[0x48]	503	1			T7	1		T28	10		T98	6
valid_sources[0x49]	589	1			T15	1		T29	2		T50	2
valid_sources[0x4a]	969	1			T7	1		T19	1		T29	3
valid_sources[0x4b]	518	1			T73	1		T15	1		T40	1
valid_sources[0x4c]	461	1			T135	1		T30	1		T46	4
valid_sources[0x4d]	348	1			T29	1		T130	1		T135	1
valid_sources[0x4e]	441	1			T29	3		T133	1		T80	5
valid_sources[0x4f]	982	1			T7	1		T19	1		T28	1
valid_sources[0x50]	574	1			T14	11		T26	43		T139	2
valid_sources[0x51]	508	1			T9	9		T29	3		T27	11
valid_sources[0x52]	279	1			T50	3		T156	1		T151	1
valid_sources[0x53]	502	1			T29	63		T56	1		T41	2
valid_sources[0x54]	453	1			T7	4		T62	1		T26	3
valid_sources[0x55]	514	1			T26	3		T40	17		T157	2
valid_sources[0x56]	700	1			T26	125		T99	1		T158	3
valid_sources[0x57]	736	1			T7	2		T29	364		T27	2
valid_sources[0x58]	554	1			T9	1		T131	2		T147	11
valid_sources[0x59]	760	1			T16	5		T7	1		T15	1
valid_sources[0x5a]	839	1			T26	115		T130	2		T135	2
valid_sources[0x5b]	365	1			T18	2		T130	1		T135	1
valid_sources[0x5c]	491	1			T7	1		T40	2		T133	1
valid_sources[0x5d]	549	1			T7	1		T130	1		T43	33
valid_sources[0x5e]	340	1			T139	2		T135	2		T148	1
valid_sources[0x5f]	691	1			T30	6		T148	1		T44	122
valid_sources[0x60]	362	1			T40	3		T159	1		T146	1
valid_sources[0x61]	661	1			T7	2		T27	8		T160	8
valid_sources[0x62]	382	1			T7	1		T40	7		T133	2
valid_sources[0x63]	757	1			T62	1		T161	1		T30	9
valid_sources[0x64]	290	1			T7	2		T133	1		T157	1
valid_sources[0x65]	347	1			T7	1		T19	1		T9	1
valid_sources[0x66]	408	1			T1	1		T19	1		T62	1
valid_sources[0x67]	427	1			T73	1		T7	1		T29	1
valid_sources[0x68]	1420	1			T7	2		T29	160		T26	399
valid_sources[0x69]	745	1			T7	1		T110	1		T132	1
valid_sources[0x6a]	335	1			T7	2		T57	4		T30	17
valid_sources[0x6b]	321	1			T62	2		T27	5		T130	1
valid_sources[0x6c]	593	1			T15	1		T62	2		T29	2
valid_sources[0x6d]	369	1			T73	1		T7	1		T60	1
valid_sources[0x6e]	549	1			T7	1		T52	2		T151	1
valid_sources[0x6f]	561	1			T9	1		T40	1		T151	1
valid_sources[0x70]	440	1			T7	1		T130	2		T43	10
valid_sources[0x71]	477	1			T133	2		T147	6		T158	3
valid_sources[0x72]	541	1			T151	2		T133	1		T45	127
valid_sources[0x73]	386	1			T29	4		T40	17		T130	1
valid_sources[0x74]	553	1			T2	9		T59	3		T29	4
valid_sources[0x75]	489	1			T7	1		T19	1		T9	1
valid_sources[0x76]	447	1			T18	2		T73	1		T29	6
valid_sources[0x77]	500	1			T43	1		T141	5		T142	1
valid_sources[0x78]	622	1			T28	3		T131	1		T135	1
valid_sources[0x79]	566	1			T73	1		T7	1		T19	1
valid_sources[0x7a]	606	1			T18	2		T7	1		T29	98
valid_sources[0x7b]	503	1			T1	2		T18	2		T151	1
valid_sources[0x7c]	671	1			T62	1		T29	3		T50	2
valid_sources[0x7d]	388	1			T7	2		T62	1		T40	4
valid_sources[0x7e]	636	1			T19	1		T42	19		T135	1
valid_sources[0x7f]	857	1			T9	5		T29	30		T21	1
valid_sources[0x80]	725	1			T18	1		T73	1		T7	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

31442

1

T7

9

T8

46

T31

4

values[0x0]

all_enables

biggest_size

42053

1

T1

4

T2

1

T4

4

values[0x1]

all_enables

biggest_size

39506

1

T3

1

T11

1

T12

1