Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13810691

1

T1

12612

T3

3563

T4

16860

full_word

53693231

1

T1

126310

T2

18432

T3

787

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	67503602	1			T1	138922		T2	18432		T3	4350
auto[TlIntgErrCmd]	111	1			T107	8		T108	6		T109	1
auto[TlIntgErrData]	108	1			T107	6		T108	3		T109	7
auto[TlIntgErrBoth]	101	1			T107	6		T108	1		T109	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30977503

1

T1

69435

T2

9216

T3

2125

auto[1]

36526419

1

T1

69487

T2

9216

T3

2225

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6613503	1			T1	6321		T3	1738		T4	8355
auto[TlIntgErrNone]	partial	auto[1]	7196884	1			T1	6291		T3	1825		T4	8505
auto[TlIntgErrNone]	full_word	auto[0]	24363862	1			T1	63114		T2	9216		T3	387
auto[TlIntgErrNone]	full_word	auto[1]	29329353	1			T1	63196		T2	9216		T3	400
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T107	4		T108	3		T118	4
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T107	4		T108	3		T109	1
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T120	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T124	1		T119	1		T123	1
auto[TlIntgErrData]	partial	auto[0]	45	1			T107	2		T108	2		T109	2
auto[TlIntgErrData]	partial	auto[1]	60	1			T107	4		T108	1		T109	5
auto[TlIntgErrData]	full_word	auto[0]	1	1			T123	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	2	1			T126	1		T127	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T107	1		T108	1		T109	1
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T107	5		T109	1		T118	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T124	1		T128	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T124	1		T119	1		T123	1