Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	729370	1			T3	558		T8	1131		T15	5282
auto[1]	10173527	1			T1	23604		T3	498		T4	50022
auto[2]	617753	1			T3	392		T8	740		T15	3412
auto[3]	10072432	1			T1	23494		T3	343		T4	50111

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14300354	1			T1	39001		T3	46		T4	82605
auto[1]	2023073	1			T1	3854		T3	248		T4	8317
auto[2]	2019622	1			T1	3888		T3	227		T4	8386
auto[3]	3250033	1			T1	355		T3	1270		T4	825

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8784832

1

T1

47058

T3

1790

T4

100033

auto[1]

12808250

1

T1

40

T3

1

T4

100

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	225131	1			T3	20		T8	948		T15	4383
auto[0]	auto[0]	auto[1]	23192	1			T3	75		T8	88		T15	429
auto[0]	auto[0]	auto[2]	23186	1			T3	95		T8	86		T15	422
auto[0]	auto[0]	auto[3]	7317	1			T3	367		T8	9		T15	45
auto[0]	auto[1]	auto[0]	3386028	1			T1	19522		T3	5		T4	41277
auto[0]	auto[1]	auto[1]	351709	1			T1	1916		T3	92		T4	4106
auto[0]	auto[1]	auto[2]	342819	1			T1	1965		T3	17		T4	4177
auto[0]	auto[1]	auto[3]	74582	1			T1	181		T3	384		T4	411
auto[0]	auto[2]	auto[0]	188464	1			T3	19		T8	574		T15	2573
auto[0]	auto[2]	auto[1]	19630	1			T3	74		T8	58		T15	296
auto[0]	auto[2]	auto[2]	19383	1			T3	49		T8	98		T15	495
auto[0]	auto[2]	auto[3]	5819	1			T3	250		T8	9		T15	44
auto[0]	auto[3]	auto[0]	3347788	1			T1	19447		T3	2		T4	41251
auto[0]	auto[3]	auto[1]	340654	1			T1	1932		T3	7		T4	4200
auto[0]	auto[3]	auto[2]	350968	1			T1	1921		T3	66		T4	4197
auto[0]	auto[3]	auto[3]	78162	1			T1	174		T3	268		T4	414
auto[1]	auto[0]	auto[0]	15012	1			T15	2		T42	1		T130	4
auto[1]	auto[0]	auto[1]	67071	1			T42	1		T139	1		T140	2
auto[1]	auto[0]	auto[2]	67276	1			T15	1		T31	1		T140	2
auto[1]	auto[0]	auto[3]	301185	1			T3	1		T141	1		T132	1
auto[1]	auto[1]	auto[0]	3562644	1			T1	16		T4	43		T10	7
auto[1]	auto[1]	auto[1]	608169	1			T1	4		T4	5		T11	14387
auto[1]	auto[1]	auto[2]	560970	1			T4	3		T11	14363		T14	1
auto[1]	auto[1]	auto[3]	1286606	1			T11	64316		T12	1		T6	1
auto[1]	auto[2]	auto[0]	13584	1			T8	1		T15	4		T31	3
auto[1]	auto[2]	auto[1]	59957	1			T141	1		T142	3		T143	3
auto[1]	auto[2]	auto[2]	56562	1			T132	1		T143	1		T144	1
auto[1]	auto[2]	auto[3]	254354	1			T145	2		T146	1		T142	1
auto[1]	auto[3]	auto[0]	3561703	1			T1	16		T4	34		T10	6
auto[1]	auto[3]	auto[1]	552691	1			T1	2		T4	6		T11	14310
auto[1]	auto[3]	auto[2]	598458	1			T1	2		T4	9		T11	14363
auto[1]	auto[3]	auto[3]	1242008	1			T11	63915		T14	1		T6	1