Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.26	100.00	94.62	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	315086547	105205	0	0
ctrl_regwen_rd_A	315086547	5998	0	0
exec_rd_A	315086547	5446	0	0
exec_regwen_rd_A	315086547	6012	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315086547	105205	0	0
T26	34395	931	0	0
T29	187613	3219	0	0
T30	0	585	0	0
T43	0	1060	0	0
T44	0	2486	0	0
T45	0	1450	0	0
T46	0	6078	0	0
T47	0	1265	0	0
T48	0	2285	0	0
T49	0	3281	0	0
T50	28693	0	0	0
T51	8332	0	0	0
T52	23496	0	0	0
T53	242952	0	0	0
T54	9817	0	0	0
T55	44020	0	0	0
T56	10036	0	0	0
T57	28698	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315086547	5998	0	0
T26	34395	0	0	0
T29	187613	402	0	0
T30	0	205	0	0
T48	0	500	0	0
T50	28693	0	0	0
T51	8332	0	0	0
T52	23496	0	0	0
T53	242952	0	0	0
T54	9817	0	0	0
T55	44020	0	0	0
T56	10036	0	0	0
T57	28698	0	0	0
T111	0	435	0	0
T112	0	160	0	0
T113	0	440	0	0
T114	0	846	0	0
T115	0	444	0	0
T116	0	570	0	0
T117	0	288	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315086547	5446	0	0
T26	34395	0	0	0
T29	187613	376	0	0
T30	0	207	0	0
T48	0	510	0	0
T50	28693	0	0	0
T51	8332	0	0	0
T52	23496	0	0	0
T53	242952	0	0	0
T54	9817	0	0	0
T55	44020	0	0	0
T56	10036	0	0	0
T57	28698	0	0	0
T111	0	383	0	0
T112	0	144	0	0
T113	0	488	0	0
T114	0	573	0	0
T115	0	410	0	0
T116	0	477	0	0
T117	0	290	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	315086547	6012	0	0
T26	34395	0	0	0
T29	187613	359	0	0
T30	0	296	0	0
T48	0	554	0	0
T50	28693	0	0	0
T51	8332	0	0	0
T52	23496	0	0	0
T53	242952	0	0	0
T54	9817	0	0	0
T55	44020	0	0	0
T56	10036	0	0	0
T57	28698	0	0	0
T111	0	467	0	0
T112	0	141	0	0
T113	0	526	0	0
T114	0	661	0	0
T115	0	383	0	0
T116	0	469	0	0
T117	0	372	0	0