Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14346546	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

59458462

1

T1

2881

T2

52212

T3

304470

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36811549	1			T1	1556		T2	142857		T3	166956
values[0x0]	17058260	1			T1	765		T2	47585		T3	80656
values[0x1]	19935199	1			T1	843		T2	94495		T3	87435

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7148393	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

66656615

1

T1

3026

T2

169382

T3

319922

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	247995	1			T2	1094		T3	1354		T6	668
valid_sources[0x01]	258550	1			T2	1078		T3	1410		T6	649
valid_sources[0x02]	345913	1			T2	1169		T3	1406		T6	646
valid_sources[0x03]	272374	1			T2	1054		T3	1206		T6	681
valid_sources[0x04]	309526	1			T2	1119		T3	1229		T6	747
valid_sources[0x05]	260160	1			T2	1062		T3	1319		T6	724
valid_sources[0x06]	314915	1			T1	67		T2	995		T3	1271
valid_sources[0x07]	285207	1			T2	1131		T3	1300		T6	658
valid_sources[0x08]	300340	1			T1	86		T2	1183		T3	1150
valid_sources[0x09]	253088	1			T2	1108		T3	1312		T6	710
valid_sources[0x0a]	282206	1			T2	1138		T3	1347		T6	756
valid_sources[0x0b]	242385	1			T2	1125		T3	1453		T6	729
valid_sources[0x0c]	316894	1			T2	1036		T3	1382		T6	780
valid_sources[0x0d]	294612	1			T2	1132		T3	1428		T6	702
valid_sources[0x0e]	349117	1			T2	1119		T3	1423		T6	697
valid_sources[0x0f]	298888	1			T2	1151		T3	1597		T6	707
valid_sources[0x10]	286171	1			T2	1104		T3	1252		T6	715
valid_sources[0x11]	248330	1			T2	1163		T3	1146		T6	762
valid_sources[0x12]	298755	1			T2	1065		T3	1272		T6	800
valid_sources[0x13]	285629	1			T2	1133		T3	1265		T6	698
valid_sources[0x14]	304082	1			T2	1111		T3	1428		T6	704
valid_sources[0x15]	326605	1			T1	144		T2	1067		T3	1266
valid_sources[0x16]	283375	1			T2	1047		T3	1176		T6	701
valid_sources[0x17]	243787	1			T1	168		T2	1193		T3	1272
valid_sources[0x18]	274636	1			T1	33		T2	1158		T3	1257
valid_sources[0x19]	402461	1			T2	1119		T3	1314		T6	691
valid_sources[0x1a]	239045	1			T2	1069		T3	1441		T6	718
valid_sources[0x1b]	319352	1			T2	1103		T3	1290		T6	763
valid_sources[0x1c]	265387	1			T2	994		T3	1457		T6	715
valid_sources[0x1d]	272018	1			T1	112		T2	1034		T3	1188
valid_sources[0x1e]	252719	1			T2	1174		T3	1601		T6	737
valid_sources[0x1f]	289588	1			T2	1223		T3	1431		T6	785
valid_sources[0x20]	275927	1			T2	1147		T3	1286		T6	687
valid_sources[0x21]	321266	1			T1	49		T2	1171		T3	1074
valid_sources[0x22]	266766	1			T1	55		T2	1040		T3	1434
valid_sources[0x23]	254015	1			T1	6		T2	1266		T3	1170
valid_sources[0x24]	278078	1			T2	1185		T3	1226		T6	670
valid_sources[0x25]	281132	1			T1	36		T2	1105		T3	1260
valid_sources[0x26]	284323	1			T2	1016		T3	1220		T6	641
valid_sources[0x27]	271639	1			T2	1152		T3	1227		T6	713
valid_sources[0x28]	268349	1			T2	1096		T3	1376		T6	699
valid_sources[0x29]	292721	1			T2	1116		T3	1326		T6	709
valid_sources[0x2a]	249959	1			T2	1162		T3	1246		T6	756
valid_sources[0x2b]	241693	1			T1	111		T2	1159		T3	1485
valid_sources[0x2c]	294986	1			T2	1081		T3	1130		T6	710
valid_sources[0x2d]	242558	1			T1	12		T2	1115		T3	1187
valid_sources[0x2e]	235402	1			T2	1096		T3	1440		T6	741
valid_sources[0x2f]	290830	1			T2	1118		T3	1373		T6	661
valid_sources[0x30]	252527	1			T2	1062		T3	966		T6	632
valid_sources[0x31]	249299	1			T2	1049		T3	1314		T6	666
valid_sources[0x32]	284209	1			T2	1091		T3	1150		T6	748
valid_sources[0x33]	425166	1			T2	1178		T3	1333		T6	761
valid_sources[0x34]	249961	1			T2	1076		T3	1271		T6	651
valid_sources[0x35]	262841	1			T2	1214		T3	1341		T6	639
valid_sources[0x36]	270394	1			T2	1158		T3	1167		T6	749
valid_sources[0x37]	308765	1			T2	1174		T3	1312		T6	717
valid_sources[0x38]	334177	1			T2	1153		T3	1257		T6	621
valid_sources[0x39]	281312	1			T2	1130		T3	1251		T6	719
valid_sources[0x3a]	394578	1			T2	1100		T3	1466		T6	697
valid_sources[0x3b]	386666	1			T2	1177		T3	1246		T6	720
valid_sources[0x3c]	256442	1			T2	1090		T3	1146		T6	763
valid_sources[0x3d]	266621	1			T2	1131		T3	1248		T6	683
valid_sources[0x3e]	278306	1			T2	1143		T3	1543		T6	826
valid_sources[0x3f]	283600	1			T2	1182		T3	1471		T6	707
valid_sources[0x40]	292169	1			T2	1130		T3	1446		T6	691
valid_sources[0x41]	380415	1			T2	1066		T3	1158		T6	634
valid_sources[0x42]	329728	1			T2	1063		T3	1173		T6	796
valid_sources[0x43]	358661	1			T2	1149		T3	1081		T6	726
valid_sources[0x44]	260210	1			T2	1183		T3	1403		T6	725
valid_sources[0x45]	301490	1			T2	1101		T3	1106		T6	663
valid_sources[0x46]	317196	1			T2	1148		T3	1375		T6	772
valid_sources[0x47]	461423	1			T2	1161		T3	1374		T6	793
valid_sources[0x48]	296326	1			T1	36		T2	1140		T3	1054
valid_sources[0x49]	258453	1			T2	1082		T3	1223		T6	672
valid_sources[0x4a]	232845	1			T2	1094		T3	1283		T6	701
valid_sources[0x4b]	274518	1			T1	20		T2	1258		T3	1086
valid_sources[0x4c]	382433	1			T2	1086		T3	1303		T6	727
valid_sources[0x4d]	291640	1			T2	1199		T3	1372		T6	765
valid_sources[0x4e]	233872	1			T2	1036		T3	1457		T6	785
valid_sources[0x4f]	289783	1			T2	1243		T3	1209		T6	680
valid_sources[0x50]	251353	1			T2	1188		T3	1359		T6	715
valid_sources[0x51]	319193	1			T2	1096		T3	1434		T6	697
valid_sources[0x52]	386764	1			T2	1154		T3	1268		T6	705
valid_sources[0x53]	263518	1			T2	1088		T3	1285		T6	776
valid_sources[0x54]	303024	1			T2	1158		T3	1165		T6	674
valid_sources[0x55]	238472	1			T1	129		T2	1125		T3	1071
valid_sources[0x56]	298055	1			T2	1153		T3	1356		T6	716
valid_sources[0x57]	238838	1			T2	1109		T3	1206		T6	681
valid_sources[0x58]	306845	1			T2	1175		T3	1276		T6	685
valid_sources[0x59]	309048	1			T2	1099		T3	1186		T6	808
valid_sources[0x5a]	287481	1			T2	1116		T3	1465		T6	710
valid_sources[0x5b]	270560	1			T1	46		T2	1111		T3	1225
valid_sources[0x5c]	279750	1			T2	1168		T3	1357		T6	747
valid_sources[0x5d]	263262	1			T2	1052		T3	1325		T6	640
valid_sources[0x5e]	237208	1			T2	1124		T3	1197		T6	672
valid_sources[0x5f]	337132	1			T2	1038		T3	1460		T6	653
valid_sources[0x60]	265490	1			T2	1037		T3	1195		T6	633
valid_sources[0x61]	273367	1			T1	127		T2	1056		T3	1351
valid_sources[0x62]	237457	1			T2	1136		T3	1195		T6	688
valid_sources[0x63]	306539	1			T1	90		T2	1110		T3	1236
valid_sources[0x64]	257361	1			T1	41		T2	1072		T3	1401
valid_sources[0x65]	236654	1			T1	19		T2	987		T3	1367
valid_sources[0x66]	253320	1			T2	1135		T3	1442		T6	733
valid_sources[0x67]	302806	1			T1	81		T2	1086		T3	1267
valid_sources[0x68]	279727	1			T2	1145		T3	1316		T6	741
valid_sources[0x69]	265713	1			T2	1192		T3	1532		T6	694
valid_sources[0x6a]	257189	1			T2	1064		T3	1141		T6	723
valid_sources[0x6b]	303638	1			T2	1045		T3	1367		T6	742
valid_sources[0x6c]	231734	1			T2	1056		T3	1504		T6	715
valid_sources[0x6d]	283325	1			T2	1119		T3	1354		T6	654
valid_sources[0x6e]	305464	1			T2	1089		T3	1141		T6	599
valid_sources[0x6f]	265778	1			T1	76		T2	1126		T3	1259
valid_sources[0x70]	254979	1			T2	1172		T3	1333		T6	698
valid_sources[0x71]	372464	1			T2	1049		T3	1283		T6	679
valid_sources[0x72]	299853	1			T2	1167		T3	1320		T6	656
valid_sources[0x73]	285299	1			T2	1073		T3	1423		T6	651
valid_sources[0x74]	254252	1			T2	1043		T3	1167		T6	763
valid_sources[0x75]	247762	1			T2	1089		T3	1390		T6	645
valid_sources[0x76]	282877	1			T2	1021		T3	1478		T6	601
valid_sources[0x77]	299228	1			T2	1014		T3	1376		T6	712
valid_sources[0x78]	302378	1			T2	1060		T3	1195		T6	649
valid_sources[0x79]	346963	1			T1	31		T2	1133		T3	1278
valid_sources[0x7a]	325599	1			T2	1124		T3	1181		T6	833
valid_sources[0x7b]	276198	1			T2	1116		T3	1234		T6	697
valid_sources[0x7c]	270562	1			T1	106		T2	1126		T3	1205
valid_sources[0x7d]	281376	1			T2	1063		T3	1529		T6	654
valid_sources[0x7e]	345836	1			T1	71		T2	1150		T3	1397
valid_sources[0x7f]	264889	1			T2	1198		T3	1216		T6	684
valid_sources[0x80]	263322	1			T1	23		T2	1136		T3	1149

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29642215

1

T1

1410

T2

26181

T3

151811

values[0x0]

all_enables

biggest_size

14904753

1

T1

730

T2

12991

T3

76057

values[0x1]

all_enables

biggest_size

14911494

1

T1

741

T2

13040

T3

76602

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32996	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

118488

1

T1

23

T3

10

T6

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	44974	1			T1	27		T7	18		T4	35
values[0x0]	51868	1			T1	17		T2	4		T3	23
values[0x1]	54642	1			T1	14		T2	4		T3	22

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25490	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

125994

1

T1

27

T2

2

T3

15

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	423	1			T1	1		T28	5		T76	2
valid_sources[0x01]	883	1			T4	3		T28	3		T29	11
valid_sources[0x02]	699	1			T28	20		T76	1		T5	8
valid_sources[0x03]	916	1			T137	2		T28	8		T29	3
valid_sources[0x04]	834	1			T14	6		T4	1		T28	5
valid_sources[0x05]	408	1			T4	1		T28	2		T29	4
valid_sources[0x06]	698	1			T3	2		T28	4		T52	2
valid_sources[0x07]	455	1			T28	6		T29	5		T24	2
valid_sources[0x08]	573	1			T28	11		T138	2		T29	8
valid_sources[0x09]	637	1			T28	14		T52	1		T54	1
valid_sources[0x0a]	730	1			T7	3		T4	2		T28	3
valid_sources[0x0b]	532	1			T28	7		T57	1		T24	1
valid_sources[0x0c]	636	1			T1	5		T28	9		T29	3
valid_sources[0x0d]	499	1			T7	2		T28	1		T16	1
valid_sources[0x0e]	557	1			T1	2		T3	1		T7	3
valid_sources[0x0f]	581	1			T6	1		T14	10		T28	7
valid_sources[0x10]	860	1			T4	2		T29	7		T56	1
valid_sources[0x11]	896	1			T29	2		T56	1		T57	1
valid_sources[0x12]	522	1			T137	2		T29	7		T27	1
valid_sources[0x13]	471	1			T3	1		T7	1		T4	1
valid_sources[0x14]	452	1			T28	34		T29	1		T24	3
valid_sources[0x15]	397	1			T3	1		T7	1		T137	1
valid_sources[0x16]	533	1			T7	4		T29	3		T24	1
valid_sources[0x17]	459	1			T12	2		T70	1		T75	1
valid_sources[0x18]	425	1			T7	2		T4	1		T29	10
valid_sources[0x19]	590	1			T28	26		T29	4		T57	1
valid_sources[0x1a]	592	1			T7	4		T28	2		T29	2
valid_sources[0x1b]	473	1			T1	1		T4	1		T28	13
valid_sources[0x1c]	511	1			T28	1		T29	2		T57	2
valid_sources[0x1d]	695	1			T28	22		T16	1		T5	5
valid_sources[0x1e]	455	1			T4	1		T70	4		T28	11
valid_sources[0x1f]	592	1			T1	1		T28	4		T5	3
valid_sources[0x20]	721	1			T1	1		T7	1		T12	6
valid_sources[0x21]	534	1			T4	1		T28	13		T29	9
valid_sources[0x22]	916	1			T28	14		T52	1		T29	5
valid_sources[0x23]	613	1			T3	1		T28	7		T5	2
valid_sources[0x24]	761	1			T1	1		T28	17		T29	5
valid_sources[0x25]	663	1			T3	3		T7	3		T28	13
valid_sources[0x26]	410	1			T70	1		T28	3		T16	2
valid_sources[0x27]	694	1			T1	1		T4	1		T28	10
valid_sources[0x28]	540	1			T28	18		T76	2		T56	1
valid_sources[0x29]	572	1			T17	1		T28	6		T29	5
valid_sources[0x2a]	449	1			T12	2		T4	1		T28	15
valid_sources[0x2b]	564	1			T1	1		T28	3		T29	1
valid_sources[0x2c]	518	1			T28	13		T5	7		T29	6
valid_sources[0x2d]	765	1			T4	1		T28	7		T29	6
valid_sources[0x2e]	868	1			T4	1		T28	24		T29	11
valid_sources[0x2f]	605	1			T7	1		T8	1		T28	11
valid_sources[0x30]	634	1			T28	4		T29	4		T24	1
valid_sources[0x31]	496	1			T28	7		T130	1		T29	11
valid_sources[0x32]	509	1			T28	10		T29	8		T27	1
valid_sources[0x33]	488	1			T1	2		T28	12		T29	5
valid_sources[0x34]	487	1			T28	15		T130	1		T29	3
valid_sources[0x35]	560	1			T6	1		T7	8		T28	3
valid_sources[0x36]	460	1			T28	12		T29	4		T56	1
valid_sources[0x37]	609	1			T28	15		T52	1		T29	4
valid_sources[0x38]	591	1			T28	5		T29	7		T24	1
valid_sources[0x39]	528	1			T29	10		T56	2		T25	4
valid_sources[0x3a]	532	1			T3	2		T28	2		T29	1
valid_sources[0x3b]	822	1			T7	1		T28	3		T76	1
valid_sources[0x3c]	514	1			T28	11		T29	5		T57	1
valid_sources[0x3d]	491	1			T28	4		T29	5		T24	1
valid_sources[0x3e]	498	1			T28	2		T29	7		T114	1
valid_sources[0x3f]	466	1			T28	3		T29	7		T24	2
valid_sources[0x40]	453	1			T28	11		T29	3		T24	2
valid_sources[0x41]	538	1			T28	4		T76	1		T29	6
valid_sources[0x42]	730	1			T1	1		T28	8		T16	1
valid_sources[0x43]	615	1			T28	5		T29	9		T25	4
valid_sources[0x44]	615	1			T7	2		T4	2		T28	3
valid_sources[0x45]	683	1			T3	2		T4	1		T28	17
valid_sources[0x46]	578	1			T1	2		T3	1		T28	3
valid_sources[0x47]	633	1			T4	1		T28	14		T29	2
valid_sources[0x48]	487	1			T1	1		T28	8		T29	4
valid_sources[0x49]	731	1			T28	11		T30	1		T29	1
valid_sources[0x4a]	443	1			T28	24		T29	4		T57	1
valid_sources[0x4b]	504	1			T7	1		T28	5		T29	6
valid_sources[0x4c]	483	1			T28	13		T29	7		T24	1
valid_sources[0x4d]	594	1			T4	1		T28	6		T29	8
valid_sources[0x4e]	545	1			T3	1		T28	1		T16	1
valid_sources[0x4f]	537	1			T4	1		T28	12		T29	4
valid_sources[0x50]	537	1			T3	1		T29	5		T24	1
valid_sources[0x51]	520	1			T12	4		T137	1		T28	14
valid_sources[0x52]	523	1			T4	1		T28	1		T16	1
valid_sources[0x53]	550	1			T28	1		T16	1		T43	4
valid_sources[0x54]	469	1			T28	11		T29	2		T56	1
valid_sources[0x55]	593	1			T12	1		T28	6		T29	4
valid_sources[0x56]	1098	1			T4	1		T28	9		T29	8
valid_sources[0x57]	587	1			T3	2		T7	1		T12	1
valid_sources[0x58]	540	1			T28	3		T29	4		T57	2
valid_sources[0x59]	376	1			T28	11		T130	1		T29	2
valid_sources[0x5a]	538	1			T28	10		T29	3		T58	2
valid_sources[0x5b]	569	1			T12	1		T70	1		T28	8
valid_sources[0x5c]	893	1			T3	3		T12	1		T28	2
valid_sources[0x5d]	553	1			T28	11		T29	3		T24	1
valid_sources[0x5e]	409	1			T28	7		T130	1		T29	4
valid_sources[0x5f]	416	1			T28	8		T16	2		T29	12
valid_sources[0x60]	574	1			T1	1		T70	1		T29	1
valid_sources[0x61]	475	1			T28	14		T29	6		T57	1
valid_sources[0x62]	693	1			T3	1		T28	10		T29	3
valid_sources[0x63]	467	1			T4	1		T28	11		T29	4
valid_sources[0x64]	636	1			T2	1		T4	1		T28	27
valid_sources[0x65]	795	1			T1	1		T7	1		T28	16
valid_sources[0x66]	472	1			T4	2		T28	9		T29	7
valid_sources[0x67]	593	1			T1	1		T28	5		T29	3
valid_sources[0x68]	631	1			T28	6		T29	5		T24	2
valid_sources[0x69]	808	1			T28	3		T29	3		T24	1
valid_sources[0x6a]	532	1			T4	1		T28	5		T52	3
valid_sources[0x6b]	469	1			T1	1		T28	17		T29	2
valid_sources[0x6c]	515	1			T13	2		T28	7		T29	5
valid_sources[0x6d]	555	1			T1	1		T7	2		T28	1
valid_sources[0x6e]	459	1			T28	5		T16	1		T29	5
valid_sources[0x6f]	654	1			T28	6		T57	1		T24	2
valid_sources[0x70]	549	1			T28	3		T29	7		T24	1
valid_sources[0x71]	518	1			T1	1		T28	16		T29	7
valid_sources[0x72]	660	1			T3	1		T28	11		T29	14
valid_sources[0x73]	428	1			T12	1		T28	1		T29	10
valid_sources[0x74]	476	1			T1	2		T7	1		T4	1
valid_sources[0x75]	735	1			T28	8		T29	6		T24	1
valid_sources[0x76]	503	1			T4	1		T29	5		T24	2
valid_sources[0x77]	642	1			T1	1		T28	24		T29	3
valid_sources[0x78]	528	1			T28	27		T29	4		T56	8
valid_sources[0x79]	447	1			T4	1		T70	1		T28	4
valid_sources[0x7a]	454	1			T3	2		T28	5		T29	1
valid_sources[0x7b]	634	1			T69	1		T137	1		T28	8
valid_sources[0x7c]	562	1			T7	4		T14	2		T4	2
valid_sources[0x7d]	744	1			T28	2		T95	1		T29	3
valid_sources[0x7e]	474	1			T1	1		T137	1		T28	10
valid_sources[0x7f]	442	1			T28	7		T29	6		T56	1
valid_sources[0x80]	522	1			T29	2		T24	3		T25	48

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

33027

1

T1

16

T7

6

T4

19

values[0x0]

all_enables

biggest_size

43851

1

T1

4

T3

6

T6

1

values[0x1]

all_enables

biggest_size

41610

1

T1

3

T3

4

T6

1