Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13995784

1

T1

21

T2

232725

T3

28435

full_word

54298571

1

T1

240

T2

52212

T3

282699

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	68294025	1			T1	261		T2	284937		T3	311134
auto[TlIntgErrCmd]	101	1			T101	7		T102	5		T103	3
auto[TlIntgErrData]	123	1			T101	7		T102	7		T103	8
auto[TlIntgErrBoth]	106	1			T101	6		T102	8		T103	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31254488

1

T1

131

T2

142857

T3

143043

auto[1]

37039867

1

T1

130

T2

142080

T3

168091

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6694698	1			T1	9		T2	116676		T3	13003
auto[TlIntgErrNone]	partial	auto[1]	7300785	1			T1	12		T2	116049		T3	15432
auto[TlIntgErrNone]	full_word	auto[0]	24559652	1			T1	122		T2	26181		T3	130040
auto[TlIntgErrNone]	full_word	auto[1]	29738890	1			T1	118		T2	26031		T3	152659
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T101	1		T102	1		T103	1
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T101	3		T102	2		T103	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T123	1		T124	1		T125	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T101	3		T102	2		T117	1
auto[TlIntgErrData]	partial	auto[0]	53	1			T101	2		T102	2		T103	4
auto[TlIntgErrData]	partial	auto[1]	63	1			T101	3		T102	5		T103	4
auto[TlIntgErrData]	full_word	auto[0]	4	1			T101	1		T126	1		T125	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T101	1		T117	1		T123	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T102	5		T103	3		T122	3
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T101	6		T102	2		T103	5
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T102	1		T127	1		T128	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T103	1		T117	1		T121	1