Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	574871	1			T2	16992		T4	7836		T13	47
auto[1]	10859559	1			T1	6		T2	17810		T3	2920
auto[2]	471986	1			T2	14884		T4	6909		T13	50
auto[3]	10763954	1			T1	5		T2	16143		T3	2936

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14476743	1			T1	5		T2	1407		T3	4075
auto[1]	2201642	1			T1	4		T2	7601		T3	839
auto[2]	2191253	1			T1	2		T2	9355		T3	832
auto[3]	3800732	1			T2	47466		T3	110		T6	1095

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8608426

1

T1

11

T2

8

T3

5851

auto[1]

14061944

1

T2

65821

T3

5

T6

149631

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	269311	1			T4	6396		T13	37		T54	62
auto[0]	auto[0]	auto[1]	28100	1			T4	684		T13	3		T54	216
auto[0]	auto[0]	auto[2]	28249	1			T2	1		T4	695		T13	6
auto[0]	auto[0]	auto[3]	10404	1			T2	4		T4	52		T13	1
auto[0]	auto[1]	auto[0]	3277765	1			T1	3		T3	2016		T6	9
auto[0]	auto[1]	auto[1]	342827	1			T1	3		T3	627		T6	1
auto[0]	auto[1]	auto[2]	329041	1			T3	217		T7	27		T8	296
auto[0]	auto[1]	auto[3]	70765	1			T3	59		T7	12		T8	57
auto[0]	auto[2]	auto[0]	227085	1			T4	5818		T13	44		T54	39
auto[0]	auto[2]	auto[1]	24020	1			T4	604		T13	2		T54	205
auto[0]	auto[2]	auto[2]	22346	1			T4	440		T13	4		T54	184
auto[0]	auto[2]	auto[3]	8544	1			T2	1		T4	41		T54	813
auto[0]	auto[3]	auto[0]	3233258	1			T1	2		T3	2055		T6	19
auto[0]	auto[3]	auto[1]	324627	1			T1	1		T3	212		T6	1
auto[0]	auto[3]	auto[2]	338553	1			T1	2		T2	1		T3	614
auto[0]	auto[3]	auto[3]	73531	1			T2	1		T3	51		T7	7
auto[1]	auto[0]	auto[0]	8131	1			T2	594		T4	6		T43	2
auto[1]	auto[0]	auto[1]	35424	1			T2	2533		T4	2		T54	1
auto[1]	auto[0]	auto[2]	35438	1			T2	2484		T4	1		T96	4020
auto[1]	auto[0]	auto[3]	159814	1			T2	11376		T75	3		T96	18199
auto[1]	auto[1]	auto[0]	3727139	1			T2	321		T3	1		T6	62199
auto[1]	auto[1]	auto[1]	713640	1			T2	2865		T6	5666		T11	4
auto[1]	auto[1]	auto[2]	704521	1			T2	1691		T6	6340		T11	2
auto[1]	auto[1]	auto[3]	1693861	1			T2	12933		T6	539		T69	1
auto[1]	auto[2]	auto[0]	7208	1			T2	351		T4	3		T43	2
auto[1]	auto[2]	auto[1]	31489	1			T2	1537		T4	1		T54	1
auto[1]	auto[2]	auto[2]	27415	1			T2	2357		T4	2		T130	1
auto[1]	auto[2]	auto[3]	123879	1			T2	10638		T75	1		T96	12206
auto[1]	auto[3]	auto[0]	3726846	1			T2	141		T3	3		T6	62450
auto[1]	auto[3]	auto[1]	701515	1			T2	666		T6	6230		T11	4
auto[1]	auto[3]	auto[2]	705690	1			T2	2821		T3	1		T6	5651
auto[1]	auto[3]	auto[3]	1659934	1			T2	12513		T6	556		T9	1