Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.26	100.00	94.62	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	311912359	107644	0	0
ctrl_regwen_rd_A	311912359	6324	0	0
exec_rd_A	311912359	5845	0	0
exec_regwen_rd_A	311912359	6715	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311912359	107644	0	0
T16	440204	0	0	0
T23	519048	0	0	0
T25	0	6973	0	0
T28	64824	2069	0	0
T29	0	825	0	0
T30	2297	0	0	0
T43	159365	0	0	0
T44	0	4347	0	0
T45	0	1470	0	0
T46	0	1994	0	0
T47	0	1851	0	0
T48	0	3603	0	0
T49	0	1611	0	0
T50	0	1679	0	0
T51	43844	0	0	0
T52	123128	0	0	0
T53	23266	0	0	0
T54	71475	0	0	0
T55	37189	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311912359	6324	0	0
T29	36434	108	0	0
T44	0	554	0	0
T46	0	450	0	0
T56	392090	0	0	0
T57	201088	0	0	0
T96	183567	0	0	0
T104	0	405	0	0
T105	0	446	0	0
T106	0	217	0	0
T107	0	331	0	0
T108	0	496	0	0
T109	0	377	0	0
T110	0	175	0	0
T111	150616	0	0	0
T112	12808	0	0	0
T113	13398	0	0	0
T114	1169	0	0	0
T115	7311	0	0	0
T116	10967	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311912359	5845	0	0
T29	36434	75	0	0
T44	0	422	0	0
T46	0	414	0	0
T56	392090	0	0	0
T57	201088	0	0	0
T96	183567	0	0	0
T104	0	314	0	0
T105	0	507	0	0
T106	0	261	0	0
T107	0	249	0	0
T108	0	396	0	0
T109	0	330	0	0
T110	0	152	0	0
T111	150616	0	0	0
T112	12808	0	0	0
T113	13398	0	0	0
T114	1169	0	0	0
T115	7311	0	0	0
T116	10967	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311912359	6715	0	0
T29	36434	139	0	0
T44	0	450	0	0
T46	0	535	0	0
T56	392090	0	0	0
T57	201088	0	0	0
T96	183567	0	0	0
T104	0	379	0	0
T105	0	575	0	0
T106	0	363	0	0
T107	0	319	0	0
T108	0	398	0	0
T109	0	376	0	0
T110	0	226	0	0
T111	150616	0	0	0
T112	12808	0	0	0
T113	13398	0	0	0
T114	1169	0	0	0
T115	7311	0	0	0
T116	10967	0	0	0