| T305 |
/workspace/coverage/default/12.sram_ctrl_ram_cfg.4033350515 |
|
|
Mar 31 02:30:04 PM PDT 24 |
Mar 31 02:30:05 PM PDT 24 |
30640341 ps |
| T100 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3883365675 |
|
|
Mar 31 02:29:46 PM PDT 24 |
Mar 31 02:33:17 PM PDT 24 |
5175049843 ps |
| T306 |
/workspace/coverage/default/4.sram_ctrl_stress_all.395751020 |
|
|
Mar 31 02:29:15 PM PDT 24 |
Mar 31 02:40:46 PM PDT 24 |
32764017213 ps |
| T101 |
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.491037723 |
|
|
Mar 31 02:31:16 PM PDT 24 |
Mar 31 02:32:01 PM PDT 24 |
1456730532 ps |
| T307 |
/workspace/coverage/default/5.sram_ctrl_stress_all.1449868608 |
|
|
Mar 31 02:29:22 PM PDT 24 |
Mar 31 02:50:56 PM PDT 24 |
5734893440 ps |
| T308 |
/workspace/coverage/default/49.sram_ctrl_regwen.3138166040 |
|
|
Mar 31 02:37:31 PM PDT 24 |
Mar 31 02:50:08 PM PDT 24 |
23029581571 ps |
| T309 |
/workspace/coverage/default/48.sram_ctrl_executable.980347905 |
|
|
Mar 31 02:37:19 PM PDT 24 |
Mar 31 02:51:48 PM PDT 24 |
15367203973 ps |
| T310 |
/workspace/coverage/default/44.sram_ctrl_executable.2831016123 |
|
|
Mar 31 02:36:43 PM PDT 24 |
Mar 31 02:48:35 PM PDT 24 |
16182364275 ps |
| T311 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.940986768 |
|
|
Mar 31 02:35:47 PM PDT 24 |
Mar 31 02:35:51 PM PDT 24 |
204648974 ps |
| T312 |
/workspace/coverage/default/29.sram_ctrl_access_during_key_req.1771289152 |
|
|
Mar 31 02:33:26 PM PDT 24 |
Mar 31 02:45:12 PM PDT 24 |
2392241633 ps |
| T313 |
/workspace/coverage/default/35.sram_ctrl_bijection.749102332 |
|
|
Mar 31 02:34:28 PM PDT 24 |
Mar 31 02:35:14 PM PDT 24 |
2915278192 ps |
| T314 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.2003149929 |
|
|
Mar 31 02:30:45 PM PDT 24 |
Mar 31 02:30:54 PM PDT 24 |
887670724 ps |
| T315 |
/workspace/coverage/default/28.sram_ctrl_smoke.1278974471 |
|
|
Mar 31 02:33:15 PM PDT 24 |
Mar 31 02:34:32 PM PDT 24 |
918171939 ps |
| T316 |
/workspace/coverage/default/4.sram_ctrl_bijection.1209736026 |
|
|
Mar 31 02:29:12 PM PDT 24 |
Mar 31 02:30:13 PM PDT 24 |
4193192371 ps |
| T317 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.349496464 |
|
|
Mar 31 02:30:32 PM PDT 24 |
Mar 31 02:30:36 PM PDT 24 |
62465277 ps |
| T318 |
/workspace/coverage/default/23.sram_ctrl_bijection.330630403 |
|
|
Mar 31 02:31:47 PM PDT 24 |
Mar 31 02:32:42 PM PDT 24 |
3381840867 ps |
| T319 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.1245070544 |
|
|
Mar 31 02:28:46 PM PDT 24 |
Mar 31 02:44:56 PM PDT 24 |
131779419392 ps |
| T320 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.1084797849 |
|
|
Mar 31 02:30:18 PM PDT 24 |
Mar 31 02:40:17 PM PDT 24 |
2423157158 ps |
| T321 |
/workspace/coverage/default/46.sram_ctrl_ram_cfg.1164026873 |
|
|
Mar 31 02:36:58 PM PDT 24 |
Mar 31 02:37:00 PM PDT 24 |
88843823 ps |
| T322 |
/workspace/coverage/default/5.sram_ctrl_regwen.1465803892 |
|
|
Mar 31 02:29:24 PM PDT 24 |
Mar 31 02:54:29 PM PDT 24 |
13582547596 ps |
| T323 |
/workspace/coverage/default/13.sram_ctrl_stress_all.1875093148 |
|
|
Mar 31 02:30:13 PM PDT 24 |
Mar 31 03:04:36 PM PDT 24 |
6072056165 ps |
| T324 |
/workspace/coverage/default/23.sram_ctrl_executable.1618307291 |
|
|
Mar 31 02:31:57 PM PDT 24 |
Mar 31 02:51:38 PM PDT 24 |
15335681718 ps |
| T325 |
/workspace/coverage/default/4.sram_ctrl_lc_escalation.3144376586 |
|
|
Mar 31 02:29:12 PM PDT 24 |
Mar 31 02:29:15 PM PDT 24 |
229868593 ps |
| T24 |
/workspace/coverage/default/0.sram_ctrl_sec_cm.3797885988 |
|
|
Mar 31 02:28:52 PM PDT 24 |
Mar 31 02:28:55 PM PDT 24 |
1949017415 ps |
| T326 |
/workspace/coverage/default/27.sram_ctrl_ram_cfg.387234281 |
|
|
Mar 31 02:33:14 PM PDT 24 |
Mar 31 02:33:15 PM PDT 24 |
151340299 ps |
| T327 |
/workspace/coverage/default/3.sram_ctrl_lc_escalation.154056889 |
|
|
Mar 31 02:29:05 PM PDT 24 |
Mar 31 02:29:09 PM PDT 24 |
284179256 ps |
| T328 |
/workspace/coverage/default/17.sram_ctrl_partial_access.354209694 |
|
|
Mar 31 02:30:51 PM PDT 24 |
Mar 31 02:31:02 PM PDT 24 |
222857339 ps |
| T329 |
/workspace/coverage/default/6.sram_ctrl_bijection.134427037 |
|
|
Mar 31 02:29:26 PM PDT 24 |
Mar 31 02:30:38 PM PDT 24 |
4194463848 ps |
| T330 |
/workspace/coverage/default/34.sram_ctrl_alert_test.1491936062 |
|
|
Mar 31 02:34:28 PM PDT 24 |
Mar 31 02:34:28 PM PDT 24 |
24596480 ps |
| T331 |
/workspace/coverage/default/24.sram_ctrl_bijection.1197144805 |
|
|
Mar 31 02:32:02 PM PDT 24 |
Mar 31 02:33:07 PM PDT 24 |
15055139974 ps |
| T332 |
/workspace/coverage/default/27.sram_ctrl_stress_all.189046879 |
|
|
Mar 31 02:33:16 PM PDT 24 |
Mar 31 03:25:24 PM PDT 24 |
209470620663 ps |
| T333 |
/workspace/coverage/default/37.sram_ctrl_smoke.2874267113 |
|
|
Mar 31 02:34:53 PM PDT 24 |
Mar 31 02:35:03 PM PDT 24 |
64003614 ps |
| T334 |
/workspace/coverage/default/47.sram_ctrl_multiple_keys.3276798087 |
|
|
Mar 31 02:37:06 PM PDT 24 |
Mar 31 02:53:11 PM PDT 24 |
2531226444 ps |
| T335 |
/workspace/coverage/default/43.sram_ctrl_smoke.2264181504 |
|
|
Mar 31 02:36:20 PM PDT 24 |
Mar 31 02:36:38 PM PDT 24 |
9094863111 ps |
| T336 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.2798493553 |
|
|
Mar 31 02:32:26 PM PDT 24 |
Mar 31 02:32:35 PM PDT 24 |
433285815 ps |
| T337 |
/workspace/coverage/default/21.sram_ctrl_bijection.332221438 |
|
|
Mar 31 02:31:28 PM PDT 24 |
Mar 31 02:31:52 PM PDT 24 |
1606621101 ps |
| T338 |
/workspace/coverage/default/19.sram_ctrl_regwen.2583701849 |
|
|
Mar 31 02:31:13 PM PDT 24 |
Mar 31 02:39:17 PM PDT 24 |
44393569839 ps |
| T339 |
/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.3945046893 |
|
|
Mar 31 02:35:12 PM PDT 24 |
Mar 31 02:40:09 PM PDT 24 |
26953148685 ps |
| T340 |
/workspace/coverage/default/28.sram_ctrl_executable.1244696084 |
|
|
Mar 31 02:33:18 PM PDT 24 |
Mar 31 02:53:03 PM PDT 24 |
14619022102 ps |
| T341 |
/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.2335737051 |
|
|
Mar 31 02:35:33 PM PDT 24 |
Mar 31 02:37:39 PM PDT 24 |
189840886 ps |
| T342 |
/workspace/coverage/default/33.sram_ctrl_stress_all.1750757906 |
|
|
Mar 31 02:34:13 PM PDT 24 |
Mar 31 03:14:43 PM PDT 24 |
6575569372 ps |
| T343 |
/workspace/coverage/default/2.sram_ctrl_mem_walk.1298026325 |
|
|
Mar 31 02:29:08 PM PDT 24 |
Mar 31 02:29:13 PM PDT 24 |
1427551970 ps |
| T344 |
/workspace/coverage/default/40.sram_ctrl_smoke.119379206 |
|
|
Mar 31 02:35:40 PM PDT 24 |
Mar 31 02:35:45 PM PDT 24 |
319911097 ps |
| T345 |
/workspace/coverage/default/32.sram_ctrl_partial_access.460448816 |
|
|
Mar 31 02:33:55 PM PDT 24 |
Mar 31 02:35:58 PM PDT 24 |
927664373 ps |
| T346 |
/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.675252434 |
|
|
Mar 31 02:33:23 PM PDT 24 |
Mar 31 02:41:53 PM PDT 24 |
160856660999 ps |
| T347 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.1539103200 |
|
|
Mar 31 02:30:11 PM PDT 24 |
Mar 31 02:30:12 PM PDT 24 |
77997408 ps |
| T348 |
/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.2769763854 |
|
|
Mar 31 02:33:25 PM PDT 24 |
Mar 31 02:33:58 PM PDT 24 |
335592738 ps |
| T349 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.740795424 |
|
|
Mar 31 02:29:57 PM PDT 24 |
Mar 31 02:44:57 PM PDT 24 |
23314460364 ps |
| T350 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.2774186835 |
|
|
Mar 31 02:36:25 PM PDT 24 |
Mar 31 02:36:30 PM PDT 24 |
141608932 ps |
| T351 |
/workspace/coverage/default/49.sram_ctrl_bijection.1229935900 |
|
|
Mar 31 02:37:28 PM PDT 24 |
Mar 31 02:38:27 PM PDT 24 |
1851084052 ps |
| T352 |
/workspace/coverage/default/38.sram_ctrl_partial_access.2519677340 |
|
|
Mar 31 02:35:14 PM PDT 24 |
Mar 31 02:35:40 PM PDT 24 |
19889887051 ps |
| T353 |
/workspace/coverage/default/25.sram_ctrl_stress_all.768011772 |
|
|
Mar 31 02:32:25 PM PDT 24 |
Mar 31 02:49:07 PM PDT 24 |
6809435609 ps |
| T354 |
/workspace/coverage/default/24.sram_ctrl_smoke.2438272421 |
|
|
Mar 31 02:32:02 PM PDT 24 |
Mar 31 02:32:09 PM PDT 24 |
1019431717 ps |
| T355 |
/workspace/coverage/default/42.sram_ctrl_stress_all.565167236 |
|
|
Mar 31 02:36:17 PM PDT 24 |
Mar 31 02:56:08 PM PDT 24 |
43033847305 ps |
| T356 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3157767176 |
|
|
Mar 31 02:29:17 PM PDT 24 |
Mar 31 02:30:05 PM PDT 24 |
105500753 ps |
| T357 |
/workspace/coverage/default/32.sram_ctrl_ram_cfg.3795562665 |
|
|
Mar 31 02:33:57 PM PDT 24 |
Mar 31 02:33:58 PM PDT 24 |
158523673 ps |
| T358 |
/workspace/coverage/default/19.sram_ctrl_mem_walk.2973749314 |
|
|
Mar 31 02:31:11 PM PDT 24 |
Mar 31 02:31:17 PM PDT 24 |
339932373 ps |
| T359 |
/workspace/coverage/default/37.sram_ctrl_ram_cfg.937221268 |
|
|
Mar 31 02:35:10 PM PDT 24 |
Mar 31 02:35:11 PM PDT 24 |
27512740 ps |
| T360 |
/workspace/coverage/default/41.sram_ctrl_alert_test.3471970329 |
|
|
Mar 31 02:36:06 PM PDT 24 |
Mar 31 02:36:08 PM PDT 24 |
18157948 ps |
| T361 |
/workspace/coverage/default/24.sram_ctrl_stress_all.259305805 |
|
|
Mar 31 02:32:09 PM PDT 24 |
Mar 31 03:23:33 PM PDT 24 |
8987457421 ps |
| T362 |
/workspace/coverage/default/28.sram_ctrl_mem_partial_access.1810289865 |
|
|
Mar 31 02:33:18 PM PDT 24 |
Mar 31 02:33:20 PM PDT 24 |
132278626 ps |
| T363 |
/workspace/coverage/default/1.sram_ctrl_mem_walk.352430191 |
|
|
Mar 31 02:28:57 PM PDT 24 |
Mar 31 02:29:02 PM PDT 24 |
756498344 ps |
| T364 |
/workspace/coverage/default/35.sram_ctrl_regwen.4008597811 |
|
|
Mar 31 02:34:41 PM PDT 24 |
Mar 31 02:58:01 PM PDT 24 |
40263255007 ps |
| T365 |
/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.4128443203 |
|
|
Mar 31 02:29:04 PM PDT 24 |
Mar 31 02:32:06 PM PDT 24 |
1179767802 ps |
| T366 |
/workspace/coverage/default/2.sram_ctrl_partial_access.1584218695 |
|
|
Mar 31 02:28:57 PM PDT 24 |
Mar 31 02:31:11 PM PDT 24 |
784381683 ps |
| T367 |
/workspace/coverage/default/42.sram_ctrl_ram_cfg.3374188877 |
|
|
Mar 31 02:36:16 PM PDT 24 |
Mar 31 02:36:16 PM PDT 24 |
36719080 ps |
| T368 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.254558133 |
|
|
Mar 31 02:35:00 PM PDT 24 |
Mar 31 02:35:55 PM PDT 24 |
421426155 ps |
| T369 |
/workspace/coverage/default/42.sram_ctrl_bijection.2888658139 |
|
|
Mar 31 02:36:09 PM PDT 24 |
Mar 31 02:36:59 PM PDT 24 |
3311422007 ps |
| T370 |
/workspace/coverage/default/13.sram_ctrl_smoke.4062520041 |
|
|
Mar 31 02:30:05 PM PDT 24 |
Mar 31 02:30:07 PM PDT 24 |
34725425 ps |
| T371 |
/workspace/coverage/default/29.sram_ctrl_regwen.3320266278 |
|
|
Mar 31 02:33:23 PM PDT 24 |
Mar 31 02:45:08 PM PDT 24 |
11118152088 ps |
| T372 |
/workspace/coverage/default/17.sram_ctrl_mem_partial_access.2665027906 |
|
|
Mar 31 02:30:57 PM PDT 24 |
Mar 31 02:31:02 PM PDT 24 |
155773746 ps |
| T373 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.1856096017 |
|
|
Mar 31 02:29:00 PM PDT 24 |
Mar 31 02:31:53 PM PDT 24 |
13117014353 ps |
| T374 |
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3307506029 |
|
|
Mar 31 02:29:28 PM PDT 24 |
Mar 31 02:34:49 PM PDT 24 |
12482276755 ps |
| T375 |
/workspace/coverage/default/46.sram_ctrl_stress_all.2120115404 |
|
|
Mar 31 02:37:07 PM PDT 24 |
Mar 31 03:27:51 PM PDT 24 |
25342445635 ps |
| T376 |
/workspace/coverage/default/46.sram_ctrl_smoke.3929225069 |
|
|
Mar 31 02:36:51 PM PDT 24 |
Mar 31 02:36:52 PM PDT 24 |
71386999 ps |
| T377 |
/workspace/coverage/default/1.sram_ctrl_stress_all.3970401305 |
|
|
Mar 31 02:29:03 PM PDT 24 |
Mar 31 04:37:48 PM PDT 24 |
419691642114 ps |
| T378 |
/workspace/coverage/default/15.sram_ctrl_partial_access.2597575612 |
|
|
Mar 31 02:30:24 PM PDT 24 |
Mar 31 02:30:32 PM PDT 24 |
164088869 ps |
| T379 |
/workspace/coverage/default/18.sram_ctrl_multiple_keys.1254712383 |
|
|
Mar 31 02:30:59 PM PDT 24 |
Mar 31 02:43:49 PM PDT 24 |
5394869826 ps |
| T380 |
/workspace/coverage/default/10.sram_ctrl_alert_test.1839599993 |
|
|
Mar 31 02:29:46 PM PDT 24 |
Mar 31 02:29:47 PM PDT 24 |
91841806 ps |
| T381 |
/workspace/coverage/default/10.sram_ctrl_regwen.846030807 |
|
|
Mar 31 02:29:47 PM PDT 24 |
Mar 31 02:54:08 PM PDT 24 |
3825282294 ps |
| T382 |
/workspace/coverage/default/18.sram_ctrl_regwen.835942072 |
|
|
Mar 31 02:31:05 PM PDT 24 |
Mar 31 02:54:51 PM PDT 24 |
64605169130 ps |
| T383 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.364087333 |
|
|
Mar 31 02:31:17 PM PDT 24 |
Mar 31 02:31:47 PM PDT 24 |
187060879 ps |
| T384 |
/workspace/coverage/default/31.sram_ctrl_bijection.3060850878 |
|
|
Mar 31 02:33:27 PM PDT 24 |
Mar 31 02:34:47 PM PDT 24 |
9236802920 ps |
| T385 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.2510942655 |
|
|
Mar 31 02:32:27 PM PDT 24 |
Mar 31 02:32:32 PM PDT 24 |
147720413 ps |
| T386 |
/workspace/coverage/default/17.sram_ctrl_mem_walk.1560274020 |
|
|
Mar 31 02:30:59 PM PDT 24 |
Mar 31 02:31:10 PM PDT 24 |
2722014918 ps |
| T387 |
/workspace/coverage/default/46.sram_ctrl_alert_test.2059590359 |
|
|
Mar 31 02:37:05 PM PDT 24 |
Mar 31 02:37:06 PM PDT 24 |
75194745 ps |
| T388 |
/workspace/coverage/default/40.sram_ctrl_mem_walk.2713044714 |
|
|
Mar 31 02:35:46 PM PDT 24 |
Mar 31 02:35:51 PM PDT 24 |
279502071 ps |
| T389 |
/workspace/coverage/default/0.sram_ctrl_partial_access.956412841 |
|
|
Mar 31 02:28:50 PM PDT 24 |
Mar 31 02:30:23 PM PDT 24 |
678447035 ps |
| T390 |
/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.3773088573 |
|
|
Mar 31 02:33:55 PM PDT 24 |
Mar 31 02:35:53 PM PDT 24 |
595524229 ps |
| T391 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.2552693179 |
|
|
Mar 31 02:30:04 PM PDT 24 |
Mar 31 02:30:07 PM PDT 24 |
227648438 ps |
| T392 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.3320640740 |
|
|
Mar 31 02:29:53 PM PDT 24 |
Mar 31 02:32:34 PM PDT 24 |
1768280918 ps |
| T393 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.192026915 |
|
|
Mar 31 02:29:17 PM PDT 24 |
Mar 31 02:29:19 PM PDT 24 |
736184505 ps |
| T394 |
/workspace/coverage/default/21.sram_ctrl_regwen.186498241 |
|
|
Mar 31 02:31:36 PM PDT 24 |
Mar 31 02:46:46 PM PDT 24 |
9517804654 ps |
| T395 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.4153448949 |
|
|
Mar 31 02:30:28 PM PDT 24 |
Mar 31 02:53:35 PM PDT 24 |
4413786583 ps |
| T396 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.2587030153 |
|
|
Mar 31 02:35:35 PM PDT 24 |
Mar 31 02:35:40 PM PDT 24 |
1396300982 ps |
| T397 |
/workspace/coverage/default/22.sram_ctrl_alert_test.4030714096 |
|
|
Mar 31 02:31:49 PM PDT 24 |
Mar 31 02:31:49 PM PDT 24 |
17406491 ps |
| T398 |
/workspace/coverage/default/21.sram_ctrl_stress_all.3891967157 |
|
|
Mar 31 02:31:42 PM PDT 24 |
Mar 31 02:44:21 PM PDT 24 |
12897556493 ps |
| T399 |
/workspace/coverage/default/42.sram_ctrl_smoke.615477539 |
|
|
Mar 31 02:36:06 PM PDT 24 |
Mar 31 02:36:14 PM PDT 24 |
698182989 ps |
| T400 |
/workspace/coverage/default/17.sram_ctrl_executable.2869692337 |
|
|
Mar 31 02:30:53 PM PDT 24 |
Mar 31 02:41:23 PM PDT 24 |
12090612431 ps |
| T401 |
/workspace/coverage/default/41.sram_ctrl_partial_access.1526712969 |
|
|
Mar 31 02:36:00 PM PDT 24 |
Mar 31 02:38:39 PM PDT 24 |
666212288 ps |
| T402 |
/workspace/coverage/default/32.sram_ctrl_smoke.2096959896 |
|
|
Mar 31 02:33:45 PM PDT 24 |
Mar 31 02:34:37 PM PDT 24 |
807381030 ps |
| T403 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.2196961114 |
|
|
Mar 31 02:29:10 PM PDT 24 |
Mar 31 02:29:26 PM PDT 24 |
264475500 ps |
| T404 |
/workspace/coverage/default/49.sram_ctrl_alert_test.2195254192 |
|
|
Mar 31 02:37:38 PM PDT 24 |
Mar 31 02:37:39 PM PDT 24 |
18392867 ps |
| T405 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2686521032 |
|
|
Mar 31 02:29:52 PM PDT 24 |
Mar 31 02:37:06 PM PDT 24 |
72253945961 ps |
| T406 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.3421120298 |
|
|
Mar 31 02:29:26 PM PDT 24 |
Mar 31 02:39:25 PM PDT 24 |
2247938432 ps |
| T407 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.531307395 |
|
|
Mar 31 02:29:28 PM PDT 24 |
Mar 31 02:34:41 PM PDT 24 |
13131808634 ps |
| T408 |
/workspace/coverage/default/28.sram_ctrl_regwen.589558890 |
|
|
Mar 31 02:33:18 PM PDT 24 |
Mar 31 02:46:39 PM PDT 24 |
37259515369 ps |
| T409 |
/workspace/coverage/default/39.sram_ctrl_executable.303456358 |
|
|
Mar 31 02:35:36 PM PDT 24 |
Mar 31 02:44:26 PM PDT 24 |
3177472476 ps |
| T410 |
/workspace/coverage/default/43.sram_ctrl_partial_access.1066624491 |
|
|
Mar 31 02:36:25 PM PDT 24 |
Mar 31 02:36:44 PM PDT 24 |
1324945526 ps |
| T411 |
/workspace/coverage/default/34.sram_ctrl_executable.705004966 |
|
|
Mar 31 02:34:19 PM PDT 24 |
Mar 31 02:36:39 PM PDT 24 |
6418179284 ps |
| T412 |
/workspace/coverage/default/22.sram_ctrl_smoke.2875337013 |
|
|
Mar 31 02:31:41 PM PDT 24 |
Mar 31 02:31:56 PM PDT 24 |
2584363671 ps |
| T413 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.3381638073 |
|
|
Mar 31 02:33:44 PM PDT 24 |
Mar 31 02:33:50 PM PDT 24 |
298707880 ps |
| T414 |
/workspace/coverage/default/20.sram_ctrl_smoke.2446546790 |
|
|
Mar 31 02:31:17 PM PDT 24 |
Mar 31 02:31:18 PM PDT 24 |
55792108 ps |
| T415 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.3018726818 |
|
|
Mar 31 02:31:36 PM PDT 24 |
Mar 31 02:32:03 PM PDT 24 |
284428305 ps |
| T416 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.846593139 |
|
|
Mar 31 02:37:28 PM PDT 24 |
Mar 31 02:51:08 PM PDT 24 |
11835482985 ps |
| T417 |
/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.2802484671 |
|
|
Mar 31 02:29:17 PM PDT 24 |
Mar 31 02:31:58 PM PDT 24 |
1939756971 ps |
| T418 |
/workspace/coverage/default/17.sram_ctrl_stress_pipeline.1854130629 |
|
|
Mar 31 02:30:52 PM PDT 24 |
Mar 31 02:34:25 PM PDT 24 |
4804854531 ps |
| T419 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.3752516357 |
|
|
Mar 31 02:29:28 PM PDT 24 |
Mar 31 02:29:33 PM PDT 24 |
126669461 ps |
| T420 |
/workspace/coverage/default/40.sram_ctrl_max_throughput.3521679743 |
|
|
Mar 31 02:35:40 PM PDT 24 |
Mar 31 02:37:18 PM PDT 24 |
1288528550 ps |
| T421 |
/workspace/coverage/default/38.sram_ctrl_stress_all.3119987595 |
|
|
Mar 31 02:35:27 PM PDT 24 |
Mar 31 03:27:49 PM PDT 24 |
41436904156 ps |
| T422 |
/workspace/coverage/default/36.sram_ctrl_alert_test.1138513447 |
|
|
Mar 31 02:34:54 PM PDT 24 |
Mar 31 02:34:55 PM PDT 24 |
23519244 ps |
| T423 |
/workspace/coverage/default/6.sram_ctrl_stress_all.2576385981 |
|
|
Mar 31 02:29:23 PM PDT 24 |
Mar 31 03:05:12 PM PDT 24 |
117600039480 ps |
| T424 |
/workspace/coverage/default/13.sram_ctrl_alert_test.2271547545 |
|
|
Mar 31 02:30:21 PM PDT 24 |
Mar 31 02:30:22 PM PDT 24 |
24609354 ps |
| T425 |
/workspace/coverage/default/40.sram_ctrl_partial_access.389377748 |
|
|
Mar 31 02:35:43 PM PDT 24 |
Mar 31 02:38:24 PM PDT 24 |
1273503219 ps |
| T426 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.3527409787 |
|
|
Mar 31 02:35:46 PM PDT 24 |
Mar 31 02:35:47 PM PDT 24 |
27892290 ps |
| T427 |
/workspace/coverage/default/39.sram_ctrl_max_throughput.1870072474 |
|
|
Mar 31 02:35:33 PM PDT 24 |
Mar 31 02:36:16 PM PDT 24 |
186707371 ps |
| T428 |
/workspace/coverage/default/1.sram_ctrl_regwen.1538434001 |
|
|
Mar 31 02:29:01 PM PDT 24 |
Mar 31 02:36:13 PM PDT 24 |
51655495680 ps |
| T429 |
/workspace/coverage/default/28.sram_ctrl_access_during_key_req.2317189860 |
|
|
Mar 31 02:33:17 PM PDT 24 |
Mar 31 02:36:51 PM PDT 24 |
1426498179 ps |
| T430 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.1064459064 |
|
|
Mar 31 02:33:24 PM PDT 24 |
Mar 31 02:35:22 PM PDT 24 |
933089124 ps |
| T431 |
/workspace/coverage/default/24.sram_ctrl_executable.1223814414 |
|
|
Mar 31 02:32:02 PM PDT 24 |
Mar 31 02:52:41 PM PDT 24 |
3127018623 ps |
| T432 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.2797959884 |
|
|
Mar 31 02:31:28 PM PDT 24 |
Mar 31 02:43:53 PM PDT 24 |
1693296679 ps |
| T433 |
/workspace/coverage/default/23.sram_ctrl_multiple_keys.3205022817 |
|
|
Mar 31 02:31:48 PM PDT 24 |
Mar 31 02:59:41 PM PDT 24 |
80036990041 ps |
| T434 |
/workspace/coverage/default/2.sram_ctrl_alert_test.937891510 |
|
|
Mar 31 02:29:05 PM PDT 24 |
Mar 31 02:29:06 PM PDT 24 |
32777900 ps |
| T435 |
/workspace/coverage/default/21.sram_ctrl_partial_access.637842028 |
|
|
Mar 31 02:31:35 PM PDT 24 |
Mar 31 02:32:15 PM PDT 24 |
829529689 ps |
| T436 |
/workspace/coverage/default/19.sram_ctrl_lc_escalation.631263844 |
|
|
Mar 31 02:31:11 PM PDT 24 |
Mar 31 02:31:15 PM PDT 24 |
471869532 ps |
| T437 |
/workspace/coverage/default/9.sram_ctrl_bijection.174640920 |
|
|
Mar 31 02:29:37 PM PDT 24 |
Mar 31 02:30:19 PM PDT 24 |
7925430161 ps |
| T438 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.771858976 |
|
|
Mar 31 02:36:48 PM PDT 24 |
Mar 31 02:39:36 PM PDT 24 |
158724370 ps |
| T439 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.2506728686 |
|
|
Mar 31 02:29:39 PM PDT 24 |
Mar 31 02:29:45 PM PDT 24 |
318283892 ps |
| T440 |
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.2289217431 |
|
|
Mar 31 02:36:00 PM PDT 24 |
Mar 31 02:40:35 PM PDT 24 |
40452209859 ps |
| T441 |
/workspace/coverage/default/43.sram_ctrl_executable.2762709210 |
|
|
Mar 31 02:36:24 PM PDT 24 |
Mar 31 02:38:19 PM PDT 24 |
347933825 ps |
| T442 |
/workspace/coverage/default/40.sram_ctrl_bijection.1945270554 |
|
|
Mar 31 02:35:40 PM PDT 24 |
Mar 31 02:36:39 PM PDT 24 |
1118004371 ps |
| T443 |
/workspace/coverage/default/33.sram_ctrl_partial_access.16501567 |
|
|
Mar 31 02:34:10 PM PDT 24 |
Mar 31 02:36:26 PM PDT 24 |
3071378599 ps |
| T444 |
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.1065493930 |
|
|
Mar 31 02:29:38 PM PDT 24 |
Mar 31 02:54:35 PM PDT 24 |
8011552864 ps |
| T445 |
/workspace/coverage/default/27.sram_ctrl_bijection.3924051354 |
|
|
Mar 31 02:32:38 PM PDT 24 |
Mar 31 02:34:02 PM PDT 24 |
41218961548 ps |
| T446 |
/workspace/coverage/default/22.sram_ctrl_multiple_keys.2469522421 |
|
|
Mar 31 02:31:42 PM PDT 24 |
Mar 31 02:49:28 PM PDT 24 |
68824719063 ps |
| T447 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.1086980951 |
|
|
Mar 31 02:29:28 PM PDT 24 |
Mar 31 02:29:29 PM PDT 24 |
78864714 ps |
| T448 |
/workspace/coverage/default/41.sram_ctrl_regwen.3123599954 |
|
|
Mar 31 02:35:58 PM PDT 24 |
Mar 31 02:48:31 PM PDT 24 |
41163871937 ps |
| T449 |
/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.1338262136 |
|
|
Mar 31 02:35:00 PM PDT 24 |
Mar 31 02:39:45 PM PDT 24 |
11415843999 ps |
| T450 |
/workspace/coverage/default/40.sram_ctrl_lc_escalation.935972633 |
|
|
Mar 31 02:35:46 PM PDT 24 |
Mar 31 02:35:53 PM PDT 24 |
649809701 ps |
| T451 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.405552074 |
|
|
Mar 31 02:31:41 PM PDT 24 |
Mar 31 02:37:44 PM PDT 24 |
16580116669 ps |
| T452 |
/workspace/coverage/default/21.sram_ctrl_lc_escalation.396780242 |
|
|
Mar 31 02:31:35 PM PDT 24 |
Mar 31 02:31:40 PM PDT 24 |
3041915188 ps |
| T453 |
/workspace/coverage/default/21.sram_ctrl_alert_test.2599354044 |
|
|
Mar 31 02:31:40 PM PDT 24 |
Mar 31 02:31:42 PM PDT 24 |
25506443 ps |
| T454 |
/workspace/coverage/default/23.sram_ctrl_ram_cfg.1632011066 |
|
|
Mar 31 02:31:56 PM PDT 24 |
Mar 31 02:31:57 PM PDT 24 |
27741902 ps |
| T455 |
/workspace/coverage/default/38.sram_ctrl_stress_pipeline.3403509060 |
|
|
Mar 31 02:35:14 PM PDT 24 |
Mar 31 02:38:39 PM PDT 24 |
4339825577 ps |
| T456 |
/workspace/coverage/default/24.sram_ctrl_multiple_keys.2959497785 |
|
|
Mar 31 02:32:02 PM PDT 24 |
Mar 31 02:34:24 PM PDT 24 |
12729720592 ps |
| T457 |
/workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.862486662 |
|
|
Mar 31 02:34:23 PM PDT 24 |
Mar 31 02:36:30 PM PDT 24 |
297744786 ps |
| T458 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.58897848 |
|
|
Mar 31 02:29:17 PM PDT 24 |
Mar 31 02:31:00 PM PDT 24 |
125497427 ps |
| T459 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.3875225370 |
|
|
Mar 31 02:30:52 PM PDT 24 |
Mar 31 02:31:00 PM PDT 24 |
790400670 ps |
| T460 |
/workspace/coverage/default/26.sram_ctrl_executable.1905782032 |
|
|
Mar 31 02:32:33 PM PDT 24 |
Mar 31 02:50:07 PM PDT 24 |
25344554297 ps |
| T461 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.3591395753 |
|
|
Mar 31 02:30:59 PM PDT 24 |
Mar 31 02:36:00 PM PDT 24 |
3332126616 ps |
| T462 |
/workspace/coverage/default/25.sram_ctrl_stress_pipeline.780642715 |
|
|
Mar 31 02:32:20 PM PDT 24 |
Mar 31 02:37:21 PM PDT 24 |
3201808774 ps |
| T463 |
/workspace/coverage/default/29.sram_ctrl_multiple_keys.3533631118 |
|
|
Mar 31 02:33:22 PM PDT 24 |
Mar 31 02:47:17 PM PDT 24 |
8436721980 ps |
| T464 |
/workspace/coverage/default/35.sram_ctrl_stress_all.1186903297 |
|
|
Mar 31 02:34:41 PM PDT 24 |
Mar 31 03:41:26 PM PDT 24 |
44093752308 ps |
| T465 |
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.5555270 |
|
|
Mar 31 02:35:00 PM PDT 24 |
Mar 31 02:36:59 PM PDT 24 |
1180169302 ps |
| T466 |
/workspace/coverage/default/39.sram_ctrl_stress_all.3120128816 |
|
|
Mar 31 02:35:40 PM PDT 24 |
Mar 31 03:06:21 PM PDT 24 |
37228256696 ps |
| T467 |
/workspace/coverage/default/29.sram_ctrl_smoke.2152995175 |
|
|
Mar 31 02:33:22 PM PDT 24 |
Mar 31 02:34:15 PM PDT 24 |
1843579034 ps |
| T468 |
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2221017735 |
|
|
Mar 31 02:29:31 PM PDT 24 |
Mar 31 02:37:46 PM PDT 24 |
3625356405 ps |
| T469 |
/workspace/coverage/default/12.sram_ctrl_alert_test.777813846 |
|
|
Mar 31 02:30:04 PM PDT 24 |
Mar 31 02:30:05 PM PDT 24 |
43048573 ps |
| T470 |
/workspace/coverage/default/40.sram_ctrl_alert_test.698342944 |
|
|
Mar 31 02:35:55 PM PDT 24 |
Mar 31 02:35:56 PM PDT 24 |
54918279 ps |
| T471 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.482620601 |
|
|
Mar 31 02:32:33 PM PDT 24 |
Mar 31 02:32:42 PM PDT 24 |
679326498 ps |
| T472 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.3394810892 |
|
|
Mar 31 02:30:26 PM PDT 24 |
Mar 31 02:30:27 PM PDT 24 |
204010289 ps |
| T473 |
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.2587918825 |
|
|
Mar 31 02:34:35 PM PDT 24 |
Mar 31 02:37:44 PM PDT 24 |
3542750551 ps |
| T474 |
/workspace/coverage/default/47.sram_ctrl_stress_all.3001584851 |
|
|
Mar 31 02:37:11 PM PDT 24 |
Mar 31 03:11:39 PM PDT 24 |
34733794162 ps |
| T475 |
/workspace/coverage/default/29.sram_ctrl_executable.3582201593 |
|
|
Mar 31 02:33:25 PM PDT 24 |
Mar 31 02:46:06 PM PDT 24 |
10273921410 ps |
| T476 |
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.2597645728 |
|
|
Mar 31 02:29:22 PM PDT 24 |
Mar 31 02:47:49 PM PDT 24 |
2883271010 ps |
| T477 |
/workspace/coverage/default/3.sram_ctrl_alert_test.249318786 |
|
|
Mar 31 02:29:09 PM PDT 24 |
Mar 31 02:29:10 PM PDT 24 |
13946727 ps |
| T478 |
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.1117212287 |
|
|
Mar 31 02:37:30 PM PDT 24 |
Mar 31 02:43:34 PM PDT 24 |
1248639064 ps |
| T479 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.3837713986 |
|
|
Mar 31 02:36:58 PM PDT 24 |
Mar 31 02:48:56 PM PDT 24 |
3882370748 ps |
| T480 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.1839826592 |
|
|
Mar 31 02:29:25 PM PDT 24 |
Mar 31 02:29:32 PM PDT 24 |
1002964977 ps |
| T481 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.2201396920 |
|
|
Mar 31 02:34:49 PM PDT 24 |
Mar 31 02:39:06 PM PDT 24 |
2904597910 ps |
| T482 |
/workspace/coverage/default/9.sram_ctrl_smoke.696503788 |
|
|
Mar 31 02:29:36 PM PDT 24 |
Mar 31 02:29:40 PM PDT 24 |
340400735 ps |
| T483 |
/workspace/coverage/default/2.sram_ctrl_multiple_keys.1721416866 |
|
|
Mar 31 02:28:59 PM PDT 24 |
Mar 31 02:39:48 PM PDT 24 |
52837105070 ps |
| T484 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.42537961 |
|
|
Mar 31 02:28:53 PM PDT 24 |
Mar 31 02:29:13 PM PDT 24 |
2260117607 ps |
| T485 |
/workspace/coverage/default/9.sram_ctrl_stress_all.1587038905 |
|
|
Mar 31 02:29:40 PM PDT 24 |
Mar 31 03:11:07 PM PDT 24 |
41886010319 ps |
| T102 |
/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.3292833255 |
|
|
Mar 31 02:30:57 PM PDT 24 |
Mar 31 02:31:09 PM PDT 24 |
1312518282 ps |
| T486 |
/workspace/coverage/default/25.sram_ctrl_multiple_keys.1505307367 |
|
|
Mar 31 02:32:24 PM PDT 24 |
Mar 31 02:47:28 PM PDT 24 |
3151131935 ps |
| T487 |
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.1088572245 |
|
|
Mar 31 02:37:05 PM PDT 24 |
Mar 31 02:37:10 PM PDT 24 |
526299535 ps |
| T488 |
/workspace/coverage/default/45.sram_ctrl_partial_access.2239041378 |
|
|
Mar 31 02:36:53 PM PDT 24 |
Mar 31 02:37:13 PM PDT 24 |
4540797997 ps |
| T489 |
/workspace/coverage/default/40.sram_ctrl_executable.2284584835 |
|
|
Mar 31 02:35:46 PM PDT 24 |
Mar 31 02:48:19 PM PDT 24 |
46430256563 ps |
| T490 |
/workspace/coverage/default/35.sram_ctrl_ram_cfg.4088483406 |
|
|
Mar 31 02:34:42 PM PDT 24 |
Mar 31 02:34:43 PM PDT 24 |
98466041 ps |
| T491 |
/workspace/coverage/default/2.sram_ctrl_smoke.2581885685 |
|
|
Mar 31 02:28:59 PM PDT 24 |
Mar 31 02:29:10 PM PDT 24 |
972030743 ps |
| T492 |
/workspace/coverage/default/41.sram_ctrl_executable.777466646 |
|
|
Mar 31 02:36:00 PM PDT 24 |
Mar 31 03:01:49 PM PDT 24 |
12925236239 ps |
| T493 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.909234106 |
|
|
Mar 31 02:33:57 PM PDT 24 |
Mar 31 02:40:33 PM PDT 24 |
17975170450 ps |
| T494 |
/workspace/coverage/default/20.sram_ctrl_access_during_key_req.3746625687 |
|
|
Mar 31 02:31:21 PM PDT 24 |
Mar 31 02:54:14 PM PDT 24 |
21392658410 ps |
| T495 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.2884434328 |
|
|
Mar 31 02:28:53 PM PDT 24 |
Mar 31 02:29:01 PM PDT 24 |
636802416 ps |
| T496 |
/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.2779804320 |
|
|
Mar 31 02:31:04 PM PDT 24 |
Mar 31 02:32:47 PM PDT 24 |
775367955 ps |
| T497 |
/workspace/coverage/default/0.sram_ctrl_regwen.2517195177 |
|
|
Mar 31 02:28:53 PM PDT 24 |
Mar 31 02:42:40 PM PDT 24 |
9759046566 ps |
| T498 |
/workspace/coverage/default/8.sram_ctrl_partial_access.701535762 |
|
|
Mar 31 02:29:31 PM PDT 24 |
Mar 31 02:29:40 PM PDT 24 |
356252779 ps |
| T499 |
/workspace/coverage/default/38.sram_ctrl_alert_test.3272955417 |
|
|
Mar 31 02:35:27 PM PDT 24 |
Mar 31 02:35:28 PM PDT 24 |
13547805 ps |
| T500 |
/workspace/coverage/default/10.sram_ctrl_executable.2550086522 |
|
|
Mar 31 02:29:49 PM PDT 24 |
Mar 31 02:37:25 PM PDT 24 |
3864735138 ps |
| T501 |
/workspace/coverage/default/16.sram_ctrl_mem_partial_access.1311892039 |
|
|
Mar 31 02:30:45 PM PDT 24 |
Mar 31 02:30:48 PM PDT 24 |
359139540 ps |
| T502 |
/workspace/coverage/default/29.sram_ctrl_ram_cfg.1920291894 |
|
|
Mar 31 02:33:24 PM PDT 24 |
Mar 31 02:33:25 PM PDT 24 |
26427813 ps |
| T503 |
/workspace/coverage/default/48.sram_ctrl_stress_all.2851613566 |
|
|
Mar 31 02:37:25 PM PDT 24 |
Mar 31 03:07:21 PM PDT 24 |
48966380599 ps |
| T504 |
/workspace/coverage/default/45.sram_ctrl_ram_cfg.1355035446 |
|
|
Mar 31 02:36:51 PM PDT 24 |
Mar 31 02:36:52 PM PDT 24 |
43526597 ps |
| T505 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2548651404 |
|
|
Mar 31 02:29:01 PM PDT 24 |
Mar 31 02:35:33 PM PDT 24 |
18234611002 ps |
| T506 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.316471774 |
|
|
Mar 31 02:35:01 PM PDT 24 |
Mar 31 02:35:08 PM PDT 24 |
521286203 ps |
| T507 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2852660723 |
|
|
Mar 31 02:29:40 PM PDT 24 |
Mar 31 02:32:04 PM PDT 24 |
1789414067 ps |
| T508 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.3567554731 |
|
|
Mar 31 02:30:52 PM PDT 24 |
Mar 31 02:34:49 PM PDT 24 |
9606814346 ps |
| T509 |
/workspace/coverage/default/20.sram_ctrl_alert_test.3910115081 |
|
|
Mar 31 02:31:28 PM PDT 24 |
Mar 31 02:31:29 PM PDT 24 |
16116561 ps |
| T103 |
/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.4128682684 |
|
|
Mar 31 02:29:05 PM PDT 24 |
Mar 31 02:30:11 PM PDT 24 |
4469833250 ps |
| T510 |
/workspace/coverage/default/13.sram_ctrl_mem_walk.937109280 |
|
|
Mar 31 02:30:14 PM PDT 24 |
Mar 31 02:30:20 PM PDT 24 |
412761049 ps |
| T511 |
/workspace/coverage/default/17.sram_ctrl_ram_cfg.3087259255 |
|
|
Mar 31 02:30:50 PM PDT 24 |
Mar 31 02:30:51 PM PDT 24 |
82757302 ps |
| T512 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.360654971 |
|
|
Mar 31 02:36:16 PM PDT 24 |
Mar 31 02:36:18 PM PDT 24 |
62217572 ps |
| T513 |
/workspace/coverage/default/46.sram_ctrl_multiple_keys.2294798182 |
|
|
Mar 31 02:36:52 PM PDT 24 |
Mar 31 02:52:36 PM PDT 24 |
2080188859 ps |
| T514 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.4204308287 |
|
|
Mar 31 02:28:54 PM PDT 24 |
Mar 31 02:28:57 PM PDT 24 |
171822493 ps |
| T515 |
/workspace/coverage/default/21.sram_ctrl_executable.3168992259 |
|
|
Mar 31 02:31:35 PM PDT 24 |
Mar 31 02:44:04 PM PDT 24 |
1437558208 ps |
| T516 |
/workspace/coverage/default/16.sram_ctrl_smoke.2971468824 |
|
|
Mar 31 02:30:39 PM PDT 24 |
Mar 31 02:30:42 PM PDT 24 |
63085274 ps |
| T517 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.1507416547 |
|
|
Mar 31 02:31:21 PM PDT 24 |
Mar 31 02:31:44 PM PDT 24 |
443690181 ps |
| T518 |
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.1045325313 |
|
|
Mar 31 02:37:12 PM PDT 24 |
Mar 31 02:44:24 PM PDT 24 |
13803547796 ps |
| T519 |
/workspace/coverage/default/1.sram_ctrl_alert_test.1654071766 |
|
|
Mar 31 02:28:58 PM PDT 24 |
Mar 31 02:28:59 PM PDT 24 |
29673742 ps |
| T520 |
/workspace/coverage/default/36.sram_ctrl_bijection.3226691476 |
|
|
Mar 31 02:34:48 PM PDT 24 |
Mar 31 02:35:13 PM PDT 24 |
1574082170 ps |
| T521 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.917287270 |
|
|
Mar 31 02:30:20 PM PDT 24 |
Mar 31 02:51:07 PM PDT 24 |
57364636207 ps |
| T522 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.3970818147 |
|
|
Mar 31 02:30:03 PM PDT 24 |
Mar 31 02:30:09 PM PDT 24 |
334519520 ps |
| T523 |
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.303458372 |
|
|
Mar 31 02:31:59 PM PDT 24 |
Mar 31 02:38:06 PM PDT 24 |
177117791484 ps |
| T524 |
/workspace/coverage/default/18.sram_ctrl_bijection.3598274784 |
|
|
Mar 31 02:30:57 PM PDT 24 |
Mar 31 02:31:43 PM PDT 24 |
4332472403 ps |
| T525 |
/workspace/coverage/default/0.sram_ctrl_stress_all.4252541632 |
|
|
Mar 31 02:28:54 PM PDT 24 |
Mar 31 02:45:08 PM PDT 24 |
83948047395 ps |
| T526 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.1373566484 |
|
|
Mar 31 02:28:59 PM PDT 24 |
Mar 31 02:29:03 PM PDT 24 |
937554817 ps |
| T527 |
/workspace/coverage/default/18.sram_ctrl_stress_all.2980834376 |
|
|
Mar 31 02:31:06 PM PDT 24 |
Mar 31 02:42:51 PM PDT 24 |
10456845515 ps |
| T528 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2407717317 |
|
|
Mar 31 02:29:23 PM PDT 24 |
Mar 31 02:31:45 PM PDT 24 |
2462919906 ps |
| T529 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.3176628993 |
|
|
Mar 31 02:34:48 PM PDT 24 |
Mar 31 02:36:30 PM PDT 24 |
117202603 ps |
| T530 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.2001606024 |
|
|
Mar 31 02:32:33 PM PDT 24 |
Mar 31 02:36:52 PM PDT 24 |
2675124650 ps |
| T531 |
/workspace/coverage/default/18.sram_ctrl_partial_access.1681042610 |
|
|
Mar 31 02:30:58 PM PDT 24 |
Mar 31 02:31:24 PM PDT 24 |
1465754756 ps |
| T532 |
/workspace/coverage/default/33.sram_ctrl_bijection.196696924 |
|
|
Mar 31 02:34:00 PM PDT 24 |
Mar 31 02:35:04 PM PDT 24 |
981487427 ps |
| T533 |
/workspace/coverage/default/29.sram_ctrl_mem_partial_access.185642418 |
|
|
Mar 31 02:33:24 PM PDT 24 |
Mar 31 02:33:27 PM PDT 24 |
95890118 ps |
| T534 |
/workspace/coverage/default/32.sram_ctrl_multiple_keys.2574697504 |
|
|
Mar 31 02:33:46 PM PDT 24 |
Mar 31 02:40:27 PM PDT 24 |
4051196369 ps |
| T535 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.41190302 |
|
|
Mar 31 02:37:14 PM PDT 24 |
Mar 31 02:39:55 PM PDT 24 |
151893643 ps |
| T536 |
/workspace/coverage/default/30.sram_ctrl_executable.1872054783 |
|
|
Mar 31 02:33:29 PM PDT 24 |
Mar 31 02:44:42 PM PDT 24 |
9434729699 ps |
| T537 |
/workspace/coverage/default/31.sram_ctrl_lc_escalation.2910208999 |
|
|
Mar 31 02:33:31 PM PDT 24 |
Mar 31 02:33:36 PM PDT 24 |
576761469 ps |
| T538 |
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.833941545 |
|
|
Mar 31 02:29:37 PM PDT 24 |
Mar 31 02:32:28 PM PDT 24 |
9872578859 ps |
| T539 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.236075470 |
|
|
Mar 31 02:37:05 PM PDT 24 |
Mar 31 02:40:23 PM PDT 24 |
4247280857 ps |
| T540 |
/workspace/coverage/default/41.sram_ctrl_bijection.404830751 |
|
|
Mar 31 02:35:53 PM PDT 24 |
Mar 31 02:37:23 PM PDT 24 |
31766781178 ps |
| T541 |
/workspace/coverage/default/16.sram_ctrl_alert_test.462974130 |
|
|
Mar 31 02:30:44 PM PDT 24 |
Mar 31 02:30:45 PM PDT 24 |
70460082 ps |
| T542 |
/workspace/coverage/default/4.sram_ctrl_executable.915795743 |
|
|
Mar 31 02:29:08 PM PDT 24 |
Mar 31 02:37:34 PM PDT 24 |
14896535113 ps |
| T543 |
/workspace/coverage/default/14.sram_ctrl_bijection.2725905951 |
|
|
Mar 31 02:30:17 PM PDT 24 |
Mar 31 02:31:16 PM PDT 24 |
11096463120 ps |
| T544 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.1863097618 |
|
|
Mar 31 02:32:39 PM PDT 24 |
Mar 31 02:37:31 PM PDT 24 |
3241331359 ps |
| T545 |
/workspace/coverage/default/3.sram_ctrl_stress_pipeline.269969659 |
|
|
Mar 31 02:29:05 PM PDT 24 |
Mar 31 02:32:04 PM PDT 24 |
1903990759 ps |
| T546 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.1917464631 |
|
|
Mar 31 02:35:14 PM PDT 24 |
Mar 31 02:53:55 PM PDT 24 |
52024882959 ps |
| T547 |
/workspace/coverage/default/47.sram_ctrl_regwen.2163405952 |
|
|
Mar 31 02:37:14 PM PDT 24 |
Mar 31 02:42:34 PM PDT 24 |
2518494203 ps |
| T548 |
/workspace/coverage/default/5.sram_ctrl_bijection.1822234545 |
|
|
Mar 31 02:29:17 PM PDT 24 |
Mar 31 02:30:34 PM PDT 24 |
23451978048 ps |
| T549 |
/workspace/coverage/default/20.sram_ctrl_lc_escalation.1018989890 |
|
|
Mar 31 02:31:23 PM PDT 24 |
Mar 31 02:31:33 PM PDT 24 |
1529475328 ps |