| T550 |
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.3900848030 |
|
|
Mar 31 02:29:46 PM PDT 24 |
Mar 31 02:55:26 PM PDT 24 |
3015210707 ps |
| T551 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.64365194 |
|
|
Mar 31 02:36:42 PM PDT 24 |
Mar 31 02:48:17 PM PDT 24 |
5176552995 ps |
| T552 |
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.103420932 |
|
|
Mar 31 02:36:41 PM PDT 24 |
Mar 31 02:39:45 PM PDT 24 |
421506672 ps |
| T553 |
/workspace/coverage/default/7.sram_ctrl_partial_access.434527745 |
|
|
Mar 31 02:29:31 PM PDT 24 |
Mar 31 02:29:33 PM PDT 24 |
294888045 ps |
| T554 |
/workspace/coverage/default/47.sram_ctrl_smoke.973547679 |
|
|
Mar 31 02:37:04 PM PDT 24 |
Mar 31 02:39:40 PM PDT 24 |
143961662 ps |
| T555 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.3198939686 |
|
|
Mar 31 02:29:24 PM PDT 24 |
Mar 31 02:29:25 PM PDT 24 |
29946590 ps |
| T556 |
/workspace/coverage/default/24.sram_ctrl_max_throughput.1640026585 |
|
|
Mar 31 02:32:03 PM PDT 24 |
Mar 31 02:32:15 PM PDT 24 |
637439443 ps |
| T557 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.2516473934 |
|
|
Mar 31 02:36:11 PM PDT 24 |
Mar 31 02:44:07 PM PDT 24 |
3027470275 ps |
| T558 |
/workspace/coverage/default/23.sram_ctrl_access_during_key_req.1277152415 |
|
|
Mar 31 02:31:57 PM PDT 24 |
Mar 31 02:58:31 PM PDT 24 |
24004844008 ps |
| T559 |
/workspace/coverage/default/25.sram_ctrl_executable.1159232226 |
|
|
Mar 31 02:32:27 PM PDT 24 |
Mar 31 02:49:02 PM PDT 24 |
23715465919 ps |
| T560 |
/workspace/coverage/default/2.sram_ctrl_executable.3682677195 |
|
|
Mar 31 02:28:59 PM PDT 24 |
Mar 31 02:47:11 PM PDT 24 |
58575148980 ps |
| T561 |
/workspace/coverage/default/10.sram_ctrl_mem_walk.2294352192 |
|
|
Mar 31 02:29:47 PM PDT 24 |
Mar 31 02:29:59 PM PDT 24 |
2850828288 ps |
| T562 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3086366627 |
|
|
Mar 31 02:36:58 PM PDT 24 |
Mar 31 02:39:08 PM PDT 24 |
551515921 ps |
| T563 |
/workspace/coverage/default/6.sram_ctrl_alert_test.1673773282 |
|
|
Mar 31 02:29:22 PM PDT 24 |
Mar 31 02:29:22 PM PDT 24 |
22502755 ps |
| T564 |
/workspace/coverage/default/42.sram_ctrl_executable.4060407041 |
|
|
Mar 31 02:36:11 PM PDT 24 |
Mar 31 02:53:05 PM PDT 24 |
72984995941 ps |
| T565 |
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.3669350081 |
|
|
Mar 31 02:31:42 PM PDT 24 |
Mar 31 02:36:17 PM PDT 24 |
12159079487 ps |
| T566 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.1174854250 |
|
|
Mar 31 02:36:08 PM PDT 24 |
Mar 31 02:36:12 PM PDT 24 |
47522275 ps |
| T567 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.3204793569 |
|
|
Mar 31 02:30:11 PM PDT 24 |
Mar 31 02:42:37 PM PDT 24 |
8522700389 ps |
| T80 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.308101141 |
|
|
Mar 31 02:29:37 PM PDT 24 |
Mar 31 02:29:40 PM PDT 24 |
191296771 ps |
| T568 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.1748351876 |
|
|
Mar 31 02:29:35 PM PDT 24 |
Mar 31 02:29:41 PM PDT 24 |
2718076498 ps |
| T569 |
/workspace/coverage/default/44.sram_ctrl_bijection.3998835310 |
|
|
Mar 31 02:36:34 PM PDT 24 |
Mar 31 02:37:39 PM PDT 24 |
4587184344 ps |
| T570 |
/workspace/coverage/default/2.sram_ctrl_regwen.363413662 |
|
|
Mar 31 02:28:59 PM PDT 24 |
Mar 31 02:29:18 PM PDT 24 |
3897017004 ps |
| T571 |
/workspace/coverage/default/37.sram_ctrl_partial_access.3538538959 |
|
|
Mar 31 02:35:03 PM PDT 24 |
Mar 31 02:37:42 PM PDT 24 |
1935929012 ps |
| T572 |
/workspace/coverage/default/12.sram_ctrl_bijection.375153462 |
|
|
Mar 31 02:30:00 PM PDT 24 |
Mar 31 02:31:14 PM PDT 24 |
13284218045 ps |
| T573 |
/workspace/coverage/default/10.sram_ctrl_bijection.378024135 |
|
|
Mar 31 02:29:40 PM PDT 24 |
Mar 31 02:31:03 PM PDT 24 |
18281816682 ps |
| T574 |
/workspace/coverage/default/47.sram_ctrl_bijection.3756078489 |
|
|
Mar 31 02:37:05 PM PDT 24 |
Mar 31 02:37:45 PM PDT 24 |
1656357085 ps |
| T575 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.181736954 |
|
|
Mar 31 02:32:26 PM PDT 24 |
Mar 31 02:32:27 PM PDT 24 |
90339624 ps |
| T576 |
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.2838963811 |
|
|
Mar 31 02:36:25 PM PDT 24 |
Mar 31 02:36:27 PM PDT 24 |
43770648 ps |
| T577 |
/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1318699153 |
|
|
Mar 31 02:30:10 PM PDT 24 |
Mar 31 02:32:35 PM PDT 24 |
877089124 ps |
| T578 |
/workspace/coverage/default/13.sram_ctrl_bijection.3259850781 |
|
|
Mar 31 02:30:11 PM PDT 24 |
Mar 31 02:30:29 PM PDT 24 |
1113737209 ps |
| T579 |
/workspace/coverage/default/7.sram_ctrl_bijection.2794907260 |
|
|
Mar 31 02:29:26 PM PDT 24 |
Mar 31 02:30:27 PM PDT 24 |
2887612005 ps |
| T580 |
/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1962217779 |
|
|
Mar 31 02:35:20 PM PDT 24 |
Mar 31 02:38:26 PM PDT 24 |
1776293149 ps |
| T581 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.1403118 |
|
|
Mar 31 02:30:24 PM PDT 24 |
Mar 31 02:30:33 PM PDT 24 |
462985674 ps |
| T582 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.4204538698 |
|
|
Mar 31 02:34:59 PM PDT 24 |
Mar 31 02:47:32 PM PDT 24 |
2144885548 ps |
| T583 |
/workspace/coverage/default/29.sram_ctrl_stress_all.3778464695 |
|
|
Mar 31 02:33:24 PM PDT 24 |
Mar 31 03:42:45 PM PDT 24 |
180182222547 ps |
| T584 |
/workspace/coverage/default/23.sram_ctrl_smoke.2371854752 |
|
|
Mar 31 02:31:48 PM PDT 24 |
Mar 31 02:33:03 PM PDT 24 |
1999483452 ps |
| T585 |
/workspace/coverage/default/12.sram_ctrl_executable.1481263801 |
|
|
Mar 31 02:30:02 PM PDT 24 |
Mar 31 02:35:43 PM PDT 24 |
6633087762 ps |
| T586 |
/workspace/coverage/default/24.sram_ctrl_regwen.3557905397 |
|
|
Mar 31 02:32:10 PM PDT 24 |
Mar 31 02:46:18 PM PDT 24 |
3373239707 ps |
| T587 |
/workspace/coverage/default/1.sram_ctrl_bijection.2499010525 |
|
|
Mar 31 02:28:58 PM PDT 24 |
Mar 31 02:30:02 PM PDT 24 |
1002669514 ps |
| T588 |
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.538699016 |
|
|
Mar 31 02:29:34 PM PDT 24 |
Mar 31 02:30:56 PM PDT 24 |
134439745 ps |
| T589 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.494132250 |
|
|
Mar 31 02:35:55 PM PDT 24 |
Mar 31 02:42:21 PM PDT 24 |
5393236363 ps |
| T590 |
/workspace/coverage/default/26.sram_ctrl_mem_partial_access.2422138870 |
|
|
Mar 31 02:32:33 PM PDT 24 |
Mar 31 02:32:38 PM PDT 24 |
174813758 ps |
| T591 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.1434734123 |
|
|
Mar 31 02:29:18 PM PDT 24 |
Mar 31 02:49:37 PM PDT 24 |
71621342778 ps |
| T25 |
/workspace/coverage/default/3.sram_ctrl_sec_cm.2330059998 |
|
|
Mar 31 02:29:13 PM PDT 24 |
Mar 31 02:29:16 PM PDT 24 |
357988191 ps |
| T592 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3178532232 |
|
|
Mar 31 02:29:40 PM PDT 24 |
Mar 31 02:34:22 PM PDT 24 |
16266838196 ps |
| T593 |
/workspace/coverage/default/39.sram_ctrl_stress_pipeline.2410688458 |
|
|
Mar 31 02:35:28 PM PDT 24 |
Mar 31 02:40:35 PM PDT 24 |
3162051908 ps |
| T594 |
/workspace/coverage/default/14.sram_ctrl_stress_all.1335654554 |
|
|
Mar 31 02:30:24 PM PDT 24 |
Mar 31 03:16:58 PM PDT 24 |
180609794968 ps |
| T595 |
/workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.189470019 |
|
|
Mar 31 02:32:10 PM PDT 24 |
Mar 31 02:35:48 PM PDT 24 |
13279277020 ps |
| T596 |
/workspace/coverage/default/9.sram_ctrl_multiple_keys.3209733365 |
|
|
Mar 31 02:29:34 PM PDT 24 |
Mar 31 02:49:27 PM PDT 24 |
11722392638 ps |
| T597 |
/workspace/coverage/default/38.sram_ctrl_bijection.2798381568 |
|
|
Mar 31 02:35:14 PM PDT 24 |
Mar 31 02:35:38 PM PDT 24 |
1601903264 ps |
| T598 |
/workspace/coverage/default/30.sram_ctrl_bijection.3565518360 |
|
|
Mar 31 02:33:24 PM PDT 24 |
Mar 31 02:34:21 PM PDT 24 |
14492382456 ps |
| T599 |
/workspace/coverage/default/21.sram_ctrl_mem_walk.3175093749 |
|
|
Mar 31 02:31:33 PM PDT 24 |
Mar 31 02:31:38 PM PDT 24 |
148039345 ps |
| T600 |
/workspace/coverage/default/35.sram_ctrl_lc_escalation.359682648 |
|
|
Mar 31 02:34:36 PM PDT 24 |
Mar 31 02:34:38 PM PDT 24 |
373303444 ps |
| T601 |
/workspace/coverage/default/2.sram_ctrl_stress_pipeline.631094193 |
|
|
Mar 31 02:28:58 PM PDT 24 |
Mar 31 02:34:43 PM PDT 24 |
7301034914 ps |
| T104 |
/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.419686200 |
|
|
Mar 31 02:33:21 PM PDT 24 |
Mar 31 02:33:42 PM PDT 24 |
1348970730 ps |
| T602 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.781794502 |
|
|
Mar 31 02:31:04 PM PDT 24 |
Mar 31 02:31:10 PM PDT 24 |
2070988746 ps |
| T603 |
/workspace/coverage/default/30.sram_ctrl_smoke.1616193105 |
|
|
Mar 31 02:33:26 PM PDT 24 |
Mar 31 02:34:59 PM PDT 24 |
608355276 ps |
| T604 |
/workspace/coverage/default/44.sram_ctrl_stress_all.4091897064 |
|
|
Mar 31 02:36:42 PM PDT 24 |
Mar 31 03:27:58 PM PDT 24 |
40263333181 ps |
| T605 |
/workspace/coverage/default/14.sram_ctrl_partial_access.3806384430 |
|
|
Mar 31 02:30:21 PM PDT 24 |
Mar 31 02:30:27 PM PDT 24 |
123540406 ps |
| T606 |
/workspace/coverage/default/27.sram_ctrl_lc_escalation.3154577823 |
|
|
Mar 31 02:32:39 PM PDT 24 |
Mar 31 02:32:42 PM PDT 24 |
141196900 ps |
| T607 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.2306017964 |
|
|
Mar 31 02:36:52 PM PDT 24 |
Mar 31 02:39:51 PM PDT 24 |
28773036754 ps |
| T608 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.3701687466 |
|
|
Mar 31 02:29:25 PM PDT 24 |
Mar 31 02:29:28 PM PDT 24 |
380468845 ps |
| T609 |
/workspace/coverage/default/26.sram_ctrl_max_throughput.1117457093 |
|
|
Mar 31 02:32:35 PM PDT 24 |
Mar 31 02:33:23 PM PDT 24 |
412736487 ps |
| T610 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.3166842627 |
|
|
Mar 31 02:30:05 PM PDT 24 |
Mar 31 02:34:15 PM PDT 24 |
1445197262 ps |
| T611 |
/workspace/coverage/default/29.sram_ctrl_bijection.1278452793 |
|
|
Mar 31 02:33:23 PM PDT 24 |
Mar 31 02:33:47 PM PDT 24 |
4080640370 ps |
| T612 |
/workspace/coverage/default/28.sram_ctrl_multiple_keys.2373847499 |
|
|
Mar 31 02:33:14 PM PDT 24 |
Mar 31 02:37:18 PM PDT 24 |
9082121231 ps |
| T613 |
/workspace/coverage/default/34.sram_ctrl_max_throughput.2773668122 |
|
|
Mar 31 02:34:19 PM PDT 24 |
Mar 31 02:34:33 PM PDT 24 |
73987949 ps |
| T614 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.3346650406 |
|
|
Mar 31 02:32:38 PM PDT 24 |
Mar 31 02:43:22 PM PDT 24 |
6109145074 ps |
| T615 |
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.2523475211 |
|
|
Mar 31 02:29:39 PM PDT 24 |
Mar 31 02:33:31 PM PDT 24 |
1903212547 ps |
| T616 |
/workspace/coverage/default/0.sram_ctrl_mem_walk.3062496123 |
|
|
Mar 31 02:28:53 PM PDT 24 |
Mar 31 02:29:01 PM PDT 24 |
453368513 ps |
| T617 |
/workspace/coverage/default/26.sram_ctrl_smoke.3334494169 |
|
|
Mar 31 02:32:27 PM PDT 24 |
Mar 31 02:32:39 PM PDT 24 |
677358848 ps |
| T618 |
/workspace/coverage/default/40.sram_ctrl_access_during_key_req.860288253 |
|
|
Mar 31 02:35:46 PM PDT 24 |
Mar 31 03:08:08 PM PDT 24 |
56507111210 ps |
| T619 |
/workspace/coverage/default/35.sram_ctrl_access_during_key_req.1206815557 |
|
|
Mar 31 02:34:35 PM PDT 24 |
Mar 31 02:53:27 PM PDT 24 |
18526525090 ps |
| T620 |
/workspace/coverage/default/41.sram_ctrl_mem_walk.2218789573 |
|
|
Mar 31 02:36:00 PM PDT 24 |
Mar 31 02:36:09 PM PDT 24 |
546265352 ps |
| T621 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.2240587000 |
|
|
Mar 31 02:30:11 PM PDT 24 |
Mar 31 02:30:16 PM PDT 24 |
1272043138 ps |
| T622 |
/workspace/coverage/default/5.sram_ctrl_alert_test.3425258881 |
|
|
Mar 31 02:29:23 PM PDT 24 |
Mar 31 02:29:23 PM PDT 24 |
12076372 ps |
| T623 |
/workspace/coverage/default/42.sram_ctrl_alert_test.3997483775 |
|
|
Mar 31 02:36:18 PM PDT 24 |
Mar 31 02:36:20 PM PDT 24 |
21059935 ps |
| T624 |
/workspace/coverage/default/35.sram_ctrl_executable.875239138 |
|
|
Mar 31 02:34:37 PM PDT 24 |
Mar 31 02:49:48 PM PDT 24 |
24841436459 ps |
| T625 |
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.271329062 |
|
|
Mar 31 02:29:52 PM PDT 24 |
Mar 31 02:35:06 PM PDT 24 |
6331323851 ps |
| T626 |
/workspace/coverage/default/48.sram_ctrl_partial_access.2412990718 |
|
|
Mar 31 02:37:22 PM PDT 24 |
Mar 31 02:37:25 PM PDT 24 |
115641838 ps |
| T627 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.751393394 |
|
|
Mar 31 02:36:00 PM PDT 24 |
Mar 31 02:36:03 PM PDT 24 |
156088011 ps |
| T628 |
/workspace/coverage/default/14.sram_ctrl_smoke.2497041426 |
|
|
Mar 31 02:30:20 PM PDT 24 |
Mar 31 02:30:27 PM PDT 24 |
1021756077 ps |
| T629 |
/workspace/coverage/default/25.sram_ctrl_bijection.3879205418 |
|
|
Mar 31 02:32:24 PM PDT 24 |
Mar 31 02:33:19 PM PDT 24 |
3024642185 ps |
| T630 |
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.612105621 |
|
|
Mar 31 02:37:04 PM PDT 24 |
Mar 31 02:42:59 PM PDT 24 |
55299940021 ps |
| T631 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.3613109167 |
|
|
Mar 31 02:35:40 PM PDT 24 |
Mar 31 02:39:51 PM PDT 24 |
17468081635 ps |
| T632 |
/workspace/coverage/default/34.sram_ctrl_regwen.1280342578 |
|
|
Mar 31 02:34:20 PM PDT 24 |
Mar 31 02:34:38 PM PDT 24 |
904243457 ps |
| T633 |
/workspace/coverage/default/31.sram_ctrl_partial_access.1255767751 |
|
|
Mar 31 02:33:32 PM PDT 24 |
Mar 31 02:35:57 PM PDT 24 |
2053961955 ps |
| T634 |
/workspace/coverage/default/1.sram_ctrl_smoke.1470131514 |
|
|
Mar 31 02:28:53 PM PDT 24 |
Mar 31 02:29:22 PM PDT 24 |
354215720 ps |
| T105 |
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.2757712658 |
|
|
Mar 31 02:34:16 PM PDT 24 |
Mar 31 02:35:39 PM PDT 24 |
2100450478 ps |
| T635 |
/workspace/coverage/default/15.sram_ctrl_mem_walk.2138134539 |
|
|
Mar 31 02:30:30 PM PDT 24 |
Mar 31 02:30:40 PM PDT 24 |
674844293 ps |
| T636 |
/workspace/coverage/default/44.sram_ctrl_smoke.1064628519 |
|
|
Mar 31 02:36:32 PM PDT 24 |
Mar 31 02:37:45 PM PDT 24 |
1794451151 ps |
| T637 |
/workspace/coverage/default/31.sram_ctrl_stress_all.591388810 |
|
|
Mar 31 02:33:45 PM PDT 24 |
Mar 31 03:06:07 PM PDT 24 |
6523855409 ps |
| T638 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.1324411368 |
|
|
Mar 31 02:34:14 PM PDT 24 |
Mar 31 02:37:46 PM PDT 24 |
2230785312 ps |
| T639 |
/workspace/coverage/default/0.sram_ctrl_ram_cfg.1630554846 |
|
|
Mar 31 02:28:53 PM PDT 24 |
Mar 31 02:28:54 PM PDT 24 |
45024418 ps |
| T640 |
/workspace/coverage/default/49.sram_ctrl_lc_escalation.1298645897 |
|
|
Mar 31 02:37:30 PM PDT 24 |
Mar 31 02:37:33 PM PDT 24 |
746990131 ps |
| T641 |
/workspace/coverage/default/3.sram_ctrl_access_during_key_req.1209229820 |
|
|
Mar 31 02:29:09 PM PDT 24 |
Mar 31 02:41:16 PM PDT 24 |
2868000048 ps |
| T642 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.740259972 |
|
|
Mar 31 02:30:24 PM PDT 24 |
Mar 31 02:30:28 PM PDT 24 |
225155159 ps |
| T106 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1320422017 |
|
|
Mar 31 02:30:25 PM PDT 24 |
Mar 31 02:32:38 PM PDT 24 |
6445600725 ps |
| T643 |
/workspace/coverage/default/33.sram_ctrl_regwen.2768220695 |
|
|
Mar 31 02:34:10 PM PDT 24 |
Mar 31 02:42:53 PM PDT 24 |
13200001782 ps |
| T644 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.4281527565 |
|
|
Mar 31 02:30:18 PM PDT 24 |
Mar 31 02:31:54 PM PDT 24 |
125715791 ps |
| T645 |
/workspace/coverage/default/19.sram_ctrl_smoke.2259340073 |
|
|
Mar 31 02:31:04 PM PDT 24 |
Mar 31 02:31:06 PM PDT 24 |
366500031 ps |
| T646 |
/workspace/coverage/default/23.sram_ctrl_stress_all.268341237 |
|
|
Mar 31 02:31:55 PM PDT 24 |
Mar 31 03:05:02 PM PDT 24 |
78204344388 ps |
| T647 |
/workspace/coverage/default/33.sram_ctrl_executable.1443860303 |
|
|
Mar 31 02:34:06 PM PDT 24 |
Mar 31 02:51:09 PM PDT 24 |
14181314511 ps |
| T35 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.2891808810 |
|
|
Mar 31 02:29:04 PM PDT 24 |
Mar 31 02:29:06 PM PDT 24 |
344392508 ps |
| T648 |
/workspace/coverage/default/29.sram_ctrl_lc_escalation.3963152965 |
|
|
Mar 31 02:33:23 PM PDT 24 |
Mar 31 02:33:30 PM PDT 24 |
1265087205 ps |
| T649 |
/workspace/coverage/default/10.sram_ctrl_smoke.4048072943 |
|
|
Mar 31 02:29:41 PM PDT 24 |
Mar 31 02:32:15 PM PDT 24 |
521985759 ps |
| T107 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.236806042 |
|
|
Mar 31 02:30:46 PM PDT 24 |
Mar 31 02:30:56 PM PDT 24 |
674445898 ps |
| T650 |
/workspace/coverage/default/25.sram_ctrl_partial_access.353548576 |
|
|
Mar 31 02:32:21 PM PDT 24 |
Mar 31 02:32:42 PM PDT 24 |
550955109 ps |
| T651 |
/workspace/coverage/default/15.sram_ctrl_lc_escalation.1710215972 |
|
|
Mar 31 02:30:24 PM PDT 24 |
Mar 31 02:30:28 PM PDT 24 |
314062550 ps |
| T652 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.2990506611 |
|
|
Mar 31 02:31:34 PM PDT 24 |
Mar 31 02:31:59 PM PDT 24 |
185890060 ps |
| T653 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.4022178745 |
|
|
Mar 31 02:32:04 PM PDT 24 |
Mar 31 02:48:15 PM PDT 24 |
3316551871 ps |
| T654 |
/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.1501596728 |
|
|
Mar 31 02:30:37 PM PDT 24 |
Mar 31 02:33:42 PM PDT 24 |
32150434146 ps |
| T655 |
/workspace/coverage/default/38.sram_ctrl_ram_cfg.2956519252 |
|
|
Mar 31 02:35:20 PM PDT 24 |
Mar 31 02:35:21 PM PDT 24 |
44279597 ps |
| T656 |
/workspace/coverage/default/20.sram_ctrl_mem_partial_access.2146615189 |
|
|
Mar 31 02:31:29 PM PDT 24 |
Mar 31 02:31:34 PM PDT 24 |
65144327 ps |
| T657 |
/workspace/coverage/default/38.sram_ctrl_executable.386020998 |
|
|
Mar 31 02:35:20 PM PDT 24 |
Mar 31 02:46:39 PM PDT 24 |
3393407831 ps |
| T658 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.4057413602 |
|
|
Mar 31 02:28:58 PM PDT 24 |
Mar 31 02:29:10 PM PDT 24 |
149836284 ps |
| T659 |
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.265025287 |
|
|
Mar 31 02:29:59 PM PDT 24 |
Mar 31 02:32:34 PM PDT 24 |
3092247231 ps |
| T660 |
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.3847068318 |
|
|
Mar 31 02:34:05 PM PDT 24 |
Mar 31 02:36:43 PM PDT 24 |
1721369211 ps |
| T661 |
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.4179584386 |
|
|
Mar 31 02:32:25 PM PDT 24 |
Mar 31 02:45:23 PM PDT 24 |
8701633796 ps |
| T662 |
/workspace/coverage/default/17.sram_ctrl_access_during_key_req.2276730994 |
|
|
Mar 31 02:30:50 PM PDT 24 |
Mar 31 02:51:01 PM PDT 24 |
6389689896 ps |
| T663 |
/workspace/coverage/default/33.sram_ctrl_alert_test.4277507583 |
|
|
Mar 31 02:34:13 PM PDT 24 |
Mar 31 02:34:14 PM PDT 24 |
27667725 ps |
| T664 |
/workspace/coverage/default/31.sram_ctrl_executable.4115722299 |
|
|
Mar 31 02:33:40 PM PDT 24 |
Mar 31 02:36:16 PM PDT 24 |
1028802509 ps |
| T665 |
/workspace/coverage/default/40.sram_ctrl_stress_all.804465741 |
|
|
Mar 31 02:35:54 PM PDT 24 |
Mar 31 03:43:16 PM PDT 24 |
47332804287 ps |
| T666 |
/workspace/coverage/default/27.sram_ctrl_access_during_key_req.2795746408 |
|
|
Mar 31 02:32:38 PM PDT 24 |
Mar 31 02:40:42 PM PDT 24 |
6650807483 ps |
| T667 |
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.221084178 |
|
|
Mar 31 02:29:31 PM PDT 24 |
Mar 31 02:45:06 PM PDT 24 |
17443608813 ps |
| T668 |
/workspace/coverage/default/32.sram_ctrl_access_during_key_req.383772907 |
|
|
Mar 31 02:33:56 PM PDT 24 |
Mar 31 02:50:17 PM PDT 24 |
4552541230 ps |
| T669 |
/workspace/coverage/default/8.sram_ctrl_executable.2149022274 |
|
|
Mar 31 02:29:34 PM PDT 24 |
Mar 31 02:52:47 PM PDT 24 |
22164540637 ps |
| T670 |
/workspace/coverage/default/22.sram_ctrl_stress_all.2409746366 |
|
|
Mar 31 02:31:50 PM PDT 24 |
Mar 31 03:34:25 PM PDT 24 |
48609282372 ps |
| T671 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.1396122969 |
|
|
Mar 31 02:30:19 PM PDT 24 |
Mar 31 02:30:27 PM PDT 24 |
649317757 ps |
| T672 |
/workspace/coverage/default/49.sram_ctrl_executable.2909800077 |
|
|
Mar 31 02:37:30 PM PDT 24 |
Mar 31 02:46:30 PM PDT 24 |
7150267337 ps |
| T673 |
/workspace/coverage/default/32.sram_ctrl_executable.3379538184 |
|
|
Mar 31 02:33:57 PM PDT 24 |
Mar 31 02:54:14 PM PDT 24 |
31287283465 ps |
| T674 |
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.2447590737 |
|
|
Mar 31 02:29:41 PM PDT 24 |
Mar 31 02:32:11 PM PDT 24 |
1655716407 ps |
| T675 |
/workspace/coverage/default/3.sram_ctrl_bijection.3187676408 |
|
|
Mar 31 02:29:03 PM PDT 24 |
Mar 31 02:29:32 PM PDT 24 |
1397470790 ps |
| T676 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.2237802072 |
|
|
Mar 31 02:35:00 PM PDT 24 |
Mar 31 02:39:35 PM PDT 24 |
2947351430 ps |
| T677 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.840061281 |
|
|
Mar 31 02:34:35 PM PDT 24 |
Mar 31 02:35:24 PM PDT 24 |
189533094 ps |
| T678 |
/workspace/coverage/default/21.sram_ctrl_smoke.786994963 |
|
|
Mar 31 02:31:29 PM PDT 24 |
Mar 31 02:33:08 PM PDT 24 |
2112637874 ps |
| T679 |
/workspace/coverage/default/46.sram_ctrl_executable.1485997999 |
|
|
Mar 31 02:36:58 PM PDT 24 |
Mar 31 02:51:09 PM PDT 24 |
13947926115 ps |
| T680 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.1797890890 |
|
|
Mar 31 02:36:53 PM PDT 24 |
Mar 31 02:41:20 PM PDT 24 |
12873159858 ps |
| T681 |
/workspace/coverage/default/9.sram_ctrl_regwen.2848117065 |
|
|
Mar 31 02:29:36 PM PDT 24 |
Mar 31 02:45:16 PM PDT 24 |
3163463400 ps |
| T682 |
/workspace/coverage/default/10.sram_ctrl_lc_escalation.3568627894 |
|
|
Mar 31 02:29:43 PM PDT 24 |
Mar 31 02:29:51 PM PDT 24 |
2807538095 ps |
| T683 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.972836365 |
|
|
Mar 31 02:29:17 PM PDT 24 |
Mar 31 02:29:21 PM PDT 24 |
233248233 ps |
| T684 |
/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.1993451418 |
|
|
Mar 31 02:34:51 PM PDT 24 |
Mar 31 02:35:21 PM PDT 24 |
1265284375 ps |
| T685 |
/workspace/coverage/default/45.sram_ctrl_mem_walk.3215739104 |
|
|
Mar 31 02:36:48 PM PDT 24 |
Mar 31 02:36:59 PM PDT 24 |
2269429340 ps |
| T686 |
/workspace/coverage/default/3.sram_ctrl_max_throughput.3259126664 |
|
|
Mar 31 02:29:05 PM PDT 24 |
Mar 31 02:30:16 PM PDT 24 |
420734051 ps |
| T687 |
/workspace/coverage/default/5.sram_ctrl_partial_access.84767190 |
|
|
Mar 31 02:29:17 PM PDT 24 |
Mar 31 02:29:31 PM PDT 24 |
1796763905 ps |
| T688 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3079125940 |
|
|
Mar 31 02:37:30 PM PDT 24 |
Mar 31 02:39:50 PM PDT 24 |
578244275 ps |
| T689 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.1162105811 |
|
|
Mar 31 02:32:03 PM PDT 24 |
Mar 31 02:32:05 PM PDT 24 |
536718597 ps |
| T690 |
/workspace/coverage/default/32.sram_ctrl_mem_partial_access.2587975478 |
|
|
Mar 31 02:33:58 PM PDT 24 |
Mar 31 02:34:03 PM PDT 24 |
172645571 ps |
| T691 |
/workspace/coverage/default/1.sram_ctrl_multiple_keys.2270113729 |
|
|
Mar 31 02:28:53 PM PDT 24 |
Mar 31 02:44:54 PM PDT 24 |
10740906170 ps |
| T692 |
/workspace/coverage/default/43.sram_ctrl_bijection.3508486621 |
|
|
Mar 31 02:36:24 PM PDT 24 |
Mar 31 02:36:46 PM PDT 24 |
1817748101 ps |
| T693 |
/workspace/coverage/default/16.sram_ctrl_max_throughput.3117726437 |
|
|
Mar 31 02:30:46 PM PDT 24 |
Mar 31 02:31:14 PM PDT 24 |
98235995 ps |
| T694 |
/workspace/coverage/default/26.sram_ctrl_stress_all.963413061 |
|
|
Mar 31 02:32:33 PM PDT 24 |
Mar 31 04:45:41 PM PDT 24 |
59166520479 ps |
| T695 |
/workspace/coverage/default/30.sram_ctrl_alert_test.3178246660 |
|
|
Mar 31 02:33:26 PM PDT 24 |
Mar 31 02:33:27 PM PDT 24 |
63768258 ps |
| T696 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.4205802340 |
|
|
Mar 31 02:35:21 PM PDT 24 |
Mar 31 02:35:27 PM PDT 24 |
421688093 ps |
| T697 |
/workspace/coverage/default/17.sram_ctrl_regwen.1831520366 |
|
|
Mar 31 02:30:51 PM PDT 24 |
Mar 31 02:45:00 PM PDT 24 |
2280293005 ps |
| T698 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.4021345589 |
|
|
Mar 31 02:32:31 PM PDT 24 |
Mar 31 02:32:32 PM PDT 24 |
211406079 ps |
| T699 |
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.1761397611 |
|
|
Mar 31 02:36:52 PM PDT 24 |
Mar 31 02:45:12 PM PDT 24 |
1813445531 ps |
| T700 |
/workspace/coverage/default/45.sram_ctrl_stress_all.2267346561 |
|
|
Mar 31 02:36:52 PM PDT 24 |
Mar 31 02:58:13 PM PDT 24 |
33021467724 ps |
| T701 |
/workspace/coverage/default/26.sram_ctrl_lc_escalation.1370895022 |
|
|
Mar 31 02:32:32 PM PDT 24 |
Mar 31 02:32:38 PM PDT 24 |
689701770 ps |
| T702 |
/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.1149967011 |
|
|
Mar 31 02:30:53 PM PDT 24 |
Mar 31 02:31:52 PM PDT 24 |
120045305 ps |
| T703 |
/workspace/coverage/default/17.sram_ctrl_max_throughput.4077083720 |
|
|
Mar 31 02:30:50 PM PDT 24 |
Mar 31 02:32:09 PM PDT 24 |
443254097 ps |
| T704 |
/workspace/coverage/default/13.sram_ctrl_executable.1789701761 |
|
|
Mar 31 02:30:10 PM PDT 24 |
Mar 31 02:40:36 PM PDT 24 |
5848182566 ps |
| T705 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.3919233384 |
|
|
Mar 31 02:31:56 PM PDT 24 |
Mar 31 02:32:02 PM PDT 24 |
551914197 ps |
| T706 |
/workspace/coverage/default/4.sram_ctrl_mem_walk.1418343093 |
|
|
Mar 31 02:29:18 PM PDT 24 |
Mar 31 02:29:23 PM PDT 24 |
239290538 ps |
| T707 |
/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.976548582 |
|
|
Mar 31 02:28:58 PM PDT 24 |
Mar 31 02:36:01 PM PDT 24 |
5762066478 ps |
| T708 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.4021977692 |
|
|
Mar 31 02:30:24 PM PDT 24 |
Mar 31 02:36:34 PM PDT 24 |
3967746518 ps |
| T709 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.1874357762 |
|
|
Mar 31 02:32:11 PM PDT 24 |
Mar 31 02:32:12 PM PDT 24 |
43696824 ps |
| T710 |
/workspace/coverage/default/22.sram_ctrl_regwen.3807710693 |
|
|
Mar 31 02:31:48 PM PDT 24 |
Mar 31 02:47:40 PM PDT 24 |
8559253883 ps |
| T711 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.1612430747 |
|
|
Mar 31 02:34:52 PM PDT 24 |
Mar 31 02:48:04 PM PDT 24 |
17412214511 ps |
| T712 |
/workspace/coverage/default/3.sram_ctrl_smoke.2490977002 |
|
|
Mar 31 02:29:03 PM PDT 24 |
Mar 31 02:29:09 PM PDT 24 |
1765604757 ps |
| T713 |
/workspace/coverage/default/45.sram_ctrl_bijection.2197204295 |
|
|
Mar 31 02:36:52 PM PDT 24 |
Mar 31 02:37:34 PM PDT 24 |
9573765700 ps |
| T714 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.2189993094 |
|
|
Mar 31 02:29:28 PM PDT 24 |
Mar 31 02:29:33 PM PDT 24 |
579901009 ps |
| T715 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.4161849359 |
|
|
Mar 31 02:29:31 PM PDT 24 |
Mar 31 02:33:25 PM PDT 24 |
13412219921 ps |
| T716 |
/workspace/coverage/default/47.sram_ctrl_mem_walk.2681945480 |
|
|
Mar 31 02:37:13 PM PDT 24 |
Mar 31 02:37:19 PM PDT 24 |
1183276954 ps |
| T717 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.2356115140 |
|
|
Mar 31 02:33:16 PM PDT 24 |
Mar 31 02:33:17 PM PDT 24 |
35525522 ps |
| T718 |
/workspace/coverage/default/11.sram_ctrl_smoke.1683740917 |
|
|
Mar 31 02:29:45 PM PDT 24 |
Mar 31 02:29:48 PM PDT 24 |
174238855 ps |
| T719 |
/workspace/coverage/default/22.sram_ctrl_bijection.367570167 |
|
|
Mar 31 02:31:43 PM PDT 24 |
Mar 31 02:32:11 PM PDT 24 |
3302169687 ps |
| T720 |
/workspace/coverage/default/41.sram_ctrl_stress_pipeline.2114910571 |
|
|
Mar 31 02:36:01 PM PDT 24 |
Mar 31 02:39:27 PM PDT 24 |
2234811367 ps |
| T721 |
/workspace/coverage/default/9.sram_ctrl_partial_access.1613051087 |
|
|
Mar 31 02:29:36 PM PDT 24 |
Mar 31 02:29:38 PM PDT 24 |
1075256617 ps |
| T722 |
/workspace/coverage/default/33.sram_ctrl_access_during_key_req.2538914157 |
|
|
Mar 31 02:34:07 PM PDT 24 |
Mar 31 02:46:58 PM PDT 24 |
47395070707 ps |
| T723 |
/workspace/coverage/default/37.sram_ctrl_mem_walk.956141777 |
|
|
Mar 31 02:35:10 PM PDT 24 |
Mar 31 02:35:20 PM PDT 24 |
599905007 ps |
| T724 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.2775879812 |
|
|
Mar 31 02:31:40 PM PDT 24 |
Mar 31 02:32:48 PM PDT 24 |
769708166 ps |
| T725 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.3211729696 |
|
|
Mar 31 02:36:40 PM PDT 24 |
Mar 31 02:36:41 PM PDT 24 |
83976018 ps |
| T726 |
/workspace/coverage/default/19.sram_ctrl_stress_pipeline.1111388816 |
|
|
Mar 31 02:31:04 PM PDT 24 |
Mar 31 02:35:20 PM PDT 24 |
11754523846 ps |
| T727 |
/workspace/coverage/default/48.sram_ctrl_alert_test.722779459 |
|
|
Mar 31 02:37:24 PM PDT 24 |
Mar 31 02:37:27 PM PDT 24 |
13659202 ps |
| T728 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.800251096 |
|
|
Mar 31 02:31:17 PM PDT 24 |
Mar 31 02:34:35 PM PDT 24 |
8709445144 ps |
| T729 |
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1669369097 |
|
|
Mar 31 02:36:52 PM PDT 24 |
Mar 31 02:39:37 PM PDT 24 |
767632700 ps |
| T730 |
/workspace/coverage/default/18.sram_ctrl_mem_partial_access.2540714455 |
|
|
Mar 31 02:31:03 PM PDT 24 |
Mar 31 02:31:08 PM PDT 24 |
773602350 ps |
| T731 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.4287396559 |
|
|
Mar 31 02:36:26 PM PDT 24 |
Mar 31 02:36:34 PM PDT 24 |
138709943 ps |
| T732 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.272243464 |
|
|
Mar 31 02:29:01 PM PDT 24 |
Mar 31 02:29:49 PM PDT 24 |
201467006 ps |
| T733 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3797643495 |
|
|
Mar 31 02:28:51 PM PDT 24 |
Mar 31 02:31:01 PM PDT 24 |
563680250 ps |
| T734 |
/workspace/coverage/default/19.sram_ctrl_partial_access.436217422 |
|
|
Mar 31 02:31:04 PM PDT 24 |
Mar 31 02:31:15 PM PDT 24 |
222009593 ps |
| T735 |
/workspace/coverage/default/45.sram_ctrl_lc_escalation.1480812209 |
|
|
Mar 31 02:36:46 PM PDT 24 |
Mar 31 02:36:51 PM PDT 24 |
1739812780 ps |
| T736 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.1234369133 |
|
|
Mar 31 02:31:29 PM PDT 24 |
Mar 31 02:41:52 PM PDT 24 |
12731574075 ps |
| T737 |
/workspace/coverage/default/3.sram_ctrl_ram_cfg.1202514656 |
|
|
Mar 31 02:29:03 PM PDT 24 |
Mar 31 02:29:04 PM PDT 24 |
167720350 ps |
| T738 |
/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.3074010023 |
|
|
Mar 31 02:33:34 PM PDT 24 |
Mar 31 02:34:38 PM PDT 24 |
235306823 ps |
| T739 |
/workspace/coverage/default/24.sram_ctrl_partial_access.3552296133 |
|
|
Mar 31 02:32:03 PM PDT 24 |
Mar 31 02:34:19 PM PDT 24 |
2899396017 ps |
| T740 |
/workspace/coverage/default/17.sram_ctrl_smoke.1621349335 |
|
|
Mar 31 02:30:44 PM PDT 24 |
Mar 31 02:30:49 PM PDT 24 |
834510570 ps |
| T741 |
/workspace/coverage/default/8.sram_ctrl_stress_all.1654518074 |
|
|
Mar 31 02:29:37 PM PDT 24 |
Mar 31 02:53:00 PM PDT 24 |
18110807380 ps |
| T742 |
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1853136455 |
|
|
Mar 31 02:29:30 PM PDT 24 |
Mar 31 02:33:36 PM PDT 24 |
14114616682 ps |
| T743 |
/workspace/coverage/default/47.sram_ctrl_executable.17809562 |
|
|
Mar 31 02:37:12 PM PDT 24 |
Mar 31 02:48:22 PM PDT 24 |
3253320775 ps |
| T744 |
/workspace/coverage/default/43.sram_ctrl_regwen.1877539218 |
|
|
Mar 31 02:36:25 PM PDT 24 |
Mar 31 02:43:59 PM PDT 24 |
9083022973 ps |
| T745 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.1891183811 |
|
|
Mar 31 02:29:48 PM PDT 24 |
Mar 31 02:33:14 PM PDT 24 |
11670638847 ps |
| T746 |
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.1355099491 |
|
|
Mar 31 02:28:59 PM PDT 24 |
Mar 31 02:29:02 PM PDT 24 |
242833571 ps |
| T747 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.3284977822 |
|
|
Mar 31 02:37:12 PM PDT 24 |
Mar 31 02:37:22 PM PDT 24 |
65390442 ps |
| T748 |
/workspace/coverage/default/16.sram_ctrl_partial_access.2591203600 |
|
|
Mar 31 02:30:38 PM PDT 24 |
Mar 31 02:33:18 PM PDT 24 |
219607309 ps |
| T749 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.2615743670 |
|
|
Mar 31 02:36:29 PM PDT 24 |
Mar 31 02:36:30 PM PDT 24 |
31028771 ps |
| T750 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.3715960485 |
|
|
Mar 31 02:36:48 PM PDT 24 |
Mar 31 02:42:57 PM PDT 24 |
14264929575 ps |
| T751 |
/workspace/coverage/default/15.sram_ctrl_smoke.1587568017 |
|
|
Mar 31 02:30:24 PM PDT 24 |
Mar 31 02:30:25 PM PDT 24 |
43199465 ps |
| T752 |
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.2302481594 |
|
|
Mar 31 02:31:42 PM PDT 24 |
Mar 31 02:32:40 PM PDT 24 |
133005762 ps |
| T753 |
/workspace/coverage/default/12.sram_ctrl_regwen.2062389032 |
|
|
Mar 31 02:30:05 PM PDT 24 |
Mar 31 02:38:25 PM PDT 24 |
49608959088 ps |
| T754 |
/workspace/coverage/default/1.sram_ctrl_executable.60300558 |
|
|
Mar 31 02:28:58 PM PDT 24 |
Mar 31 02:37:25 PM PDT 24 |
1440519962 ps |
| T755 |
/workspace/coverage/default/28.sram_ctrl_lc_escalation.2511865691 |
|
|
Mar 31 02:33:16 PM PDT 24 |
Mar 31 02:33:22 PM PDT 24 |
761101221 ps |
| T756 |
/workspace/coverage/default/27.sram_ctrl_executable.165217303 |
|
|
Mar 31 02:33:14 PM PDT 24 |
Mar 31 02:47:15 PM PDT 24 |
33448199735 ps |
| T757 |
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.3167050102 |
|
|
Mar 31 02:31:29 PM PDT 24 |
Mar 31 02:36:42 PM PDT 24 |
14800343157 ps |
| T758 |
/workspace/coverage/default/37.sram_ctrl_regwen.2663442988 |
|
|
Mar 31 02:35:06 PM PDT 24 |
Mar 31 02:49:12 PM PDT 24 |
25008435153 ps |
| T759 |
/workspace/coverage/default/6.sram_ctrl_partial_access.3208073703 |
|
|
Mar 31 02:29:24 PM PDT 24 |
Mar 31 02:29:33 PM PDT 24 |
2382595449 ps |
| T760 |
/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.956382663 |
|
|
Mar 31 02:32:20 PM PDT 24 |
Mar 31 02:32:36 PM PDT 24 |
92208868 ps |
| T761 |
/workspace/coverage/default/33.sram_ctrl_mem_partial_access.748298364 |
|
|
Mar 31 02:34:04 PM PDT 24 |
Mar 31 02:34:10 PM PDT 24 |
364619907 ps |
| T762 |
/workspace/coverage/default/12.sram_ctrl_partial_access.1484385974 |
|
|
Mar 31 02:29:59 PM PDT 24 |
Mar 31 02:30:16 PM PDT 24 |
192951656 ps |
| T763 |
/workspace/coverage/default/37.sram_ctrl_bijection.1753105206 |
|
|
Mar 31 02:35:00 PM PDT 24 |
Mar 31 02:36:00 PM PDT 24 |
4014549533 ps |
| T764 |
/workspace/coverage/default/15.sram_ctrl_alert_test.1132434679 |
|
|
Mar 31 02:30:38 PM PDT 24 |
Mar 31 02:30:38 PM PDT 24 |
17809079 ps |
| T765 |
/workspace/coverage/default/31.sram_ctrl_alert_test.2335323807 |
|
|
Mar 31 02:33:44 PM PDT 24 |
Mar 31 02:33:45 PM PDT 24 |
12598036 ps |
| T766 |
/workspace/coverage/default/48.sram_ctrl_regwen.1799182562 |
|
|
Mar 31 02:37:21 PM PDT 24 |
Mar 31 02:53:14 PM PDT 24 |
15387535270 ps |
| T767 |
/workspace/coverage/default/4.sram_ctrl_alert_test.3434392500 |
|
|
Mar 31 02:29:19 PM PDT 24 |
Mar 31 02:29:19 PM PDT 24 |
20015630 ps |
| T768 |
/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.4237933430 |
|
|
Mar 31 02:35:53 PM PDT 24 |
Mar 31 02:40:22 PM PDT 24 |
2392654541 ps |
| T769 |
/workspace/coverage/default/32.sram_ctrl_lc_escalation.1946910763 |
|
|
Mar 31 02:33:56 PM PDT 24 |
Mar 31 02:33:58 PM PDT 24 |
368984565 ps |
| T770 |
/workspace/coverage/default/29.sram_ctrl_alert_test.1314087710 |
|
|
Mar 31 02:33:25 PM PDT 24 |
Mar 31 02:33:26 PM PDT 24 |
32163760 ps |
| T771 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.3710490333 |
|
|
Mar 31 02:33:31 PM PDT 24 |
Mar 31 02:33:44 PM PDT 24 |
681325867 ps |
| T772 |
/workspace/coverage/default/31.sram_ctrl_smoke.521660026 |
|
|
Mar 31 02:33:28 PM PDT 24 |
Mar 31 02:33:40 PM PDT 24 |
1046916844 ps |
| T773 |
/workspace/coverage/default/49.sram_ctrl_partial_access.2816487527 |
|
|
Mar 31 02:37:28 PM PDT 24 |
Mar 31 02:37:45 PM PDT 24 |
1979950060 ps |
| T774 |
/workspace/coverage/default/20.sram_ctrl_executable.1673551757 |
|
|
Mar 31 02:31:23 PM PDT 24 |
Mar 31 02:34:24 PM PDT 24 |
3117688491 ps |
| T775 |
/workspace/coverage/default/2.sram_ctrl_stress_all.2956387519 |
|
|
Mar 31 02:29:05 PM PDT 24 |
Mar 31 02:30:53 PM PDT 24 |
12567687352 ps |
| T776 |
/workspace/coverage/default/14.sram_ctrl_executable.3425560542 |
|
|
Mar 31 02:30:24 PM PDT 24 |
Mar 31 02:38:40 PM PDT 24 |
5241747550 ps |
| T777 |
/workspace/coverage/default/26.sram_ctrl_regwen.2280074629 |
|
|
Mar 31 02:32:37 PM PDT 24 |
Mar 31 02:45:20 PM PDT 24 |
6334620303 ps |
| T778 |
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.1614334885 |
|
|
Mar 31 02:36:09 PM PDT 24 |
Mar 31 02:40:08 PM PDT 24 |
2416380749 ps |
| T779 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.1825020561 |
|
|
Mar 31 02:29:59 PM PDT 24 |
Mar 31 02:30:01 PM PDT 24 |
86866400 ps |
| T780 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.2049851513 |
|
|
Mar 31 02:37:20 PM PDT 24 |
Mar 31 02:38:41 PM PDT 24 |
393280371 ps |
| T781 |
/workspace/coverage/default/3.sram_ctrl_executable.1959544968 |
|
|
Mar 31 02:29:05 PM PDT 24 |
Mar 31 02:51:15 PM PDT 24 |
44471291666 ps |
| T782 |
/workspace/coverage/default/33.sram_ctrl_smoke.1666531366 |
|
|
Mar 31 02:34:00 PM PDT 24 |
Mar 31 02:34:13 PM PDT 24 |
10522923945 ps |
| T783 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.2767803883 |
|
|
Mar 31 02:35:20 PM PDT 24 |
Mar 31 02:35:30 PM PDT 24 |
69039596 ps |
| T784 |
/workspace/coverage/default/36.sram_ctrl_mem_walk.1979736011 |
|
|
Mar 31 02:34:57 PM PDT 24 |
Mar 31 02:35:02 PM PDT 24 |
448862776 ps |
| T785 |
/workspace/coverage/default/39.sram_ctrl_lc_escalation.609887366 |
|
|
Mar 31 02:35:34 PM PDT 24 |
Mar 31 02:35:38 PM PDT 24 |
348013756 ps |
| T786 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.575446108 |
|
|
Mar 31 02:31:27 PM PDT 24 |
Mar 31 02:31:27 PM PDT 24 |
80596307 ps |
| T787 |
/workspace/coverage/default/26.sram_ctrl_access_during_key_req.343984142 |
|
|
Mar 31 02:32:31 PM PDT 24 |
Mar 31 02:47:49 PM PDT 24 |
3255303801 ps |
| T788 |
/workspace/coverage/default/20.sram_ctrl_partial_access.2381185544 |
|
|
Mar 31 02:31:17 PM PDT 24 |
Mar 31 02:31:18 PM PDT 24 |
33633152 ps |
| T789 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.800820657 |
|
|
Mar 31 02:29:29 PM PDT 24 |
Mar 31 02:31:41 PM PDT 24 |
6147134424 ps |
| T790 |
/workspace/coverage/default/21.sram_ctrl_ram_cfg.4029434630 |
|
|
Mar 31 02:31:34 PM PDT 24 |
Mar 31 02:31:35 PM PDT 24 |
152028781 ps |
| T791 |
/workspace/coverage/default/38.sram_ctrl_access_during_key_req.499018873 |
|
|
Mar 31 02:35:20 PM PDT 24 |
Mar 31 02:52:04 PM PDT 24 |
13433445209 ps |
| T792 |
/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.3606369872 |
|
|
Mar 31 02:33:16 PM PDT 24 |
Mar 31 02:40:39 PM PDT 24 |
68041326374 ps |