| T793 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.621613125 |
|
|
Mar 31 02:37:18 PM PDT 24 |
Mar 31 02:42:03 PM PDT 24 |
2919666992 ps |
| T794 |
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.3276244597 |
|
|
Mar 31 02:30:26 PM PDT 24 |
Mar 31 02:31:36 PM PDT 24 |
553605509 ps |
| T795 |
/workspace/coverage/default/44.sram_ctrl_max_throughput.1665345207 |
|
|
Mar 31 02:36:34 PM PDT 24 |
Mar 31 02:36:36 PM PDT 24 |
44880124 ps |
| T796 |
/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.1019437373 |
|
|
Mar 31 02:34:05 PM PDT 24 |
Mar 31 02:34:07 PM PDT 24 |
182741417 ps |
| T797 |
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.3606770949 |
|
|
Mar 31 02:31:36 PM PDT 24 |
Mar 31 02:35:10 PM PDT 24 |
9153982004 ps |
| T798 |
/workspace/coverage/default/44.sram_ctrl_alert_test.3073319979 |
|
|
Mar 31 02:36:41 PM PDT 24 |
Mar 31 02:36:42 PM PDT 24 |
13168015 ps |
| T799 |
/workspace/coverage/default/48.sram_ctrl_mem_walk.184788714 |
|
|
Mar 31 02:37:18 PM PDT 24 |
Mar 31 02:37:29 PM PDT 24 |
462671643 ps |
| T800 |
/workspace/coverage/default/36.sram_ctrl_smoke.1783051876 |
|
|
Mar 31 02:34:48 PM PDT 24 |
Mar 31 02:37:17 PM PDT 24 |
1174927161 ps |
| T801 |
/workspace/coverage/default/34.sram_ctrl_stress_all.21150245 |
|
|
Mar 31 02:34:30 PM PDT 24 |
Mar 31 02:59:50 PM PDT 24 |
115347391255 ps |
| T802 |
/workspace/coverage/default/9.sram_ctrl_mem_walk.4036488075 |
|
|
Mar 31 02:29:40 PM PDT 24 |
Mar 31 02:29:46 PM PDT 24 |
235069817 ps |
| T803 |
/workspace/coverage/default/0.sram_ctrl_bijection.4031911846 |
|
|
Mar 31 02:28:47 PM PDT 24 |
Mar 31 02:29:04 PM PDT 24 |
1064330801 ps |
| T804 |
/workspace/coverage/default/34.sram_ctrl_lc_escalation.2406602165 |
|
|
Mar 31 02:34:20 PM PDT 24 |
Mar 31 02:34:31 PM PDT 24 |
3841133329 ps |
| T805 |
/workspace/coverage/default/11.sram_ctrl_alert_test.3922578001 |
|
|
Mar 31 02:29:59 PM PDT 24 |
Mar 31 02:30:01 PM PDT 24 |
41805214 ps |
| T806 |
/workspace/coverage/default/40.sram_ctrl_regwen.2142135092 |
|
|
Mar 31 02:35:46 PM PDT 24 |
Mar 31 02:49:16 PM PDT 24 |
76048850684 ps |
| T807 |
/workspace/coverage/default/35.sram_ctrl_partial_access.898780655 |
|
|
Mar 31 02:34:36 PM PDT 24 |
Mar 31 02:35:46 PM PDT 24 |
1842092678 ps |
| T808 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.3066054510 |
|
|
Mar 31 02:37:31 PM PDT 24 |
Mar 31 02:39:28 PM PDT 24 |
124094500 ps |
| T809 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.1542088109 |
|
|
Mar 31 02:37:21 PM PDT 24 |
Mar 31 02:37:23 PM PDT 24 |
349266005 ps |
| T810 |
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.1118908844 |
|
|
Mar 31 02:32:04 PM PDT 24 |
Mar 31 02:32:23 PM PDT 24 |
77844520 ps |
| T811 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.3143822932 |
|
|
Mar 31 02:29:59 PM PDT 24 |
Mar 31 02:30:02 PM PDT 24 |
196138109 ps |
| T812 |
/workspace/coverage/default/9.sram_ctrl_executable.2544509433 |
|
|
Mar 31 02:29:35 PM PDT 24 |
Mar 31 02:38:45 PM PDT 24 |
1650864508 ps |
| T813 |
/workspace/coverage/default/36.sram_ctrl_stress_all.1541560539 |
|
|
Mar 31 02:34:54 PM PDT 24 |
Mar 31 03:30:17 PM PDT 24 |
18097693552 ps |
| T814 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.822070338 |
|
|
Mar 31 02:30:11 PM PDT 24 |
Mar 31 02:33:01 PM PDT 24 |
1400262308 ps |
| T815 |
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.2761967065 |
|
|
Mar 31 02:37:23 PM PDT 24 |
Mar 31 02:41:48 PM PDT 24 |
35929287833 ps |
| T816 |
/workspace/coverage/default/45.sram_ctrl_alert_test.2629536009 |
|
|
Mar 31 02:36:52 PM PDT 24 |
Mar 31 02:36:53 PM PDT 24 |
30845495 ps |
| T817 |
/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.3076786993 |
|
|
Mar 31 02:35:07 PM PDT 24 |
Mar 31 02:36:05 PM PDT 24 |
4308537579 ps |
| T818 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.2968882078 |
|
|
Mar 31 02:31:18 PM PDT 24 |
Mar 31 02:39:29 PM PDT 24 |
7902909719 ps |
| T819 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3916692999 |
|
|
Mar 31 02:37:21 PM PDT 24 |
Mar 31 02:40:58 PM PDT 24 |
46139163856 ps |
| T820 |
/workspace/coverage/default/2.sram_ctrl_access_during_key_req.633640247 |
|
|
Mar 31 02:29:00 PM PDT 24 |
Mar 31 02:36:05 PM PDT 24 |
3478470608 ps |
| T821 |
/workspace/coverage/default/46.sram_ctrl_lc_escalation.1276944853 |
|
|
Mar 31 02:36:57 PM PDT 24 |
Mar 31 02:37:07 PM PDT 24 |
2617978158 ps |
| T822 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.3526742131 |
|
|
Mar 31 02:28:53 PM PDT 24 |
Mar 31 02:34:54 PM PDT 24 |
9308773988 ps |
| T823 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.1575652522 |
|
|
Mar 31 02:31:55 PM PDT 24 |
Mar 31 02:32:00 PM PDT 24 |
2892450548 ps |
| T824 |
/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.363069628 |
|
|
Mar 31 02:32:38 PM PDT 24 |
Mar 31 02:41:52 PM PDT 24 |
265642262852 ps |
| T825 |
/workspace/coverage/default/14.sram_ctrl_regwen.947317718 |
|
|
Mar 31 02:30:25 PM PDT 24 |
Mar 31 02:53:44 PM PDT 24 |
1724649867 ps |
| T826 |
/workspace/coverage/default/34.sram_ctrl_partial_access.981987002 |
|
|
Mar 31 02:34:13 PM PDT 24 |
Mar 31 02:34:20 PM PDT 24 |
416195713 ps |
| T827 |
/workspace/coverage/default/0.sram_ctrl_executable.3639831731 |
|
|
Mar 31 02:28:52 PM PDT 24 |
Mar 31 02:32:25 PM PDT 24 |
2266358021 ps |
| T828 |
/workspace/coverage/default/8.sram_ctrl_regwen.1983296720 |
|
|
Mar 31 02:29:37 PM PDT 24 |
Mar 31 02:39:14 PM PDT 24 |
3573036226 ps |
| T829 |
/workspace/coverage/default/2.sram_ctrl_ram_cfg.3465779819 |
|
|
Mar 31 02:29:04 PM PDT 24 |
Mar 31 02:29:05 PM PDT 24 |
123164141 ps |
| T830 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.1903857828 |
|
|
Mar 31 02:36:34 PM PDT 24 |
Mar 31 02:40:33 PM PDT 24 |
9624355842 ps |
| T831 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.4004686938 |
|
|
Mar 31 02:36:24 PM PDT 24 |
Mar 31 02:36:30 PM PDT 24 |
463243716 ps |
| T832 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.692513539 |
|
|
Mar 31 02:29:53 PM PDT 24 |
Mar 31 02:30:34 PM PDT 24 |
748715110 ps |
| T833 |
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1054194893 |
|
|
Mar 31 02:37:36 PM PDT 24 |
Mar 31 02:37:59 PM PDT 24 |
3155025758 ps |
| T834 |
/workspace/coverage/default/6.sram_ctrl_max_throughput.2048959816 |
|
|
Mar 31 02:29:22 PM PDT 24 |
Mar 31 02:29:46 PM PDT 24 |
145001220 ps |
| T36 |
/workspace/coverage/default/1.sram_ctrl_sec_cm.652485178 |
|
|
Mar 31 02:29:00 PM PDT 24 |
Mar 31 02:29:04 PM PDT 24 |
1681827475 ps |
| T835 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.2035230667 |
|
|
Mar 31 02:30:24 PM PDT 24 |
Mar 31 02:36:33 PM PDT 24 |
4583664466 ps |
| T836 |
/workspace/coverage/default/23.sram_ctrl_partial_access.4128633693 |
|
|
Mar 31 02:31:59 PM PDT 24 |
Mar 31 02:33:51 PM PDT 24 |
2740546726 ps |
| T837 |
/workspace/coverage/default/34.sram_ctrl_smoke.676450341 |
|
|
Mar 31 02:34:12 PM PDT 24 |
Mar 31 02:34:14 PM PDT 24 |
181249185 ps |
| T838 |
/workspace/coverage/default/31.sram_ctrl_ram_cfg.3412877851 |
|
|
Mar 31 02:33:40 PM PDT 24 |
Mar 31 02:33:41 PM PDT 24 |
52592655 ps |
| T839 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.4161321557 |
|
|
Mar 31 02:34:07 PM PDT 24 |
Mar 31 02:34:16 PM PDT 24 |
1612504495 ps |
| T840 |
/workspace/coverage/default/16.sram_ctrl_executable.1911998317 |
|
|
Mar 31 02:30:46 PM PDT 24 |
Mar 31 02:36:42 PM PDT 24 |
27796143650 ps |
| T841 |
/workspace/coverage/default/32.sram_ctrl_regwen.1593898970 |
|
|
Mar 31 02:33:57 PM PDT 24 |
Mar 31 02:52:11 PM PDT 24 |
3413407514 ps |
| T842 |
/workspace/coverage/default/12.sram_ctrl_smoke.2681682583 |
|
|
Mar 31 02:30:03 PM PDT 24 |
Mar 31 02:30:16 PM PDT 24 |
420678829 ps |
| T843 |
/workspace/coverage/default/34.sram_ctrl_bijection.1842953881 |
|
|
Mar 31 02:34:13 PM PDT 24 |
Mar 31 02:34:31 PM PDT 24 |
961012385 ps |
| T844 |
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.4122412145 |
|
|
Mar 31 02:33:41 PM PDT 24 |
Mar 31 02:53:01 PM PDT 24 |
3638280802 ps |
| T845 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.2174348129 |
|
|
Mar 31 02:29:30 PM PDT 24 |
Mar 31 02:29:35 PM PDT 24 |
872854737 ps |
| T846 |
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.36251019 |
|
|
Mar 31 02:36:40 PM PDT 24 |
Mar 31 02:36:43 PM PDT 24 |
98010085 ps |
| T847 |
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.3862838489 |
|
|
Mar 31 02:30:10 PM PDT 24 |
Mar 31 02:34:11 PM PDT 24 |
14902159822 ps |
| T848 |
/workspace/coverage/default/28.sram_ctrl_bijection.2428878772 |
|
|
Mar 31 02:33:18 PM PDT 24 |
Mar 31 02:34:21 PM PDT 24 |
3879248362 ps |
| T849 |
/workspace/coverage/default/12.sram_ctrl_stress_all.1568392142 |
|
|
Mar 31 02:30:03 PM PDT 24 |
Mar 31 03:33:21 PM PDT 24 |
92113758300 ps |
| T850 |
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.664201127 |
|
|
Mar 31 02:33:30 PM PDT 24 |
Mar 31 02:37:09 PM PDT 24 |
14733940077 ps |
| T851 |
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.2594124951 |
|
|
Mar 31 02:36:16 PM PDT 24 |
Mar 31 02:36:19 PM PDT 24 |
380139703 ps |
| T852 |
/workspace/coverage/default/45.sram_ctrl_executable.3408018142 |
|
|
Mar 31 02:36:52 PM PDT 24 |
Mar 31 02:51:33 PM PDT 24 |
11752108315 ps |
| T853 |
/workspace/coverage/default/13.sram_ctrl_partial_access.2348452709 |
|
|
Mar 31 02:30:11 PM PDT 24 |
Mar 31 02:30:22 PM PDT 24 |
3342760227 ps |
| T854 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.3124944277 |
|
|
Mar 31 02:37:12 PM PDT 24 |
Mar 31 02:37:18 PM PDT 24 |
605895212 ps |
| T855 |
/workspace/coverage/default/39.sram_ctrl_partial_access.2532860016 |
|
|
Mar 31 02:35:26 PM PDT 24 |
Mar 31 02:35:57 PM PDT 24 |
1333190827 ps |
| T856 |
/workspace/coverage/default/19.sram_ctrl_bijection.592994070 |
|
|
Mar 31 02:31:05 PM PDT 24 |
Mar 31 02:31:48 PM PDT 24 |
1780815608 ps |
| T857 |
/workspace/coverage/default/19.sram_ctrl_mem_partial_access.998745083 |
|
|
Mar 31 02:31:19 PM PDT 24 |
Mar 31 02:31:22 PM PDT 24 |
89172467 ps |
| T858 |
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.1765190724 |
|
|
Mar 31 02:30:19 PM PDT 24 |
Mar 31 02:36:12 PM PDT 24 |
107332581593 ps |
| T859 |
/workspace/coverage/default/40.sram_ctrl_multiple_keys.1471680044 |
|
|
Mar 31 02:35:40 PM PDT 24 |
Mar 31 02:39:52 PM PDT 24 |
1617635072 ps |
| T860 |
/workspace/coverage/default/24.sram_ctrl_mem_walk.565625295 |
|
|
Mar 31 02:32:10 PM PDT 24 |
Mar 31 02:32:16 PM PDT 24 |
937864070 ps |
| T861 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.3556779685 |
|
|
Mar 31 02:36:34 PM PDT 24 |
Mar 31 02:51:37 PM PDT 24 |
141827942156 ps |
| T862 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.3296721793 |
|
|
Mar 31 02:31:22 PM PDT 24 |
Mar 31 02:32:31 PM PDT 24 |
120054257 ps |
| T863 |
/workspace/coverage/default/4.sram_ctrl_stress_pipeline.3844418149 |
|
|
Mar 31 02:29:10 PM PDT 24 |
Mar 31 02:33:46 PM PDT 24 |
5983024178 ps |
| T864 |
/workspace/coverage/default/32.sram_ctrl_alert_test.4103968369 |
|
|
Mar 31 02:33:57 PM PDT 24 |
Mar 31 02:33:58 PM PDT 24 |
150579747 ps |
| T865 |
/workspace/coverage/default/28.sram_ctrl_partial_access.3898662610 |
|
|
Mar 31 02:33:17 PM PDT 24 |
Mar 31 02:33:44 PM PDT 24 |
152111636 ps |
| T866 |
/workspace/coverage/default/30.sram_ctrl_stress_pipeline.1040547894 |
|
|
Mar 31 02:33:28 PM PDT 24 |
Mar 31 02:35:20 PM PDT 24 |
2372308847 ps |
| T867 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.558769715 |
|
|
Mar 31 02:35:20 PM PDT 24 |
Mar 31 02:35:23 PM PDT 24 |
47166594 ps |
| T868 |
/workspace/coverage/default/22.sram_ctrl_mem_partial_access.726391600 |
|
|
Mar 31 02:31:48 PM PDT 24 |
Mar 31 02:31:53 PM PDT 24 |
289876585 ps |
| T869 |
/workspace/coverage/default/27.sram_ctrl_mem_partial_access.3335367156 |
|
|
Mar 31 02:33:14 PM PDT 24 |
Mar 31 02:33:17 PM PDT 24 |
44577283 ps |
| T870 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.792355991 |
|
|
Mar 31 02:29:05 PM PDT 24 |
Mar 31 02:29:10 PM PDT 24 |
1021639666 ps |
| T871 |
/workspace/coverage/default/1.sram_ctrl_max_throughput.3083287145 |
|
|
Mar 31 02:29:00 PM PDT 24 |
Mar 31 02:29:24 PM PDT 24 |
1178805282 ps |
| T872 |
/workspace/coverage/default/22.sram_ctrl_access_during_key_req.869717602 |
|
|
Mar 31 02:31:48 PM PDT 24 |
Mar 31 02:45:32 PM PDT 24 |
10541721780 ps |
| T873 |
/workspace/coverage/default/18.sram_ctrl_alert_test.419143897 |
|
|
Mar 31 02:31:05 PM PDT 24 |
Mar 31 02:31:06 PM PDT 24 |
22477601 ps |
| T874 |
/workspace/coverage/default/38.sram_ctrl_max_throughput.3282382934 |
|
|
Mar 31 02:35:21 PM PDT 24 |
Mar 31 02:35:23 PM PDT 24 |
148280372 ps |
| T875 |
/workspace/coverage/default/33.sram_ctrl_ram_cfg.3848953228 |
|
|
Mar 31 02:34:06 PM PDT 24 |
Mar 31 02:34:07 PM PDT 24 |
28142949 ps |
| T876 |
/workspace/coverage/default/39.sram_ctrl_alert_test.1001984551 |
|
|
Mar 31 02:35:42 PM PDT 24 |
Mar 31 02:35:43 PM PDT 24 |
31139849 ps |
| T877 |
/workspace/coverage/default/26.sram_ctrl_bijection.691691078 |
|
|
Mar 31 02:32:37 PM PDT 24 |
Mar 31 02:33:08 PM PDT 24 |
4063197970 ps |
| T878 |
/workspace/coverage/default/11.sram_ctrl_lc_escalation.2395738981 |
|
|
Mar 31 02:29:52 PM PDT 24 |
Mar 31 02:29:56 PM PDT 24 |
660873503 ps |
| T879 |
/workspace/coverage/default/48.sram_ctrl_smoke.408845866 |
|
|
Mar 31 02:37:12 PM PDT 24 |
Mar 31 02:37:57 PM PDT 24 |
328649900 ps |
| T880 |
/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.1673131347 |
|
|
Mar 31 02:31:56 PM PDT 24 |
Mar 31 02:53:28 PM PDT 24 |
2634865387 ps |
| T881 |
/workspace/coverage/default/22.sram_ctrl_ram_cfg.3431579814 |
|
|
Mar 31 02:31:50 PM PDT 24 |
Mar 31 02:31:50 PM PDT 24 |
44291207 ps |
| T882 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.2603582434 |
|
|
Mar 31 02:31:36 PM PDT 24 |
Mar 31 02:31:42 PM PDT 24 |
167277432 ps |
| T883 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.2456944846 |
|
|
Mar 31 02:33:18 PM PDT 24 |
Mar 31 02:33:21 PM PDT 24 |
252092297 ps |
| T884 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.1456051083 |
|
|
Mar 31 02:35:34 PM PDT 24 |
Mar 31 02:35:35 PM PDT 24 |
43056919 ps |
| T885 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.4111168186 |
|
|
Mar 31 02:29:35 PM PDT 24 |
Mar 31 02:29:38 PM PDT 24 |
83605353 ps |
| T886 |
/workspace/coverage/default/30.sram_ctrl_lc_escalation.3593316458 |
|
|
Mar 31 02:33:25 PM PDT 24 |
Mar 31 02:33:31 PM PDT 24 |
455996677 ps |
| T887 |
/workspace/coverage/default/49.sram_ctrl_stress_all.3117488950 |
|
|
Mar 31 02:37:38 PM PDT 24 |
Mar 31 03:36:17 PM PDT 24 |
54882382972 ps |
| T888 |
/workspace/coverage/default/10.sram_ctrl_ram_cfg.2257661732 |
|
|
Mar 31 02:29:47 PM PDT 24 |
Mar 31 02:29:49 PM PDT 24 |
82127316 ps |
| T889 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1936306362 |
|
|
Mar 31 02:29:37 PM PDT 24 |
Mar 31 02:31:00 PM PDT 24 |
1025326745 ps |
| T890 |
/workspace/coverage/default/18.sram_ctrl_smoke.1543098557 |
|
|
Mar 31 02:31:00 PM PDT 24 |
Mar 31 02:31:04 PM PDT 24 |
306426159 ps |
| T891 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.1744439679 |
|
|
Mar 31 02:36:40 PM PDT 24 |
Mar 31 02:36:45 PM PDT 24 |
2315033891 ps |
| T892 |
/workspace/coverage/default/7.sram_ctrl_stress_all.4206702817 |
|
|
Mar 31 02:29:28 PM PDT 24 |
Mar 31 02:50:22 PM PDT 24 |
25231680761 ps |
| T893 |
/workspace/coverage/default/30.sram_ctrl_stress_all.3338156226 |
|
|
Mar 31 02:33:28 PM PDT 24 |
Mar 31 03:15:38 PM PDT 24 |
12418877334 ps |
| T894 |
/workspace/coverage/default/8.sram_ctrl_smoke.4263188411 |
|
|
Mar 31 02:29:30 PM PDT 24 |
Mar 31 02:30:31 PM PDT 24 |
376461715 ps |
| T895 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.3890296254 |
|
|
Mar 31 02:30:54 PM PDT 24 |
Mar 31 02:36:33 PM PDT 24 |
19024347714 ps |
| T896 |
/workspace/coverage/default/18.sram_ctrl_executable.3228916328 |
|
|
Mar 31 02:31:07 PM PDT 24 |
Mar 31 02:48:51 PM PDT 24 |
27209435334 ps |
| T897 |
/workspace/coverage/default/6.sram_ctrl_regwen.35858464 |
|
|
Mar 31 02:29:23 PM PDT 24 |
Mar 31 02:32:18 PM PDT 24 |
20265093517 ps |
| T898 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.1827981746 |
|
|
Mar 31 02:28:50 PM PDT 24 |
Mar 31 02:33:26 PM PDT 24 |
28340356709 ps |
| T899 |
/workspace/coverage/default/24.sram_ctrl_stress_pipeline.482698946 |
|
|
Mar 31 02:32:04 PM PDT 24 |
Mar 31 02:37:00 PM PDT 24 |
17912011023 ps |
| T900 |
/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.1856546882 |
|
|
Mar 31 02:34:36 PM PDT 24 |
Mar 31 02:36:27 PM PDT 24 |
1027157505 ps |
| T901 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.4109567850 |
|
|
Mar 31 02:31:03 PM PDT 24 |
Mar 31 02:31:08 PM PDT 24 |
187049917 ps |
| T902 |
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.3157782367 |
|
|
Mar 31 02:36:52 PM PDT 24 |
Mar 31 02:36:56 PM PDT 24 |
61621043 ps |
| T903 |
/workspace/coverage/default/6.sram_ctrl_multiple_keys.3372396734 |
|
|
Mar 31 02:29:23 PM PDT 24 |
Mar 31 02:42:36 PM PDT 24 |
3241146806 ps |
| T904 |
/workspace/coverage/default/25.sram_ctrl_smoke.3166094015 |
|
|
Mar 31 02:32:20 PM PDT 24 |
Mar 31 02:32:29 PM PDT 24 |
155326548 ps |
| T905 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.1779340843 |
|
|
Mar 31 02:30:45 PM PDT 24 |
Mar 31 02:49:07 PM PDT 24 |
36968115526 ps |
| T906 |
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.1460331469 |
|
|
Mar 31 02:36:18 PM PDT 24 |
Mar 31 02:36:37 PM PDT 24 |
2465796114 ps |
| T907 |
/workspace/coverage/default/6.sram_ctrl_executable.3920838959 |
|
|
Mar 31 02:29:24 PM PDT 24 |
Mar 31 02:48:57 PM PDT 24 |
26491003141 ps |
| T908 |
/workspace/coverage/default/25.sram_ctrl_alert_test.2144116800 |
|
|
Mar 31 02:32:26 PM PDT 24 |
Mar 31 02:32:26 PM PDT 24 |
21776789 ps |
| T909 |
/workspace/coverage/default/19.sram_ctrl_alert_test.4140797688 |
|
|
Mar 31 02:31:14 PM PDT 24 |
Mar 31 02:31:15 PM PDT 24 |
12016122 ps |
| T910 |
/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.2624203013 |
|
|
Mar 31 02:33:17 PM PDT 24 |
Mar 31 02:33:27 PM PDT 24 |
352285485 ps |
| T911 |
/workspace/coverage/default/27.sram_ctrl_alert_test.1503183104 |
|
|
Mar 31 02:33:15 PM PDT 24 |
Mar 31 02:33:16 PM PDT 24 |
18185319 ps |
| T912 |
/workspace/coverage/default/36.sram_ctrl_lc_escalation.2470296429 |
|
|
Mar 31 02:34:49 PM PDT 24 |
Mar 31 02:34:54 PM PDT 24 |
1688242527 ps |
| T913 |
/workspace/coverage/default/8.sram_ctrl_lc_escalation.1378509214 |
|
|
Mar 31 02:29:37 PM PDT 24 |
Mar 31 02:29:42 PM PDT 24 |
495297372 ps |
| T914 |
/workspace/coverage/default/22.sram_ctrl_partial_access.1813256298 |
|
|
Mar 31 02:31:42 PM PDT 24 |
Mar 31 02:32:00 PM PDT 24 |
3638736082 ps |
| T915 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.672894578 |
|
|
Mar 31 02:29:41 PM PDT 24 |
Mar 31 02:44:29 PM PDT 24 |
5666393781 ps |
| T916 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.2425810486 |
|
|
Mar 31 02:33:26 PM PDT 24 |
Mar 31 02:59:03 PM PDT 24 |
13331546453 ps |
| T917 |
/workspace/coverage/default/46.sram_ctrl_regwen.2041856135 |
|
|
Mar 31 02:36:58 PM PDT 24 |
Mar 31 03:03:04 PM PDT 24 |
17072841621 ps |
| T918 |
/workspace/coverage/default/4.sram_ctrl_smoke.843598212 |
|
|
Mar 31 02:29:12 PM PDT 24 |
Mar 31 02:29:21 PM PDT 24 |
114732882 ps |
| T919 |
/workspace/coverage/default/27.sram_ctrl_partial_access.792623755 |
|
|
Mar 31 02:32:38 PM PDT 24 |
Mar 31 02:32:45 PM PDT 24 |
1480361635 ps |
| T920 |
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.4239415077 |
|
|
Mar 31 02:29:58 PM PDT 24 |
Mar 31 02:30:00 PM PDT 24 |
150727074 ps |
| T921 |
/workspace/coverage/default/4.sram_ctrl_access_during_key_req.3865867966 |
|
|
Mar 31 02:29:12 PM PDT 24 |
Mar 31 02:40:50 PM PDT 24 |
3794625295 ps |
| T922 |
/workspace/coverage/default/41.sram_ctrl_smoke.3200012554 |
|
|
Mar 31 02:35:55 PM PDT 24 |
Mar 31 02:36:12 PM PDT 24 |
1128870338 ps |
| T923 |
/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.2633311159 |
|
|
Mar 31 02:29:00 PM PDT 24 |
Mar 31 02:29:17 PM PDT 24 |
167075045 ps |
| T924 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.3689752604 |
|
|
Mar 31 02:35:27 PM PDT 24 |
Mar 31 02:44:27 PM PDT 24 |
6741041468 ps |
| T925 |
/workspace/coverage/default/3.sram_ctrl_partial_access.2396164968 |
|
|
Mar 31 02:29:05 PM PDT 24 |
Mar 31 02:30:24 PM PDT 24 |
1944442606 ps |
| T926 |
/workspace/coverage/default/46.sram_ctrl_max_throughput.2293940157 |
|
|
Mar 31 02:36:59 PM PDT 24 |
Mar 31 02:38:55 PM PDT 24 |
241039916 ps |
| T927 |
/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.214908771 |
|
|
Mar 31 02:34:36 PM PDT 24 |
Mar 31 02:40:02 PM PDT 24 |
28396101497 ps |
| T928 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.1404636247 |
|
|
Mar 31 02:37:31 PM PDT 24 |
Mar 31 02:37:37 PM PDT 24 |
705425044 ps |
| T929 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.994351886 |
|
|
Mar 31 02:34:41 PM PDT 24 |
Mar 31 02:34:46 PM PDT 24 |
629705147 ps |
| T65 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3200004402 |
|
|
Mar 31 12:35:39 PM PDT 24 |
Mar 31 12:35:39 PM PDT 24 |
50308549 ps |
| T930 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1203252253 |
|
|
Mar 31 12:36:00 PM PDT 24 |
Mar 31 12:36:02 PM PDT 24 |
124200461 ps |
| T931 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.548558437 |
|
|
Mar 31 12:35:34 PM PDT 24 |
Mar 31 12:35:37 PM PDT 24 |
60293800 ps |
| T932 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3567323308 |
|
|
Mar 31 12:35:48 PM PDT 24 |
Mar 31 12:35:49 PM PDT 24 |
386152553 ps |
| T933 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1234546443 |
|
|
Mar 31 12:35:34 PM PDT 24 |
Mar 31 12:35:35 PM PDT 24 |
50119520 ps |
| T88 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3564957747 |
|
|
Mar 31 12:35:55 PM PDT 24 |
Mar 31 12:35:55 PM PDT 24 |
20249943 ps |
| T89 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3630230580 |
|
|
Mar 31 12:35:46 PM PDT 24 |
Mar 31 12:35:47 PM PDT 24 |
16394482 ps |
| T122 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.903883331 |
|
|
Mar 31 12:35:43 PM PDT 24 |
Mar 31 12:35:46 PM PDT 24 |
1624350689 ps |
| T934 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3903844791 |
|
|
Mar 31 12:35:42 PM PDT 24 |
Mar 31 12:35:46 PM PDT 24 |
357920388 ps |
| T66 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2492295288 |
|
|
Mar 31 12:35:46 PM PDT 24 |
Mar 31 12:35:48 PM PDT 24 |
256774746 ps |
| T67 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3090574296 |
|
|
Mar 31 12:35:46 PM PDT 24 |
Mar 31 12:35:49 PM PDT 24 |
1600652893 ps |
| T935 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3978345088 |
|
|
Mar 31 12:37:06 PM PDT 24 |
Mar 31 12:37:08 PM PDT 24 |
36851140 ps |
| T95 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1624683540 |
|
|
Mar 31 12:35:33 PM PDT 24 |
Mar 31 12:35:34 PM PDT 24 |
35471496 ps |
| T936 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.115756320 |
|
|
Mar 31 12:35:50 PM PDT 24 |
Mar 31 12:35:54 PM PDT 24 |
112253062 ps |
| T68 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2923477103 |
|
|
Mar 31 12:35:56 PM PDT 24 |
Mar 31 12:35:57 PM PDT 24 |
19224634 ps |
| T97 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.970725807 |
|
|
Mar 31 12:35:38 PM PDT 24 |
Mar 31 12:35:40 PM PDT 24 |
3237229083 ps |
| T937 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.558834812 |
|
|
Mar 31 12:35:42 PM PDT 24 |
Mar 31 12:35:44 PM PDT 24 |
51162800 ps |
| T90 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.309410751 |
|
|
Mar 31 12:36:48 PM PDT 24 |
Mar 31 12:36:49 PM PDT 24 |
35228525 ps |
| T69 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1211049897 |
|
|
Mar 31 12:35:33 PM PDT 24 |
Mar 31 12:35:35 PM PDT 24 |
223540202 ps |
| T70 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2518749460 |
|
|
Mar 31 12:36:16 PM PDT 24 |
Mar 31 12:36:18 PM PDT 24 |
823031459 ps |
| T938 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.348063177 |
|
|
Mar 31 12:36:00 PM PDT 24 |
Mar 31 12:36:02 PM PDT 24 |
60391807 ps |
| T939 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.644463474 |
|
|
Mar 31 12:35:43 PM PDT 24 |
Mar 31 12:35:46 PM PDT 24 |
109879330 ps |
| T71 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1110352674 |
|
|
Mar 31 12:35:45 PM PDT 24 |
Mar 31 12:35:46 PM PDT 24 |
59007310 ps |
| T940 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1774348878 |
|
|
Mar 31 12:35:52 PM PDT 24 |
Mar 31 12:35:53 PM PDT 24 |
54192220 ps |
| T941 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.4135558997 |
|
|
Mar 31 12:35:46 PM PDT 24 |
Mar 31 12:35:47 PM PDT 24 |
49200140 ps |
| T942 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2175619172 |
|
|
Mar 31 12:35:51 PM PDT 24 |
Mar 31 12:35:52 PM PDT 24 |
17559467 ps |
| T91 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.4108676780 |
|
|
Mar 31 12:36:00 PM PDT 24 |
Mar 31 12:36:01 PM PDT 24 |
50225413 ps |
| T72 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2343557466 |
|
|
Mar 31 12:36:08 PM PDT 24 |
Mar 31 12:36:09 PM PDT 24 |
13133108 ps |
| T943 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2388858987 |
|
|
Mar 31 12:36:01 PM PDT 24 |
Mar 31 12:36:07 PM PDT 24 |
65879358 ps |
| T73 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.4113074049 |
|
|
Mar 31 12:35:30 PM PDT 24 |
Mar 31 12:35:31 PM PDT 24 |
46466316 ps |
| T92 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1501856379 |
|
|
Mar 31 12:36:02 PM PDT 24 |
Mar 31 12:36:04 PM PDT 24 |
15321952 ps |
| T944 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2271758975 |
|
|
Mar 31 12:35:49 PM PDT 24 |
Mar 31 12:35:52 PM PDT 24 |
53591726 ps |
| T945 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1483460745 |
|
|
Mar 31 12:35:38 PM PDT 24 |
Mar 31 12:35:40 PM PDT 24 |
794703643 ps |
| T946 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2139304097 |
|
|
Mar 31 12:35:58 PM PDT 24 |
Mar 31 12:35:59 PM PDT 24 |
30897843 ps |
| T947 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2951372067 |
|
|
Mar 31 12:35:45 PM PDT 24 |
Mar 31 12:35:46 PM PDT 24 |
15367578 ps |
| T948 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.974903106 |
|
|
Mar 31 12:36:12 PM PDT 24 |
Mar 31 12:36:13 PM PDT 24 |
19674138 ps |
| T949 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1985264548 |
|
|
Mar 31 12:36:00 PM PDT 24 |
Mar 31 12:36:01 PM PDT 24 |
28281023 ps |
| T74 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3786796298 |
|
|
Mar 31 12:35:41 PM PDT 24 |
Mar 31 12:35:43 PM PDT 24 |
419714264 ps |
| T950 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2241480902 |
|
|
Mar 31 12:35:37 PM PDT 24 |
Mar 31 12:35:38 PM PDT 24 |
69170961 ps |
| T951 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3076603216 |
|
|
Mar 31 12:36:02 PM PDT 24 |
Mar 31 12:36:04 PM PDT 24 |
125192897 ps |
| T76 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.98527943 |
|
|
Mar 31 12:35:44 PM PDT 24 |
Mar 31 12:35:46 PM PDT 24 |
448405421 ps |
| T98 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1076369672 |
|
|
Mar 31 12:36:02 PM PDT 24 |
Mar 31 12:36:03 PM PDT 24 |
279026343 ps |
| T952 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3015010175 |
|
|
Mar 31 12:36:00 PM PDT 24 |
Mar 31 12:36:04 PM PDT 24 |
71278709 ps |
| T953 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.852943285 |
|
|
Mar 31 12:36:46 PM PDT 24 |
Mar 31 12:36:48 PM PDT 24 |
117264212 ps |
| T954 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3170340382 |
|
|
Mar 31 12:35:44 PM PDT 24 |
Mar 31 12:35:45 PM PDT 24 |
67570142 ps |
| T99 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1423438870 |
|
|
Mar 31 12:35:40 PM PDT 24 |
Mar 31 12:35:41 PM PDT 24 |
338533580 ps |
| T955 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.4228941760 |
|
|
Mar 31 12:35:45 PM PDT 24 |
Mar 31 12:35:46 PM PDT 24 |
132052769 ps |
| T956 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3596948064 |
|
|
Mar 31 12:35:46 PM PDT 24 |
Mar 31 12:35:51 PM PDT 24 |
607432880 ps |
| T113 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.4210753458 |
|
|
Mar 31 12:35:40 PM PDT 24 |
Mar 31 12:35:43 PM PDT 24 |
389291814 ps |
| T957 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3008314099 |
|
|
Mar 31 12:35:45 PM PDT 24 |
Mar 31 12:35:47 PM PDT 24 |
154402376 ps |
| T110 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2702233200 |
|
|
Mar 31 12:35:36 PM PDT 24 |
Mar 31 12:35:37 PM PDT 24 |
621680740 ps |
| T958 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.635720172 |
|
|
Mar 31 12:35:45 PM PDT 24 |
Mar 31 12:35:46 PM PDT 24 |
121474097 ps |
| T959 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.821170779 |
|
|
Mar 31 12:36:46 PM PDT 24 |
Mar 31 12:36:48 PM PDT 24 |
41670702 ps |
| T77 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2345790560 |
|
|
Mar 31 12:35:43 PM PDT 24 |
Mar 31 12:35:47 PM PDT 24 |
630179512 ps |
| T81 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3220887303 |
|
|
Mar 31 12:35:56 PM PDT 24 |
Mar 31 12:36:00 PM PDT 24 |
1210763578 ps |
| T960 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3571746731 |
|
|
Mar 31 12:35:46 PM PDT 24 |
Mar 31 12:35:47 PM PDT 24 |
25343828 ps |
| T961 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3847328164 |
|
|
Mar 31 12:35:48 PM PDT 24 |
Mar 31 12:35:49 PM PDT 24 |
49020060 ps |
| T962 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2197867560 |
|
|
Mar 31 12:35:45 PM PDT 24 |
Mar 31 12:35:46 PM PDT 24 |
33682438 ps |
| T85 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2538804477 |
|
|
Mar 31 12:35:54 PM PDT 24 |
Mar 31 12:35:56 PM PDT 24 |
907761333 ps |
| T963 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.138106853 |
|
|
Mar 31 12:36:02 PM PDT 24 |
Mar 31 12:36:06 PM PDT 24 |
132955507 ps |
| T82 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3903186662 |
|
|
Mar 31 12:35:42 PM PDT 24 |
Mar 31 12:35:46 PM PDT 24 |
183846625 ps |
| T964 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1710340223 |
|
|
Mar 31 12:36:03 PM PDT 24 |
Mar 31 12:36:07 PM PDT 24 |
338820326 ps |
| T965 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.4014225588 |
|
|
Mar 31 12:35:30 PM PDT 24 |
Mar 31 12:35:33 PM PDT 24 |
57679688 ps |
| T966 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1768924479 |
|
|
Mar 31 12:35:41 PM PDT 24 |
Mar 31 12:35:43 PM PDT 24 |
23694184 ps |
| T967 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1275761439 |
|
|
Mar 31 12:35:38 PM PDT 24 |
Mar 31 12:35:39 PM PDT 24 |
48458587 ps |
| T114 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.534941400 |
|
|
Mar 31 12:35:44 PM PDT 24 |
Mar 31 12:35:47 PM PDT 24 |
183133184 ps |
| T83 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2465249179 |
|
|
Mar 31 12:36:46 PM PDT 24 |
Mar 31 12:36:51 PM PDT 24 |
6368836662 ps |
| T84 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2577710799 |
|
|
Mar 31 12:36:21 PM PDT 24 |
Mar 31 12:36:22 PM PDT 24 |
134641350 ps |
| T115 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.287576515 |
|
|
Mar 31 12:35:41 PM PDT 24 |
Mar 31 12:35:44 PM PDT 24 |
468498503 ps |
| T968 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.109198092 |
|
|
Mar 31 12:35:47 PM PDT 24 |
Mar 31 12:35:48 PM PDT 24 |
39119752 ps |
| T969 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2136409033 |
|
|
Mar 31 12:36:06 PM PDT 24 |
Mar 31 12:36:07 PM PDT 24 |
29235105 ps |
| T970 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1298473068 |
|
|
Mar 31 12:35:44 PM PDT 24 |
Mar 31 12:35:45 PM PDT 24 |
18552233 ps |
| T86 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.336553790 |
|
|
Mar 31 12:36:48 PM PDT 24 |
Mar 31 12:36:51 PM PDT 24 |
453558428 ps |
| T971 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1025846051 |
|
|
Mar 31 12:35:40 PM PDT 24 |
Mar 31 12:35:42 PM PDT 24 |
71871820 ps |
| T972 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.833127207 |
|
|
Mar 31 12:35:40 PM PDT 24 |
Mar 31 12:35:41 PM PDT 24 |
55284166 ps |
| T117 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2831561569 |
|
|
Mar 31 12:35:46 PM PDT 24 |
Mar 31 12:35:48 PM PDT 24 |
108747499 ps |
| T973 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2701174855 |
|
|
Mar 31 12:35:43 PM PDT 24 |
Mar 31 12:35:44 PM PDT 24 |
40971403 ps |
| T974 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1601113999 |
|
|
Mar 31 12:35:35 PM PDT 24 |
Mar 31 12:35:36 PM PDT 24 |
12181293 ps |
| T975 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.973763578 |
|
|
Mar 31 12:35:39 PM PDT 24 |
Mar 31 12:35:39 PM PDT 24 |
40617208 ps |
| T976 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3804908908 |
|
|
Mar 31 12:35:39 PM PDT 24 |
Mar 31 12:35:39 PM PDT 24 |
17978237 ps |
| T977 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3834706656 |
|
|
Mar 31 12:35:42 PM PDT 24 |
Mar 31 12:35:43 PM PDT 24 |
14520949 ps |
| T978 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3031425526 |
|
|
Mar 31 12:36:47 PM PDT 24 |
Mar 31 12:36:50 PM PDT 24 |
911102959 ps |
| T87 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2720370273 |
|
|
Mar 31 12:36:06 PM PDT 24 |
Mar 31 12:36:09 PM PDT 24 |
1554774740 ps |
| T979 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3457003912 |
|
|
Mar 31 12:35:45 PM PDT 24 |
Mar 31 12:35:49 PM PDT 24 |
278870438 ps |
| T980 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1023120744 |
|
|
Mar 31 12:35:42 PM PDT 24 |
Mar 31 12:35:43 PM PDT 24 |
70438375 ps |
| T981 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.4254424504 |
|
|
Mar 31 12:35:42 PM PDT 24 |
Mar 31 12:35:44 PM PDT 24 |
179521025 ps |
| T111 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3804573548 |
|
|
Mar 31 12:35:57 PM PDT 24 |
Mar 31 12:36:00 PM PDT 24 |
396619637 ps |
| T982 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3208617350 |
|
|
Mar 31 12:36:15 PM PDT 24 |
Mar 31 12:36:16 PM PDT 24 |
24515619 ps |
| T119 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3714670395 |
|
|
Mar 31 12:35:51 PM PDT 24 |
Mar 31 12:35:53 PM PDT 24 |
193846706 ps |
| T983 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.873476401 |
|
|
Mar 31 12:35:46 PM PDT 24 |
Mar 31 12:35:49 PM PDT 24 |
3608340054 ps |
| T984 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2271478466 |
|
|
Mar 31 12:35:46 PM PDT 24 |
Mar 31 12:35:47 PM PDT 24 |
13392523 ps |
| T118 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3304724021 |
|
|
Mar 31 12:36:09 PM PDT 24 |
Mar 31 12:36:11 PM PDT 24 |
345479905 ps |
| T985 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1955265116 |
|
|
Mar 31 12:36:14 PM PDT 24 |
Mar 31 12:36:15 PM PDT 24 |
23929090 ps |
| T112 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3316114401 |
|
|
Mar 31 12:35:43 PM PDT 24 |
Mar 31 12:35:46 PM PDT 24 |
649704670 ps |
| T986 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2632156158 |
|
|
Mar 31 12:35:36 PM PDT 24 |
Mar 31 12:35:40 PM PDT 24 |
39016394 ps |
| T987 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2007796581 |
|
|
Mar 31 12:35:42 PM PDT 24 |
Mar 31 12:35:43 PM PDT 24 |
91554675 ps |
| T988 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.696485964 |
|
|
Mar 31 12:35:43 PM PDT 24 |
Mar 31 12:35:44 PM PDT 24 |
95502469 ps |
| T989 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2888415309 |
|
|
Mar 31 12:35:38 PM PDT 24 |
Mar 31 12:35:40 PM PDT 24 |
26635842 ps |
| T990 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2150438303 |
|
|
Mar 31 12:35:44 PM PDT 24 |
Mar 31 12:35:46 PM PDT 24 |
107009339 ps |
| T991 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.47108078 |
|
|
Mar 31 12:35:39 PM PDT 24 |
Mar 31 12:35:42 PM PDT 24 |
319674439 ps |
| T992 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1535920887 |
|
|
Mar 31 12:35:47 PM PDT 24 |
Mar 31 12:35:49 PM PDT 24 |
468773522 ps |
| T116 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.4215223226 |
|
|
Mar 31 12:36:04 PM PDT 24 |
Mar 31 12:36:08 PM PDT 24 |
1855976716 ps |
| T993 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3329942034 |
|
|
Mar 31 12:35:50 PM PDT 24 |
Mar 31 12:35:52 PM PDT 24 |
28871509 ps |
| T994 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1851123024 |
|
|
Mar 31 12:35:48 PM PDT 24 |
Mar 31 12:35:49 PM PDT 24 |
13340961 ps |
| T995 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3812451640 |
|
|
Mar 31 12:35:40 PM PDT 24 |
Mar 31 12:35:42 PM PDT 24 |
275016973 ps |
| T996 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.792697365 |
|
|
Mar 31 12:36:11 PM PDT 24 |
Mar 31 12:36:13 PM PDT 24 |
94355139 ps |
| T997 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.4191434597 |
|
|
Mar 31 12:35:46 PM PDT 24 |
Mar 31 12:35:47 PM PDT 24 |
15269075 ps |
| T998 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1897004451 |
|
|
Mar 31 12:35:34 PM PDT 24 |
Mar 31 12:35:36 PM PDT 24 |
732403717 ps |
| T999 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2984167111 |
|
|
Mar 31 12:35:45 PM PDT 24 |
Mar 31 12:35:48 PM PDT 24 |
67997136 ps |
| T1000 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2933988094 |
|
|
Mar 31 12:35:42 PM PDT 24 |
Mar 31 12:35:42 PM PDT 24 |
16017303 ps |
| T120 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1905210165 |
|
|
Mar 31 12:35:44 PM PDT 24 |
Mar 31 12:35:46 PM PDT 24 |
265501052 ps |
| T1001 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2803883941 |
|
|
Mar 31 12:35:46 PM PDT 24 |
Mar 31 12:35:47 PM PDT 24 |
36548589 ps |