Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.26	100.00	94.62	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	337137669	103869	0	0
ctrl_regwen_rd_A	337137669	4157	0	0
exec_rd_A	337137669	3606	0	0
exec_regwen_rd_A	337137669	4103	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337137669	103869	0	0
T5	391705	0	0	0
T6	653439	0	0	0
T12	37406	1185	0	0
T13	3941	0	0	0
T14	128735	3216	0	0
T16	1557	0	0	0
T23	8541	0	0	0
T24	0	1330	0	0
T34	0	669	0	0
T40	0	1416	0	0
T41	0	1440	0	0
T42	0	7471	0	0
T43	0	2373	0	0
T44	0	1199	0	0
T45	0	4366	0	0
T46	63488	0	0	0
T47	133529	0	0	0
T48	134007	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337137669	4157	0	0
T24	50534	302	0	0
T34	0	118	0	0
T43	0	275	0	0
T96	0	159	0	0
T97	0	334	0	0
T98	0	268	0	0
T99	0	286	0	0
T100	0	410	0	0
T101	0	143	0	0
T102	0	172	0	0
T103	55192	0	0	0
T104	96345	0	0	0
T105	205059	0	0	0
T106	54743	0	0	0
T107	128841	0	0	0
T108	417576	0	0	0
T109	2147	0	0	0
T110	6127	0	0	0
T111	14741	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337137669	3606	0	0
T24	50534	238	0	0
T34	0	98	0	0
T43	0	283	0	0
T96	0	108	0	0
T97	0	283	0	0
T98	0	279	0	0
T99	0	233	0	0
T100	0	342	0	0
T101	0	108	0	0
T102	0	229	0	0
T103	55192	0	0	0
T104	96345	0	0	0
T105	205059	0	0	0
T106	54743	0	0	0
T107	128841	0	0	0
T108	417576	0	0	0
T109	2147	0	0	0
T110	6127	0	0	0
T111	14741	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337137669	4103	0	0
T24	50534	306	0	0
T34	0	117	0	0
T43	0	306	0	0
T96	0	127	0	0
T97	0	308	0	0
T98	0	208	0	0
T99	0	392	0	0
T100	0	331	0	0
T101	0	193	0	0
T102	0	231	0	0
T103	55192	0	0	0
T104	96345	0	0	0
T105	205059	0	0	0
T106	54743	0	0	0
T107	128841	0	0	0
T108	417576	0	0	0
T109	2147	0	0	0
T110	6127	0	0	0
T111	14741	0	0	0