| T795 |
/workspace/coverage/default/1.sram_ctrl_executable.2660258991 |
|
|
Apr 04 12:35:48 PM PDT 24 |
Apr 04 12:55:43 PM PDT 24 |
115666253686 ps |
| T796 |
/workspace/coverage/default/24.sram_ctrl_alert_test.3739263972 |
|
|
Apr 04 12:37:08 PM PDT 24 |
Apr 04 12:37:09 PM PDT 24 |
31160269 ps |
| T797 |
/workspace/coverage/default/21.sram_ctrl_regwen.1965683721 |
|
|
Apr 04 12:36:54 PM PDT 24 |
Apr 04 12:55:03 PM PDT 24 |
23914919905 ps |
| T798 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.907039369 |
|
|
Apr 04 12:39:03 PM PDT 24 |
Apr 04 12:39:06 PM PDT 24 |
826577602 ps |
| T799 |
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.749817748 |
|
|
Apr 04 12:39:02 PM PDT 24 |
Apr 04 12:41:04 PM PDT 24 |
144309863 ps |
| T800 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.3216785903 |
|
|
Apr 04 12:38:53 PM PDT 24 |
Apr 04 12:38:56 PM PDT 24 |
48632982 ps |
| T801 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.150370138 |
|
|
Apr 04 12:39:29 PM PDT 24 |
Apr 04 01:05:08 PM PDT 24 |
5312299182 ps |
| T802 |
/workspace/coverage/default/7.sram_ctrl_bijection.1344561538 |
|
|
Apr 04 12:36:10 PM PDT 24 |
Apr 04 12:37:18 PM PDT 24 |
8737170757 ps |
| T803 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.2241894477 |
|
|
Apr 04 12:39:22 PM PDT 24 |
Apr 04 01:01:43 PM PDT 24 |
12706535744 ps |
| T804 |
/workspace/coverage/default/3.sram_ctrl_stress_pipeline.430015887 |
|
|
Apr 04 12:35:59 PM PDT 24 |
Apr 04 12:39:18 PM PDT 24 |
2294965052 ps |
| T805 |
/workspace/coverage/default/18.sram_ctrl_partial_access.3927650329 |
|
|
Apr 04 12:36:42 PM PDT 24 |
Apr 04 12:37:13 PM PDT 24 |
132049921 ps |
| T806 |
/workspace/coverage/default/2.sram_ctrl_ram_cfg.3529955381 |
|
|
Apr 04 12:35:51 PM PDT 24 |
Apr 04 12:35:52 PM PDT 24 |
80721304 ps |
| T807 |
/workspace/coverage/default/41.sram_ctrl_bijection.2202601633 |
|
|
Apr 04 12:38:45 PM PDT 24 |
Apr 04 12:39:03 PM PDT 24 |
1328241801 ps |
| T808 |
/workspace/coverage/default/17.sram_ctrl_mem_partial_access.2186967407 |
|
|
Apr 04 12:36:41 PM PDT 24 |
Apr 04 12:36:44 PM PDT 24 |
193020491 ps |
| T809 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.2134387361 |
|
|
Apr 04 12:36:51 PM PDT 24 |
Apr 04 12:38:06 PM PDT 24 |
230447213 ps |
| T810 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.491339824 |
|
|
Apr 04 12:39:14 PM PDT 24 |
Apr 04 12:47:41 PM PDT 24 |
9787351090 ps |
| T811 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.3440695634 |
|
|
Apr 04 12:36:32 PM PDT 24 |
Apr 04 12:43:02 PM PDT 24 |
1463119227 ps |
| T812 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.307745816 |
|
|
Apr 04 12:35:51 PM PDT 24 |
Apr 04 12:43:13 PM PDT 24 |
100075431405 ps |
| T813 |
/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.1565890661 |
|
|
Apr 04 12:36:58 PM PDT 24 |
Apr 04 12:37:36 PM PDT 24 |
984860808 ps |
| T814 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.2583972999 |
|
|
Apr 04 12:36:56 PM PDT 24 |
Apr 04 12:44:12 PM PDT 24 |
86444160733 ps |
| T815 |
/workspace/coverage/default/21.sram_ctrl_partial_access.3446362621 |
|
|
Apr 04 12:36:58 PM PDT 24 |
Apr 04 12:37:06 PM PDT 24 |
179635928 ps |
| T816 |
/workspace/coverage/default/2.sram_ctrl_smoke.30755552 |
|
|
Apr 04 12:35:50 PM PDT 24 |
Apr 04 12:36:41 PM PDT 24 |
391403013 ps |
| T817 |
/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.144801337 |
|
|
Apr 04 12:35:59 PM PDT 24 |
Apr 04 12:38:56 PM PDT 24 |
1846089371 ps |
| T818 |
/workspace/coverage/default/29.sram_ctrl_alert_test.3870856927 |
|
|
Apr 04 12:37:34 PM PDT 24 |
Apr 04 12:37:34 PM PDT 24 |
17692144 ps |
| T819 |
/workspace/coverage/default/34.sram_ctrl_smoke.173985710 |
|
|
Apr 04 12:38:02 PM PDT 24 |
Apr 04 12:39:20 PM PDT 24 |
229290480 ps |
| T820 |
/workspace/coverage/default/19.sram_ctrl_executable.2666600816 |
|
|
Apr 04 12:36:45 PM PDT 24 |
Apr 04 12:44:23 PM PDT 24 |
23040829749 ps |
| T821 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.423036535 |
|
|
Apr 04 12:37:26 PM PDT 24 |
Apr 04 12:37:26 PM PDT 24 |
51819963 ps |
| T822 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.2883405750 |
|
|
Apr 04 12:38:45 PM PDT 24 |
Apr 04 12:38:46 PM PDT 24 |
31175730 ps |
| T823 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.3634065405 |
|
|
Apr 04 12:38:20 PM PDT 24 |
Apr 04 12:40:11 PM PDT 24 |
325172200 ps |
| T824 |
/workspace/coverage/default/8.sram_ctrl_smoke.2286107671 |
|
|
Apr 04 12:36:13 PM PDT 24 |
Apr 04 12:36:56 PM PDT 24 |
408185183 ps |
| T825 |
/workspace/coverage/default/0.sram_ctrl_mem_walk.2068660776 |
|
|
Apr 04 12:35:51 PM PDT 24 |
Apr 04 12:35:59 PM PDT 24 |
268178195 ps |
| T826 |
/workspace/coverage/default/39.sram_ctrl_regwen.497511173 |
|
|
Apr 04 12:38:38 PM PDT 24 |
Apr 04 12:41:27 PM PDT 24 |
2828612007 ps |
| T827 |
/workspace/coverage/default/24.sram_ctrl_partial_access.3479266645 |
|
|
Apr 04 12:37:05 PM PDT 24 |
Apr 04 12:37:10 PM PDT 24 |
252093563 ps |
| T828 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.3862809833 |
|
|
Apr 04 12:38:05 PM PDT 24 |
Apr 04 12:38:15 PM PDT 24 |
1555069435 ps |
| T829 |
/workspace/coverage/default/3.sram_ctrl_stress_all.314693628 |
|
|
Apr 04 12:36:04 PM PDT 24 |
Apr 04 12:42:16 PM PDT 24 |
34238897275 ps |
| T830 |
/workspace/coverage/default/34.sram_ctrl_stress_all.2850032157 |
|
|
Apr 04 12:38:00 PM PDT 24 |
Apr 04 01:43:43 PM PDT 24 |
11883827127 ps |
| T831 |
/workspace/coverage/default/7.sram_ctrl_smoke.1361383882 |
|
|
Apr 04 12:36:13 PM PDT 24 |
Apr 04 12:36:19 PM PDT 24 |
331586484 ps |
| T832 |
/workspace/coverage/default/33.sram_ctrl_multiple_keys.1117180833 |
|
|
Apr 04 12:37:55 PM PDT 24 |
Apr 04 12:42:33 PM PDT 24 |
2790897135 ps |
| T833 |
/workspace/coverage/default/18.sram_ctrl_smoke.3498873134 |
|
|
Apr 04 12:36:42 PM PDT 24 |
Apr 04 12:37:00 PM PDT 24 |
1125203303 ps |
| T834 |
/workspace/coverage/default/18.sram_ctrl_multiple_keys.42146054 |
|
|
Apr 04 12:36:41 PM PDT 24 |
Apr 04 12:50:08 PM PDT 24 |
11566185917 ps |
| T835 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.2695727012 |
|
|
Apr 04 12:36:55 PM PDT 24 |
Apr 04 12:37:01 PM PDT 24 |
142839391 ps |
| T836 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.654149093 |
|
|
Apr 04 12:36:35 PM PDT 24 |
Apr 04 12:36:41 PM PDT 24 |
1829515073 ps |
| T837 |
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2972534779 |
|
|
Apr 04 12:39:12 PM PDT 24 |
Apr 04 12:39:59 PM PDT 24 |
1584751674 ps |
| T838 |
/workspace/coverage/default/41.sram_ctrl_stress_pipeline.1070906467 |
|
|
Apr 04 12:38:47 PM PDT 24 |
Apr 04 12:44:39 PM PDT 24 |
40831441265 ps |
| T839 |
/workspace/coverage/default/35.sram_ctrl_executable.1926345854 |
|
|
Apr 04 12:38:07 PM PDT 24 |
Apr 04 01:01:57 PM PDT 24 |
14767478773 ps |
| T840 |
/workspace/coverage/default/9.sram_ctrl_stress_all.3656704951 |
|
|
Apr 04 12:36:27 PM PDT 24 |
Apr 04 01:36:30 PM PDT 24 |
24011587464 ps |
| T841 |
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.3900033207 |
|
|
Apr 04 12:35:57 PM PDT 24 |
Apr 04 12:59:05 PM PDT 24 |
7829839312 ps |
| T842 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.412116129 |
|
|
Apr 04 12:36:53 PM PDT 24 |
Apr 04 12:47:40 PM PDT 24 |
6365499138 ps |
| T843 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.4257090807 |
|
|
Apr 04 12:37:05 PM PDT 24 |
Apr 04 12:37:15 PM PDT 24 |
2004184566 ps |
| T844 |
/workspace/coverage/default/1.sram_ctrl_mem_walk.485967147 |
|
|
Apr 04 12:35:54 PM PDT 24 |
Apr 04 12:36:02 PM PDT 24 |
462239888 ps |
| T845 |
/workspace/coverage/default/34.sram_ctrl_ram_cfg.2952747237 |
|
|
Apr 04 12:38:17 PM PDT 24 |
Apr 04 12:38:18 PM PDT 24 |
88028807 ps |
| T846 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.3345362982 |
|
|
Apr 04 12:36:01 PM PDT 24 |
Apr 04 12:40:34 PM PDT 24 |
23657157473 ps |
| T847 |
/workspace/coverage/default/0.sram_ctrl_stress_all.3523723403 |
|
|
Apr 04 12:35:52 PM PDT 24 |
Apr 04 01:19:59 PM PDT 24 |
13530237324 ps |
| T848 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.299669668 |
|
|
Apr 04 12:39:28 PM PDT 24 |
Apr 04 12:52:08 PM PDT 24 |
13941463157 ps |
| T849 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.2525841207 |
|
|
Apr 04 12:36:00 PM PDT 24 |
Apr 04 12:36:02 PM PDT 24 |
155202647 ps |
| T850 |
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.1327343473 |
|
|
Apr 04 12:38:16 PM PDT 24 |
Apr 04 12:38:59 PM PDT 24 |
466790802 ps |
| T851 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.3073487975 |
|
|
Apr 04 12:38:38 PM PDT 24 |
Apr 04 12:49:21 PM PDT 24 |
2727913063 ps |
| T852 |
/workspace/coverage/default/27.sram_ctrl_partial_access.1888720235 |
|
|
Apr 04 12:37:17 PM PDT 24 |
Apr 04 12:37:33 PM PDT 24 |
3322782878 ps |
| T853 |
/workspace/coverage/default/44.sram_ctrl_stress_all.3487885952 |
|
|
Apr 04 12:39:13 PM PDT 24 |
Apr 04 01:24:30 PM PDT 24 |
87945234940 ps |
| T854 |
/workspace/coverage/default/32.sram_ctrl_multiple_keys.902384601 |
|
|
Apr 04 12:37:44 PM PDT 24 |
Apr 04 12:48:32 PM PDT 24 |
21290858326 ps |
| T855 |
/workspace/coverage/default/35.sram_ctrl_multiple_keys.3306805905 |
|
|
Apr 04 12:38:02 PM PDT 24 |
Apr 04 12:44:47 PM PDT 24 |
22270960937 ps |
| T856 |
/workspace/coverage/default/26.sram_ctrl_alert_test.117343793 |
|
|
Apr 04 12:37:21 PM PDT 24 |
Apr 04 12:37:23 PM PDT 24 |
33099267 ps |
| T857 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2699106031 |
|
|
Apr 04 12:36:10 PM PDT 24 |
Apr 04 12:45:09 PM PDT 24 |
14102142617 ps |
| T858 |
/workspace/coverage/default/32.sram_ctrl_mem_partial_access.1617120217 |
|
|
Apr 04 12:37:55 PM PDT 24 |
Apr 04 12:37:59 PM PDT 24 |
130060108 ps |
| T859 |
/workspace/coverage/default/15.sram_ctrl_stress_all.59815086 |
|
|
Apr 04 12:36:42 PM PDT 24 |
Apr 04 02:23:48 PM PDT 24 |
283751251533 ps |
| T860 |
/workspace/coverage/default/36.sram_ctrl_partial_access.3457708697 |
|
|
Apr 04 12:38:11 PM PDT 24 |
Apr 04 12:38:27 PM PDT 24 |
887019878 ps |
| T861 |
/workspace/coverage/default/19.sram_ctrl_ram_cfg.1386751352 |
|
|
Apr 04 12:36:45 PM PDT 24 |
Apr 04 12:36:46 PM PDT 24 |
28703190 ps |
| T862 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.4101376607 |
|
|
Apr 04 12:36:28 PM PDT 24 |
Apr 04 12:38:05 PM PDT 24 |
1796560240 ps |
| T863 |
/workspace/coverage/default/42.sram_ctrl_executable.1032094541 |
|
|
Apr 04 12:38:54 PM PDT 24 |
Apr 04 12:53:05 PM PDT 24 |
52107283027 ps |
| T864 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.1099971761 |
|
|
Apr 04 12:36:28 PM PDT 24 |
Apr 04 12:36:38 PM PDT 24 |
4996794934 ps |
| T865 |
/workspace/coverage/default/13.sram_ctrl_mem_walk.2547171397 |
|
|
Apr 04 12:36:33 PM PDT 24 |
Apr 04 12:36:41 PM PDT 24 |
521472957 ps |
| T866 |
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1279235612 |
|
|
Apr 04 12:39:27 PM PDT 24 |
Apr 04 12:45:04 PM PDT 24 |
14156811489 ps |
| T867 |
/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.3403484115 |
|
|
Apr 04 12:37:20 PM PDT 24 |
Apr 04 12:41:52 PM PDT 24 |
3945915580 ps |
| T868 |
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.4007083887 |
|
|
Apr 04 12:36:43 PM PDT 24 |
Apr 04 12:38:23 PM PDT 24 |
12795044367 ps |
| T869 |
/workspace/coverage/default/20.sram_ctrl_access_during_key_req.1909110816 |
|
|
Apr 04 12:36:50 PM PDT 24 |
Apr 04 01:00:04 PM PDT 24 |
2589820104 ps |
| T870 |
/workspace/coverage/default/20.sram_ctrl_mem_partial_access.3844744592 |
|
|
Apr 04 12:36:55 PM PDT 24 |
Apr 04 12:37:01 PM PDT 24 |
593020317 ps |
| T871 |
/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.1720193888 |
|
|
Apr 04 12:35:51 PM PDT 24 |
Apr 04 12:36:31 PM PDT 24 |
99822076 ps |
| T872 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.1616456198 |
|
|
Apr 04 12:36:06 PM PDT 24 |
Apr 04 12:36:09 PM PDT 24 |
42656928 ps |
| T873 |
/workspace/coverage/default/31.sram_ctrl_lc_escalation.636915044 |
|
|
Apr 04 12:37:50 PM PDT 24 |
Apr 04 12:37:56 PM PDT 24 |
895054701 ps |
| T874 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3394179172 |
|
|
Apr 04 12:36:43 PM PDT 24 |
Apr 04 12:37:46 PM PDT 24 |
417646173 ps |
| T875 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2146414677 |
|
|
Apr 04 12:35:49 PM PDT 24 |
Apr 04 12:37:54 PM PDT 24 |
732696156 ps |
| T876 |
/workspace/coverage/default/34.sram_ctrl_regwen.1347801511 |
|
|
Apr 04 12:38:01 PM PDT 24 |
Apr 04 12:45:19 PM PDT 24 |
13652939477 ps |
| T877 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.2861827414 |
|
|
Apr 04 12:38:17 PM PDT 24 |
Apr 04 12:38:24 PM PDT 24 |
766541643 ps |
| T878 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.723586951 |
|
|
Apr 04 12:39:07 PM PDT 24 |
Apr 04 12:39:18 PM PDT 24 |
1338785468 ps |
| T879 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.4084718417 |
|
|
Apr 04 12:36:52 PM PDT 24 |
Apr 04 12:36:58 PM PDT 24 |
442044961 ps |
| T880 |
/workspace/coverage/default/43.sram_ctrl_executable.3662136873 |
|
|
Apr 04 12:39:05 PM PDT 24 |
Apr 04 12:56:37 PM PDT 24 |
4545129056 ps |
| T881 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.4159173966 |
|
|
Apr 04 12:38:39 PM PDT 24 |
Apr 04 12:38:49 PM PDT 24 |
1360263321 ps |
| T882 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.1407315521 |
|
|
Apr 04 12:36:31 PM PDT 24 |
Apr 04 12:48:44 PM PDT 24 |
3869328965 ps |
| T883 |
/workspace/coverage/default/23.sram_ctrl_executable.997208495 |
|
|
Apr 04 12:37:06 PM PDT 24 |
Apr 04 12:47:52 PM PDT 24 |
19094722371 ps |
| T884 |
/workspace/coverage/default/38.sram_ctrl_mem_walk.2591063569 |
|
|
Apr 04 12:38:45 PM PDT 24 |
Apr 04 12:38:51 PM PDT 24 |
241197952 ps |
| T885 |
/workspace/coverage/default/12.sram_ctrl_ram_cfg.2848852389 |
|
|
Apr 04 12:36:23 PM PDT 24 |
Apr 04 12:36:24 PM PDT 24 |
46860657 ps |
| T886 |
/workspace/coverage/default/10.sram_ctrl_partial_access.3809574421 |
|
|
Apr 04 12:36:30 PM PDT 24 |
Apr 04 12:37:16 PM PDT 24 |
372885158 ps |
| T887 |
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.3132363273 |
|
|
Apr 04 12:37:36 PM PDT 24 |
Apr 04 12:39:02 PM PDT 24 |
2763258697 ps |
| T888 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.3157033008 |
|
|
Apr 04 12:35:41 PM PDT 24 |
Apr 04 12:43:28 PM PDT 24 |
2288363887 ps |
| T889 |
/workspace/coverage/default/0.sram_ctrl_alert_test.2331520069 |
|
|
Apr 04 12:36:04 PM PDT 24 |
Apr 04 12:36:05 PM PDT 24 |
98719504 ps |
| T890 |
/workspace/coverage/default/43.sram_ctrl_multiple_keys.3621445961 |
|
|
Apr 04 12:38:54 PM PDT 24 |
Apr 04 12:51:00 PM PDT 24 |
4127837740 ps |
| T891 |
/workspace/coverage/default/16.sram_ctrl_executable.3345059948 |
|
|
Apr 04 12:36:36 PM PDT 24 |
Apr 04 01:02:32 PM PDT 24 |
78301754275 ps |
| T892 |
/workspace/coverage/default/27.sram_ctrl_executable.62578200 |
|
|
Apr 04 12:37:27 PM PDT 24 |
Apr 04 12:51:04 PM PDT 24 |
6794638411 ps |
| T893 |
/workspace/coverage/default/20.sram_ctrl_bijection.3970771227 |
|
|
Apr 04 12:36:50 PM PDT 24 |
Apr 04 12:37:27 PM PDT 24 |
2010098856 ps |
| T894 |
/workspace/coverage/default/26.sram_ctrl_access_during_key_req.2467468012 |
|
|
Apr 04 12:37:17 PM PDT 24 |
Apr 04 01:04:18 PM PDT 24 |
3054841000 ps |
| T895 |
/workspace/coverage/default/24.sram_ctrl_executable.3000811917 |
|
|
Apr 04 12:37:09 PM PDT 24 |
Apr 04 12:47:41 PM PDT 24 |
2115181817 ps |
| T896 |
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.4123023459 |
|
|
Apr 04 12:39:03 PM PDT 24 |
Apr 04 12:39:07 PM PDT 24 |
123788351 ps |
| T897 |
/workspace/coverage/default/33.sram_ctrl_mem_partial_access.1826751462 |
|
|
Apr 04 12:37:59 PM PDT 24 |
Apr 04 12:38:05 PM PDT 24 |
173368957 ps |
| T898 |
/workspace/coverage/default/0.sram_ctrl_smoke.3948550783 |
|
|
Apr 04 12:35:52 PM PDT 24 |
Apr 04 12:36:07 PM PDT 24 |
2872626380 ps |
| T899 |
/workspace/coverage/default/3.sram_ctrl_executable.3197102918 |
|
|
Apr 04 12:35:51 PM PDT 24 |
Apr 04 12:54:22 PM PDT 24 |
12821918877 ps |
| T900 |
/workspace/coverage/default/17.sram_ctrl_access_during_key_req.4076698185 |
|
|
Apr 04 12:36:39 PM PDT 24 |
Apr 04 12:48:45 PM PDT 24 |
20201729906 ps |
| T901 |
/workspace/coverage/default/9.sram_ctrl_executable.2443253027 |
|
|
Apr 04 12:36:37 PM PDT 24 |
Apr 04 12:39:22 PM PDT 24 |
809176544 ps |
| T902 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.2724448546 |
|
|
Apr 04 12:38:35 PM PDT 24 |
Apr 04 12:39:43 PM PDT 24 |
224677177 ps |
| T903 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.586241113 |
|
|
Apr 04 12:38:37 PM PDT 24 |
Apr 04 12:41:40 PM PDT 24 |
30650329117 ps |
| T904 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.3537387737 |
|
|
Apr 04 12:38:18 PM PDT 24 |
Apr 04 12:50:57 PM PDT 24 |
56126415847 ps |
| T905 |
/workspace/coverage/default/30.sram_ctrl_regwen.1430420784 |
|
|
Apr 04 12:37:38 PM PDT 24 |
Apr 04 12:42:35 PM PDT 24 |
9398804819 ps |
| T906 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.3945581458 |
|
|
Apr 04 12:35:58 PM PDT 24 |
Apr 04 12:36:05 PM PDT 24 |
1240281229 ps |
| T907 |
/workspace/coverage/default/37.sram_ctrl_mem_partial_access.4024748507 |
|
|
Apr 04 12:38:19 PM PDT 24 |
Apr 04 12:38:24 PM PDT 24 |
66503030 ps |
| T908 |
/workspace/coverage/default/30.sram_ctrl_lc_escalation.2160173596 |
|
|
Apr 04 12:37:33 PM PDT 24 |
Apr 04 12:37:35 PM PDT 24 |
213897451 ps |
| T909 |
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.728318374 |
|
|
Apr 04 12:39:04 PM PDT 24 |
Apr 04 12:52:31 PM PDT 24 |
5283273367 ps |
| T910 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.3119638397 |
|
|
Apr 04 12:35:54 PM PDT 24 |
Apr 04 12:37:23 PM PDT 24 |
489114983 ps |
| T911 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.3339526039 |
|
|
Apr 04 12:36:43 PM PDT 24 |
Apr 04 12:39:10 PM PDT 24 |
6665060823 ps |
| T912 |
/workspace/coverage/default/43.sram_ctrl_regwen.4100612607 |
|
|
Apr 04 12:39:05 PM PDT 24 |
Apr 04 12:43:41 PM PDT 24 |
4609855832 ps |
| T913 |
/workspace/coverage/default/30.sram_ctrl_executable.4283342957 |
|
|
Apr 04 12:37:38 PM PDT 24 |
Apr 04 12:48:48 PM PDT 24 |
7385109777 ps |
| T914 |
/workspace/coverage/default/48.sram_ctrl_regwen.966322865 |
|
|
Apr 04 12:39:31 PM PDT 24 |
Apr 04 12:56:07 PM PDT 24 |
19333298624 ps |
| T915 |
/workspace/coverage/default/2.sram_ctrl_multiple_keys.3839799308 |
|
|
Apr 04 12:36:17 PM PDT 24 |
Apr 04 12:48:03 PM PDT 24 |
1505716656 ps |
| T916 |
/workspace/coverage/default/26.sram_ctrl_stress_all.4264785465 |
|
|
Apr 04 12:37:22 PM PDT 24 |
Apr 04 12:53:41 PM PDT 24 |
7236986960 ps |
| T917 |
/workspace/coverage/default/42.sram_ctrl_stress_all.3765759139 |
|
|
Apr 04 12:38:55 PM PDT 24 |
Apr 04 01:10:53 PM PDT 24 |
7457340991 ps |
| T918 |
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2328340416 |
|
|
Apr 04 12:36:14 PM PDT 24 |
Apr 04 12:36:51 PM PDT 24 |
128573642 ps |
| T919 |
/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.874292308 |
|
|
Apr 04 12:36:05 PM PDT 24 |
Apr 04 12:36:26 PM PDT 24 |
214062158 ps |
| T920 |
/workspace/coverage/default/24.sram_ctrl_stress_pipeline.3818646907 |
|
|
Apr 04 12:37:01 PM PDT 24 |
Apr 04 12:40:22 PM PDT 24 |
2394467831 ps |
| T921 |
/workspace/coverage/default/34.sram_ctrl_executable.480110355 |
|
|
Apr 04 12:38:10 PM PDT 24 |
Apr 04 12:46:56 PM PDT 24 |
7814356698 ps |
| T922 |
/workspace/coverage/default/42.sram_ctrl_bijection.1149880210 |
|
|
Apr 04 12:38:46 PM PDT 24 |
Apr 04 12:39:57 PM PDT 24 |
4559496791 ps |
| T923 |
/workspace/coverage/default/25.sram_ctrl_multiple_keys.452517875 |
|
|
Apr 04 12:37:20 PM PDT 24 |
Apr 04 12:38:19 PM PDT 24 |
312300175 ps |
| T924 |
/workspace/coverage/default/32.sram_ctrl_max_throughput.984046987 |
|
|
Apr 04 12:37:43 PM PDT 24 |
Apr 04 12:37:47 PM PDT 24 |
210467077 ps |
| T925 |
/workspace/coverage/default/21.sram_ctrl_lc_escalation.2262512654 |
|
|
Apr 04 12:36:55 PM PDT 24 |
Apr 04 12:37:06 PM PDT 24 |
2470174974 ps |
| T926 |
/workspace/coverage/default/40.sram_ctrl_access_during_key_req.1778730208 |
|
|
Apr 04 12:38:39 PM PDT 24 |
Apr 04 01:01:00 PM PDT 24 |
3996687220 ps |
| T927 |
/workspace/coverage/default/7.sram_ctrl_regwen.4087061407 |
|
|
Apr 04 12:36:23 PM PDT 24 |
Apr 04 12:37:42 PM PDT 24 |
2252750932 ps |
| T928 |
/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.1325635833 |
|
|
Apr 04 12:37:02 PM PDT 24 |
Apr 04 12:37:04 PM PDT 24 |
41603934 ps |
| T929 |
/workspace/coverage/default/39.sram_ctrl_mem_partial_access.255383297 |
|
|
Apr 04 12:38:41 PM PDT 24 |
Apr 04 12:38:46 PM PDT 24 |
124607692 ps |
| T930 |
/workspace/coverage/default/43.sram_ctrl_bijection.2202788429 |
|
|
Apr 04 12:38:54 PM PDT 24 |
Apr 04 12:39:21 PM PDT 24 |
2712573260 ps |
| T931 |
/workspace/coverage/default/41.sram_ctrl_lc_escalation.1243083902 |
|
|
Apr 04 12:38:45 PM PDT 24 |
Apr 04 12:38:50 PM PDT 24 |
1542944030 ps |
| T932 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.2397936867 |
|
|
Apr 04 12:37:22 PM PDT 24 |
Apr 04 12:37:25 PM PDT 24 |
85411493 ps |
| T933 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1725848880 |
|
|
Apr 04 03:35:55 PM PDT 24 |
Apr 04 03:35:58 PM PDT 24 |
149881914 ps |
| T87 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1752152407 |
|
|
Apr 04 03:35:54 PM PDT 24 |
Apr 04 03:35:55 PM PDT 24 |
82702253 ps |
| T57 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.398599366 |
|
|
Apr 04 03:35:51 PM PDT 24 |
Apr 04 03:35:51 PM PDT 24 |
76263411 ps |
| T58 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.956736726 |
|
|
Apr 04 03:35:53 PM PDT 24 |
Apr 04 03:35:54 PM PDT 24 |
13330518 ps |
| T934 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2991042074 |
|
|
Apr 04 03:35:53 PM PDT 24 |
Apr 04 03:35:56 PM PDT 24 |
106487032 ps |
| T935 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1954728367 |
|
|
Apr 04 03:35:51 PM PDT 24 |
Apr 04 03:35:53 PM PDT 24 |
42120449 ps |
| T59 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1502002320 |
|
|
Apr 04 03:35:54 PM PDT 24 |
Apr 04 03:35:56 PM PDT 24 |
1662066010 ps |
| T60 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.719296780 |
|
|
Apr 04 03:35:35 PM PDT 24 |
Apr 04 03:35:36 PM PDT 24 |
31425931 ps |
| T95 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1199296384 |
|
|
Apr 04 03:35:51 PM PDT 24 |
Apr 04 03:35:52 PM PDT 24 |
192439952 ps |
| T936 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3126231790 |
|
|
Apr 04 03:35:50 PM PDT 24 |
Apr 04 03:35:52 PM PDT 24 |
58492671 ps |
| T61 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.382901203 |
|
|
Apr 04 03:35:52 PM PDT 24 |
Apr 04 03:35:52 PM PDT 24 |
41856453 ps |
| T62 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.4197770104 |
|
|
Apr 04 03:35:35 PM PDT 24 |
Apr 04 03:35:35 PM PDT 24 |
14863472 ps |
| T88 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.511468890 |
|
|
Apr 04 03:35:55 PM PDT 24 |
Apr 04 03:35:56 PM PDT 24 |
65868197 ps |
| T89 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2113847725 |
|
|
Apr 04 03:35:55 PM PDT 24 |
Apr 04 03:35:55 PM PDT 24 |
34539796 ps |
| T63 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1541493787 |
|
|
Apr 04 03:35:36 PM PDT 24 |
Apr 04 03:35:38 PM PDT 24 |
1142504373 ps |
| T96 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.340713950 |
|
|
Apr 04 03:35:54 PM PDT 24 |
Apr 04 03:35:56 PM PDT 24 |
105329923 ps |
| T937 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.873446605 |
|
|
Apr 04 03:35:53 PM PDT 24 |
Apr 04 03:35:54 PM PDT 24 |
37294387 ps |
| T64 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.595950068 |
|
|
Apr 04 03:35:51 PM PDT 24 |
Apr 04 03:35:53 PM PDT 24 |
372544662 ps |
| T65 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.234072197 |
|
|
Apr 04 03:35:52 PM PDT 24 |
Apr 04 03:35:54 PM PDT 24 |
2498164722 ps |
| T938 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1254857862 |
|
|
Apr 04 03:35:57 PM PDT 24 |
Apr 04 03:35:59 PM PDT 24 |
34324621 ps |
| T66 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.789829771 |
|
|
Apr 04 03:35:34 PM PDT 24 |
Apr 04 03:35:37 PM PDT 24 |
1553815783 ps |
| T90 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2355253803 |
|
|
Apr 04 03:35:23 PM PDT 24 |
Apr 04 03:35:24 PM PDT 24 |
38782165 ps |
| T939 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3468963681 |
|
|
Apr 04 03:35:37 PM PDT 24 |
Apr 04 03:35:38 PM PDT 24 |
334204691 ps |
| T940 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3433906044 |
|
|
Apr 04 03:35:51 PM PDT 24 |
Apr 04 03:35:54 PM PDT 24 |
424850319 ps |
| T97 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2760619640 |
|
|
Apr 04 03:35:55 PM PDT 24 |
Apr 04 03:35:56 PM PDT 24 |
137896415 ps |
| T79 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.984906250 |
|
|
Apr 04 03:35:36 PM PDT 24 |
Apr 04 03:35:39 PM PDT 24 |
2584785696 ps |
| T112 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2757891026 |
|
|
Apr 04 03:35:57 PM PDT 24 |
Apr 04 03:35:59 PM PDT 24 |
362211004 ps |
| T110 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.576974143 |
|
|
Apr 04 03:35:34 PM PDT 24 |
Apr 04 03:35:35 PM PDT 24 |
243735327 ps |
| T111 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.842705407 |
|
|
Apr 04 03:35:54 PM PDT 24 |
Apr 04 03:35:56 PM PDT 24 |
507861077 ps |
| T941 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3466029462 |
|
|
Apr 04 03:35:36 PM PDT 24 |
Apr 04 03:35:36 PM PDT 24 |
16668880 ps |
| T91 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.684378270 |
|
|
Apr 04 03:35:53 PM PDT 24 |
Apr 04 03:35:54 PM PDT 24 |
21516500 ps |
| T942 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.4245478385 |
|
|
Apr 04 03:35:35 PM PDT 24 |
Apr 04 03:35:36 PM PDT 24 |
16592857 ps |
| T107 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.4128900583 |
|
|
Apr 04 03:35:24 PM PDT 24 |
Apr 04 03:35:26 PM PDT 24 |
846514472 ps |
| T943 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3479385681 |
|
|
Apr 04 03:35:55 PM PDT 24 |
Apr 04 03:35:56 PM PDT 24 |
49479905 ps |
| T944 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3705917314 |
|
|
Apr 04 03:35:54 PM PDT 24 |
Apr 04 03:35:55 PM PDT 24 |
26590878 ps |
| T105 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1436146730 |
|
|
Apr 04 03:35:23 PM PDT 24 |
Apr 04 03:35:24 PM PDT 24 |
97634323 ps |
| T69 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1124390119 |
|
|
Apr 04 03:35:56 PM PDT 24 |
Apr 04 03:35:59 PM PDT 24 |
1830378379 ps |
| T945 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3363227457 |
|
|
Apr 04 03:35:39 PM PDT 24 |
Apr 04 03:35:41 PM PDT 24 |
22097595 ps |
| T946 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.285002104 |
|
|
Apr 04 03:35:55 PM PDT 24 |
Apr 04 03:35:56 PM PDT 24 |
17668799 ps |
| T947 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.949171767 |
|
|
Apr 04 03:35:53 PM PDT 24 |
Apr 04 03:35:57 PM PDT 24 |
131390706 ps |
| T70 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3425163147 |
|
|
Apr 04 03:35:54 PM PDT 24 |
Apr 04 03:35:57 PM PDT 24 |
382614536 ps |
| T948 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.327050958 |
|
|
Apr 04 03:35:52 PM PDT 24 |
Apr 04 03:35:53 PM PDT 24 |
18120495 ps |
| T71 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3292781361 |
|
|
Apr 04 03:35:55 PM PDT 24 |
Apr 04 03:35:59 PM PDT 24 |
3361468449 ps |
| T116 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3007761344 |
|
|
Apr 04 03:35:52 PM PDT 24 |
Apr 04 03:35:54 PM PDT 24 |
374288855 ps |
| T106 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1969404197 |
|
|
Apr 04 03:35:55 PM PDT 24 |
Apr 04 03:35:56 PM PDT 24 |
107172120 ps |
| T949 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1681711084 |
|
|
Apr 04 03:36:07 PM PDT 24 |
Apr 04 03:36:11 PM PDT 24 |
1779952390 ps |
| T950 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3821000548 |
|
|
Apr 04 03:35:58 PM PDT 24 |
Apr 04 03:35:59 PM PDT 24 |
172522774 ps |
| T72 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2966546131 |
|
|
Apr 04 03:35:55 PM PDT 24 |
Apr 04 03:35:55 PM PDT 24 |
34807773 ps |
| T117 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2988605260 |
|
|
Apr 04 03:35:53 PM PDT 24 |
Apr 04 03:35:55 PM PDT 24 |
120821029 ps |
| T951 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1381835265 |
|
|
Apr 04 03:35:35 PM PDT 24 |
Apr 04 03:35:36 PM PDT 24 |
51329287 ps |
| T952 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.4029160304 |
|
|
Apr 04 03:35:55 PM PDT 24 |
Apr 04 03:35:58 PM PDT 24 |
122073832 ps |
| T73 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.4035201297 |
|
|
Apr 04 03:35:21 PM PDT 24 |
Apr 04 03:35:23 PM PDT 24 |
211793062 ps |
| T953 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1890386628 |
|
|
Apr 04 03:35:56 PM PDT 24 |
Apr 04 03:35:57 PM PDT 24 |
172962740 ps |
| T80 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3682881585 |
|
|
Apr 04 03:35:55 PM PDT 24 |
Apr 04 03:35:56 PM PDT 24 |
16691841 ps |
| T954 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.272877979 |
|
|
Apr 04 03:35:58 PM PDT 24 |
Apr 04 03:36:00 PM PDT 24 |
127826203 ps |
| T955 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1847506721 |
|
|
Apr 04 03:35:27 PM PDT 24 |
Apr 04 03:35:28 PM PDT 24 |
38133369 ps |
| T956 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2416270664 |
|
|
Apr 04 03:35:54 PM PDT 24 |
Apr 04 03:35:56 PM PDT 24 |
164894707 ps |
| T957 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2155760651 |
|
|
Apr 04 03:35:55 PM PDT 24 |
Apr 04 03:35:56 PM PDT 24 |
13463922 ps |
| T81 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2718151976 |
|
|
Apr 04 03:35:53 PM PDT 24 |
Apr 04 03:35:55 PM PDT 24 |
2875785292 ps |
| T958 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2322476228 |
|
|
Apr 04 03:35:55 PM PDT 24 |
Apr 04 03:35:56 PM PDT 24 |
181500000 ps |
| T959 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1655053699 |
|
|
Apr 04 03:35:21 PM PDT 24 |
Apr 04 03:35:22 PM PDT 24 |
16038248 ps |
| T82 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.559805122 |
|
|
Apr 04 03:35:56 PM PDT 24 |
Apr 04 03:36:00 PM PDT 24 |
1901630198 ps |
| T960 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.571755137 |
|
|
Apr 04 03:35:50 PM PDT 24 |
Apr 04 03:35:56 PM PDT 24 |
195375161 ps |
| T961 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.4084989549 |
|
|
Apr 04 03:35:21 PM PDT 24 |
Apr 04 03:35:25 PM PDT 24 |
139510612 ps |
| T962 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.322218384 |
|
|
Apr 04 03:35:54 PM PDT 24 |
Apr 04 03:35:55 PM PDT 24 |
47024667 ps |
| T963 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1427484515 |
|
|
Apr 04 03:35:57 PM PDT 24 |
Apr 04 03:35:57 PM PDT 24 |
23815986 ps |
| T964 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2876052338 |
|
|
Apr 04 03:35:36 PM PDT 24 |
Apr 04 03:35:37 PM PDT 24 |
122922959 ps |
| T965 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2373663542 |
|
|
Apr 04 03:35:55 PM PDT 24 |
Apr 04 03:35:56 PM PDT 24 |
28786190 ps |
| T966 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.223185099 |
|
|
Apr 04 03:35:54 PM PDT 24 |
Apr 04 03:35:56 PM PDT 24 |
69828888 ps |
| T115 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1368394964 |
|
|
Apr 04 03:35:55 PM PDT 24 |
Apr 04 03:35:58 PM PDT 24 |
204595441 ps |
| T967 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3386822483 |
|
|
Apr 04 03:35:35 PM PDT 24 |
Apr 04 03:35:35 PM PDT 24 |
29653361 ps |
| T968 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1117201019 |
|
|
Apr 04 03:35:56 PM PDT 24 |
Apr 04 03:35:58 PM PDT 24 |
28665610 ps |
| T969 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3814017306 |
|
|
Apr 04 03:35:22 PM PDT 24 |
Apr 04 03:35:23 PM PDT 24 |
21836194 ps |
| T970 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1361384288 |
|
|
Apr 04 03:36:03 PM PDT 24 |
Apr 04 03:36:04 PM PDT 24 |
101951440 ps |
| T83 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2941133830 |
|
|
Apr 04 03:35:56 PM PDT 24 |
Apr 04 03:35:58 PM PDT 24 |
854632614 ps |
| T971 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.634495173 |
|
|
Apr 04 03:35:35 PM PDT 24 |
Apr 04 03:35:36 PM PDT 24 |
29579976 ps |
| T113 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.699359650 |
|
|
Apr 04 03:35:53 PM PDT 24 |
Apr 04 03:35:55 PM PDT 24 |
202228346 ps |
| T972 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.956528524 |
|
|
Apr 04 03:35:58 PM PDT 24 |
Apr 04 03:36:00 PM PDT 24 |
32226389 ps |
| T118 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1782603566 |
|
|
Apr 04 03:35:55 PM PDT 24 |
Apr 04 03:35:57 PM PDT 24 |
141926701 ps |
| T973 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2944452267 |
|
|
Apr 04 03:35:50 PM PDT 24 |
Apr 04 03:35:51 PM PDT 24 |
130734378 ps |
| T974 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3731214319 |
|
|
Apr 04 03:35:35 PM PDT 24 |
Apr 04 03:35:36 PM PDT 24 |
94513453 ps |
| T84 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3643563335 |
|
|
Apr 04 03:35:20 PM PDT 24 |
Apr 04 03:35:22 PM PDT 24 |
81593558 ps |
| T975 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.640438655 |
|
|
Apr 04 03:35:52 PM PDT 24 |
Apr 04 03:35:55 PM PDT 24 |
33140054 ps |
| T976 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2729328135 |
|
|
Apr 04 03:35:58 PM PDT 24 |
Apr 04 03:36:00 PM PDT 24 |
127611183 ps |
| T977 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.82903981 |
|
|
Apr 04 03:35:56 PM PDT 24 |
Apr 04 03:35:57 PM PDT 24 |
156937559 ps |
| T978 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3243430025 |
|
|
Apr 04 03:35:56 PM PDT 24 |
Apr 04 03:36:00 PM PDT 24 |
49754067 ps |
| T979 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.802594902 |
|
|
Apr 04 03:35:58 PM PDT 24 |
Apr 04 03:36:00 PM PDT 24 |
53685539 ps |
| T85 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3240423578 |
|
|
Apr 04 03:35:38 PM PDT 24 |
Apr 04 03:35:39 PM PDT 24 |
23794794 ps |
| T980 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3030915203 |
|
|
Apr 04 03:35:55 PM PDT 24 |
Apr 04 03:35:59 PM PDT 24 |
1550539257 ps |
| T981 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2938644125 |
|
|
Apr 04 03:35:53 PM PDT 24 |
Apr 04 03:35:54 PM PDT 24 |
125790826 ps |
| T982 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2075104599 |
|
|
Apr 04 03:35:36 PM PDT 24 |
Apr 04 03:35:36 PM PDT 24 |
18374115 ps |
| T983 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3989300570 |
|
|
Apr 04 03:35:53 PM PDT 24 |
Apr 04 03:35:56 PM PDT 24 |
1211920580 ps |
| T984 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2394718332 |
|
|
Apr 04 03:35:55 PM PDT 24 |
Apr 04 03:35:56 PM PDT 24 |
12541176 ps |
| T985 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1922963595 |
|
|
Apr 04 03:35:21 PM PDT 24 |
Apr 04 03:35:22 PM PDT 24 |
11793020 ps |
| T986 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3234020403 |
|
|
Apr 04 03:35:53 PM PDT 24 |
Apr 04 03:35:54 PM PDT 24 |
17664018 ps |
| T987 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1278013806 |
|
|
Apr 04 03:35:52 PM PDT 24 |
Apr 04 03:35:53 PM PDT 24 |
16675084 ps |
| T988 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.11417434 |
|
|
Apr 04 03:35:22 PM PDT 24 |
Apr 04 03:35:23 PM PDT 24 |
11274182 ps |
| T989 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2495721323 |
|
|
Apr 04 03:35:36 PM PDT 24 |
Apr 04 03:35:36 PM PDT 24 |
15809483 ps |
| T990 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.348798083 |
|
|
Apr 04 03:35:21 PM PDT 24 |
Apr 04 03:35:21 PM PDT 24 |
36424518 ps |
| T991 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2348887414 |
|
|
Apr 04 03:35:36 PM PDT 24 |
Apr 04 03:35:38 PM PDT 24 |
101456454 ps |
| T992 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3563937414 |
|
|
Apr 04 03:35:53 PM PDT 24 |
Apr 04 03:35:54 PM PDT 24 |
55097319 ps |
| T993 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3267301763 |
|
|
Apr 04 03:35:55 PM PDT 24 |
Apr 04 03:35:56 PM PDT 24 |
38371287 ps |
| T994 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.379238762 |
|
|
Apr 04 03:35:35 PM PDT 24 |
Apr 04 03:35:36 PM PDT 24 |
21309455 ps |
| T995 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3587611851 |
|
|
Apr 04 03:35:35 PM PDT 24 |
Apr 04 03:35:37 PM PDT 24 |
36602940 ps |
| T996 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.336311911 |
|
|
Apr 04 03:35:55 PM PDT 24 |
Apr 04 03:35:56 PM PDT 24 |
50206898 ps |
| T108 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1462864388 |
|
|
Apr 04 03:35:36 PM PDT 24 |
Apr 04 03:35:39 PM PDT 24 |
446597833 ps |
| T997 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.4246201021 |
|
|
Apr 04 03:35:58 PM PDT 24 |
Apr 04 03:36:01 PM PDT 24 |
1520897261 ps |
| T998 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.724417509 |
|
|
Apr 04 03:35:57 PM PDT 24 |
Apr 04 03:36:00 PM PDT 24 |
1412933302 ps |
| T999 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.258392499 |
|
|
Apr 04 03:35:35 PM PDT 24 |
Apr 04 03:35:36 PM PDT 24 |
29162662 ps |
| T1000 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.146526730 |
|
|
Apr 04 03:35:23 PM PDT 24 |
Apr 04 03:35:28 PM PDT 24 |
119521376 ps |
| T1001 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2356847808 |
|
|
Apr 04 03:35:52 PM PDT 24 |
Apr 04 03:35:53 PM PDT 24 |
44476006 ps |
| T1002 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.176869156 |
|
|
Apr 04 03:35:59 PM PDT 24 |
Apr 04 03:35:59 PM PDT 24 |
27773521 ps |