| T799 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.2243888543 |
|
|
Apr 15 02:30:58 PM PDT 24 |
Apr 15 02:35:06 PM PDT 24 |
9477018107 ps |
| T800 |
/workspace/coverage/default/27.sram_ctrl_executable.4205831428 |
|
|
Apr 15 02:31:40 PM PDT 24 |
Apr 15 02:47:14 PM PDT 24 |
97003292620 ps |
| T801 |
/workspace/coverage/default/35.sram_ctrl_partial_access.60527414 |
|
|
Apr 15 02:32:45 PM PDT 24 |
Apr 15 02:34:35 PM PDT 24 |
210045391 ps |
| T802 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.2417480789 |
|
|
Apr 15 02:30:27 PM PDT 24 |
Apr 15 02:30:30 PM PDT 24 |
174224872 ps |
| T34 |
/workspace/coverage/default/3.sram_ctrl_sec_cm.4285741206 |
|
|
Apr 15 02:29:56 PM PDT 24 |
Apr 15 02:30:00 PM PDT 24 |
894900219 ps |
| T803 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.3634572154 |
|
|
Apr 15 02:30:25 PM PDT 24 |
Apr 15 02:30:35 PM PDT 24 |
898215459 ps |
| T804 |
/workspace/coverage/default/14.sram_ctrl_executable.681686568 |
|
|
Apr 15 02:30:32 PM PDT 24 |
Apr 15 02:51:09 PM PDT 24 |
25101010816 ps |
| T805 |
/workspace/coverage/default/5.sram_ctrl_bijection.65205814 |
|
|
Apr 15 02:30:01 PM PDT 24 |
Apr 15 02:30:23 PM PDT 24 |
4734744661 ps |
| T806 |
/workspace/coverage/default/32.sram_ctrl_alert_test.4128828059 |
|
|
Apr 15 02:32:33 PM PDT 24 |
Apr 15 02:32:34 PM PDT 24 |
13084997 ps |
| T807 |
/workspace/coverage/default/19.sram_ctrl_stress_pipeline.1067690495 |
|
|
Apr 15 02:30:55 PM PDT 24 |
Apr 15 02:34:50 PM PDT 24 |
5077037270 ps |
| T808 |
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.3569093565 |
|
|
Apr 15 02:30:35 PM PDT 24 |
Apr 15 02:31:48 PM PDT 24 |
131930856 ps |
| T809 |
/workspace/coverage/default/38.sram_ctrl_bijection.581906339 |
|
|
Apr 15 02:33:16 PM PDT 24 |
Apr 15 02:34:24 PM PDT 24 |
1191821083 ps |
| T810 |
/workspace/coverage/default/27.sram_ctrl_lc_escalation.2923893724 |
|
|
Apr 15 02:31:42 PM PDT 24 |
Apr 15 02:31:45 PM PDT 24 |
157517176 ps |
| T811 |
/workspace/coverage/default/17.sram_ctrl_mem_walk.2685567530 |
|
|
Apr 15 02:30:46 PM PDT 24 |
Apr 15 02:30:57 PM PDT 24 |
2730635057 ps |
| T812 |
/workspace/coverage/default/17.sram_ctrl_smoke.3205805590 |
|
|
Apr 15 02:30:43 PM PDT 24 |
Apr 15 02:30:52 PM PDT 24 |
450132228 ps |
| T813 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.321693572 |
|
|
Apr 15 02:30:03 PM PDT 24 |
Apr 15 02:30:10 PM PDT 24 |
1476493301 ps |
| T814 |
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3827834023 |
|
|
Apr 15 02:30:17 PM PDT 24 |
Apr 15 02:35:07 PM PDT 24 |
46117151976 ps |
| T815 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1533919191 |
|
|
Apr 15 02:34:02 PM PDT 24 |
Apr 15 02:37:48 PM PDT 24 |
6350736380 ps |
| T816 |
/workspace/coverage/default/46.sram_ctrl_regwen.3199367038 |
|
|
Apr 15 02:34:37 PM PDT 24 |
Apr 15 02:42:51 PM PDT 24 |
13925314181 ps |
| T817 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.2715112108 |
|
|
Apr 15 02:33:17 PM PDT 24 |
Apr 15 02:45:39 PM PDT 24 |
5347656401 ps |
| T818 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.736091362 |
|
|
Apr 15 02:32:08 PM PDT 24 |
Apr 15 02:41:44 PM PDT 24 |
20899298015 ps |
| T819 |
/workspace/coverage/default/15.sram_ctrl_ram_cfg.4123960124 |
|
|
Apr 15 02:30:36 PM PDT 24 |
Apr 15 02:30:37 PM PDT 24 |
83716939 ps |
| T820 |
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.2436100830 |
|
|
Apr 15 02:31:14 PM PDT 24 |
Apr 15 02:35:03 PM PDT 24 |
9242933005 ps |
| T821 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.1588584554 |
|
|
Apr 15 02:29:44 PM PDT 24 |
Apr 15 02:29:50 PM PDT 24 |
1617763945 ps |
| T822 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.1795218266 |
|
|
Apr 15 02:30:31 PM PDT 24 |
Apr 15 02:30:33 PM PDT 24 |
81189805 ps |
| T823 |
/workspace/coverage/default/36.sram_ctrl_partial_access.942897444 |
|
|
Apr 15 02:32:58 PM PDT 24 |
Apr 15 02:33:17 PM PDT 24 |
1019474619 ps |
| T824 |
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.273430836 |
|
|
Apr 15 02:32:52 PM PDT 24 |
Apr 15 02:36:41 PM PDT 24 |
4753013755 ps |
| T825 |
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.562272165 |
|
|
Apr 15 02:30:03 PM PDT 24 |
Apr 15 02:44:53 PM PDT 24 |
3518031335 ps |
| T826 |
/workspace/coverage/default/6.sram_ctrl_max_throughput.1685432573 |
|
|
Apr 15 02:30:01 PM PDT 24 |
Apr 15 02:32:37 PM PDT 24 |
1607291237 ps |
| T827 |
/workspace/coverage/default/14.sram_ctrl_partial_access.2130798240 |
|
|
Apr 15 02:30:33 PM PDT 24 |
Apr 15 02:30:36 PM PDT 24 |
115150914 ps |
| T828 |
/workspace/coverage/default/1.sram_ctrl_partial_access.1797333144 |
|
|
Apr 15 02:29:49 PM PDT 24 |
Apr 15 02:30:07 PM PDT 24 |
1252844814 ps |
| T829 |
/workspace/coverage/default/44.sram_ctrl_smoke.3876359120 |
|
|
Apr 15 02:34:12 PM PDT 24 |
Apr 15 02:34:16 PM PDT 24 |
65026875 ps |
| T830 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.2164613949 |
|
|
Apr 15 02:31:38 PM PDT 24 |
Apr 15 02:35:45 PM PDT 24 |
3020038603 ps |
| T831 |
/workspace/coverage/default/48.sram_ctrl_regwen.475179271 |
|
|
Apr 15 02:34:58 PM PDT 24 |
Apr 15 02:49:03 PM PDT 24 |
9235170260 ps |
| T832 |
/workspace/coverage/default/34.sram_ctrl_lc_escalation.97758694 |
|
|
Apr 15 02:32:41 PM PDT 24 |
Apr 15 02:32:48 PM PDT 24 |
1969283813 ps |
| T833 |
/workspace/coverage/default/4.sram_ctrl_regwen.1503684597 |
|
|
Apr 15 02:29:57 PM PDT 24 |
Apr 15 02:45:57 PM PDT 24 |
2615583573 ps |
| T834 |
/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.2556764581 |
|
|
Apr 15 02:30:00 PM PDT 24 |
Apr 15 02:37:10 PM PDT 24 |
19524597842 ps |
| T835 |
/workspace/coverage/default/38.sram_ctrl_max_throughput.3531191060 |
|
|
Apr 15 02:33:20 PM PDT 24 |
Apr 15 02:35:11 PM PDT 24 |
137521365 ps |
| T836 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.113981 |
|
|
Apr 15 02:32:36 PM PDT 24 |
Apr 15 02:32:47 PM PDT 24 |
858383366 ps |
| T837 |
/workspace/coverage/default/46.sram_ctrl_stress_all.1226946560 |
|
|
Apr 15 02:34:41 PM PDT 24 |
Apr 15 03:38:56 PM PDT 24 |
497632959141 ps |
| T838 |
/workspace/coverage/default/19.sram_ctrl_stress_all.846664249 |
|
|
Apr 15 02:30:57 PM PDT 24 |
Apr 15 03:10:51 PM PDT 24 |
15854626898 ps |
| T839 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.1680813483 |
|
|
Apr 15 02:29:48 PM PDT 24 |
Apr 15 02:32:28 PM PDT 24 |
4028312398 ps |
| T840 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.3117453895 |
|
|
Apr 15 02:31:11 PM PDT 24 |
Apr 15 02:33:05 PM PDT 24 |
237270768 ps |
| T113 |
/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.451503385 |
|
|
Apr 15 02:33:20 PM PDT 24 |
Apr 15 02:33:58 PM PDT 24 |
1314981122 ps |
| T841 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2390044252 |
|
|
Apr 15 02:30:14 PM PDT 24 |
Apr 15 02:35:04 PM PDT 24 |
8098349330 ps |
| T842 |
/workspace/coverage/default/33.sram_ctrl_access_during_key_req.3952362011 |
|
|
Apr 15 02:32:36 PM PDT 24 |
Apr 15 02:33:18 PM PDT 24 |
727617708 ps |
| T843 |
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.637912107 |
|
|
Apr 15 02:30:16 PM PDT 24 |
Apr 15 02:30:47 PM PDT 24 |
92776632 ps |
| T844 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.835794210 |
|
|
Apr 15 02:32:34 PM PDT 24 |
Apr 15 02:36:56 PM PDT 24 |
7076174273 ps |
| T845 |
/workspace/coverage/default/49.sram_ctrl_stress_all.4165071514 |
|
|
Apr 15 02:35:11 PM PDT 24 |
Apr 15 03:57:47 PM PDT 24 |
192642572041 ps |
| T846 |
/workspace/coverage/default/23.sram_ctrl_mem_walk.653968815 |
|
|
Apr 15 02:31:18 PM PDT 24 |
Apr 15 02:31:24 PM PDT 24 |
471906677 ps |
| T847 |
/workspace/coverage/default/31.sram_ctrl_partial_access.320818137 |
|
|
Apr 15 02:32:16 PM PDT 24 |
Apr 15 02:32:17 PM PDT 24 |
241349957 ps |
| T848 |
/workspace/coverage/default/2.sram_ctrl_lc_escalation.2723780212 |
|
|
Apr 15 02:29:54 PM PDT 24 |
Apr 15 02:29:57 PM PDT 24 |
147234473 ps |
| T849 |
/workspace/coverage/default/45.sram_ctrl_stress_all.2487268436 |
|
|
Apr 15 02:34:29 PM PDT 24 |
Apr 15 03:30:46 PM PDT 24 |
196725020402 ps |
| T850 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.2210902099 |
|
|
Apr 15 02:35:07 PM PDT 24 |
Apr 15 02:39:11 PM PDT 24 |
2798885963 ps |
| T851 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.2512399215 |
|
|
Apr 15 02:29:46 PM PDT 24 |
Apr 15 02:40:00 PM PDT 24 |
1987555354 ps |
| T852 |
/workspace/coverage/default/37.sram_ctrl_partial_access.848102539 |
|
|
Apr 15 02:33:08 PM PDT 24 |
Apr 15 02:33:50 PM PDT 24 |
154804116 ps |
| T853 |
/workspace/coverage/default/41.sram_ctrl_bijection.1577106876 |
|
|
Apr 15 02:33:43 PM PDT 24 |
Apr 15 02:34:38 PM PDT 24 |
872713844 ps |
| T854 |
/workspace/coverage/default/27.sram_ctrl_partial_access.136174535 |
|
|
Apr 15 02:31:40 PM PDT 24 |
Apr 15 02:33:25 PM PDT 24 |
1141145282 ps |
| T855 |
/workspace/coverage/default/49.sram_ctrl_alert_test.3859702335 |
|
|
Apr 15 02:35:11 PM PDT 24 |
Apr 15 02:35:12 PM PDT 24 |
14194290 ps |
| T856 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.2467082244 |
|
|
Apr 15 02:34:40 PM PDT 24 |
Apr 15 02:50:51 PM PDT 24 |
7011073527 ps |
| T857 |
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.685266560 |
|
|
Apr 15 02:33:01 PM PDT 24 |
Apr 15 02:33:07 PM PDT 24 |
664139267 ps |
| T858 |
/workspace/coverage/default/25.sram_ctrl_partial_access.3787189043 |
|
|
Apr 15 02:31:29 PM PDT 24 |
Apr 15 02:32:08 PM PDT 24 |
508347857 ps |
| T859 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.2894787100 |
|
|
Apr 15 02:33:18 PM PDT 24 |
Apr 15 02:33:23 PM PDT 24 |
349263359 ps |
| T860 |
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.1501858030 |
|
|
Apr 15 02:34:28 PM PDT 24 |
Apr 15 02:52:53 PM PDT 24 |
13892622896 ps |
| T861 |
/workspace/coverage/default/36.sram_ctrl_alert_test.3172501201 |
|
|
Apr 15 02:33:07 PM PDT 24 |
Apr 15 02:33:08 PM PDT 24 |
19221935 ps |
| T862 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.1633008334 |
|
|
Apr 15 02:30:09 PM PDT 24 |
Apr 15 02:33:38 PM PDT 24 |
9216223887 ps |
| T863 |
/workspace/coverage/default/20.sram_ctrl_partial_access.2167312838 |
|
|
Apr 15 02:30:57 PM PDT 24 |
Apr 15 02:31:13 PM PDT 24 |
1825140437 ps |
| T864 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.754632875 |
|
|
Apr 15 02:31:17 PM PDT 24 |
Apr 15 02:36:34 PM PDT 24 |
36873125021 ps |
| T865 |
/workspace/coverage/default/38.sram_ctrl_access_during_key_req.3424923700 |
|
|
Apr 15 02:33:19 PM PDT 24 |
Apr 15 02:47:18 PM PDT 24 |
3249576409 ps |
| T866 |
/workspace/coverage/default/44.sram_ctrl_executable.2165070579 |
|
|
Apr 15 02:34:14 PM PDT 24 |
Apr 15 02:37:32 PM PDT 24 |
19789328656 ps |
| T867 |
/workspace/coverage/default/42.sram_ctrl_smoke.751904031 |
|
|
Apr 15 02:33:56 PM PDT 24 |
Apr 15 02:34:10 PM PDT 24 |
862812053 ps |
| T35 |
/workspace/coverage/default/1.sram_ctrl_sec_cm.368683244 |
|
|
Apr 15 02:29:48 PM PDT 24 |
Apr 15 02:29:52 PM PDT 24 |
676276431 ps |
| T868 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1189619797 |
|
|
Apr 15 02:34:49 PM PDT 24 |
Apr 15 02:35:49 PM PDT 24 |
750057625 ps |
| T869 |
/workspace/coverage/default/44.sram_ctrl_stress_all.2442464515 |
|
|
Apr 15 02:34:22 PM PDT 24 |
Apr 15 03:21:14 PM PDT 24 |
183124230545 ps |
| T870 |
/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.2977353419 |
|
|
Apr 15 02:32:48 PM PDT 24 |
Apr 15 02:32:55 PM PDT 24 |
680944230 ps |
| T871 |
/workspace/coverage/default/7.sram_ctrl_smoke.3770363378 |
|
|
Apr 15 02:30:13 PM PDT 24 |
Apr 15 02:30:17 PM PDT 24 |
201689866 ps |
| T872 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.3275802832 |
|
|
Apr 15 02:30:36 PM PDT 24 |
Apr 15 02:34:05 PM PDT 24 |
5959803388 ps |
| T873 |
/workspace/coverage/default/14.sram_ctrl_stress_all.934911522 |
|
|
Apr 15 02:30:32 PM PDT 24 |
Apr 15 03:33:42 PM PDT 24 |
50513710858 ps |
| T874 |
/workspace/coverage/default/35.sram_ctrl_alert_test.3486219987 |
|
|
Apr 15 02:32:52 PM PDT 24 |
Apr 15 02:32:53 PM PDT 24 |
13465363 ps |
| T875 |
/workspace/coverage/default/40.sram_ctrl_partial_access_b2b.4268428557 |
|
|
Apr 15 02:33:35 PM PDT 24 |
Apr 15 02:39:28 PM PDT 24 |
55760433760 ps |
| T876 |
/workspace/coverage/default/21.sram_ctrl_partial_access.600292841 |
|
|
Apr 15 02:31:01 PM PDT 24 |
Apr 15 02:31:10 PM PDT 24 |
4814155792 ps |
| T877 |
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.3090556454 |
|
|
Apr 15 02:34:02 PM PDT 24 |
Apr 15 02:37:33 PM PDT 24 |
2261478717 ps |
| T878 |
/workspace/coverage/default/38.sram_ctrl_alert_test.2448046449 |
|
|
Apr 15 02:33:26 PM PDT 24 |
Apr 15 02:33:27 PM PDT 24 |
34197309 ps |
| T879 |
/workspace/coverage/default/34.sram_ctrl_stress_all.1805663760 |
|
|
Apr 15 02:32:47 PM PDT 24 |
Apr 15 02:57:52 PM PDT 24 |
8600912709 ps |
| T880 |
/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.2667067697 |
|
|
Apr 15 02:30:50 PM PDT 24 |
Apr 15 02:31:56 PM PDT 24 |
452424355 ps |
| T881 |
/workspace/coverage/default/36.sram_ctrl_mem_walk.4250399905 |
|
|
Apr 15 02:33:13 PM PDT 24 |
Apr 15 02:33:19 PM PDT 24 |
231077544 ps |
| T882 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.90115855 |
|
|
Apr 15 02:30:47 PM PDT 24 |
Apr 15 02:33:14 PM PDT 24 |
134663211 ps |
| T883 |
/workspace/coverage/default/0.sram_ctrl_ram_cfg.1914402001 |
|
|
Apr 15 02:29:46 PM PDT 24 |
Apr 15 02:29:48 PM PDT 24 |
105134962 ps |
| T884 |
/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.4242866460 |
|
|
Apr 15 02:32:55 PM PDT 24 |
Apr 15 02:33:39 PM PDT 24 |
427411619 ps |
| T885 |
/workspace/coverage/default/41.sram_ctrl_executable.1127533535 |
|
|
Apr 15 02:33:49 PM PDT 24 |
Apr 15 02:45:35 PM PDT 24 |
11029465976 ps |
| T886 |
/workspace/coverage/default/23.sram_ctrl_max_throughput.1686715535 |
|
|
Apr 15 02:31:14 PM PDT 24 |
Apr 15 02:32:00 PM PDT 24 |
404571929 ps |
| T887 |
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.3511933420 |
|
|
Apr 15 02:30:02 PM PDT 24 |
Apr 15 02:32:46 PM PDT 24 |
24309439115 ps |
| T888 |
/workspace/coverage/default/3.sram_ctrl_bijection.3415521692 |
|
|
Apr 15 02:29:55 PM PDT 24 |
Apr 15 02:30:49 PM PDT 24 |
3224927933 ps |
| T889 |
/workspace/coverage/default/28.sram_ctrl_alert_test.3499138919 |
|
|
Apr 15 02:31:52 PM PDT 24 |
Apr 15 02:31:53 PM PDT 24 |
18302726 ps |
| T890 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.229886655 |
|
|
Apr 15 02:30:25 PM PDT 24 |
Apr 15 02:36:42 PM PDT 24 |
5579050047 ps |
| T891 |
/workspace/coverage/default/45.sram_ctrl_mem_walk.3760113880 |
|
|
Apr 15 02:34:30 PM PDT 24 |
Apr 15 02:34:37 PM PDT 24 |
677578579 ps |
| T892 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.1659477689 |
|
|
Apr 15 02:30:11 PM PDT 24 |
Apr 15 02:30:16 PM PDT 24 |
240719895 ps |
| T893 |
/workspace/coverage/default/27.sram_ctrl_bijection.814519223 |
|
|
Apr 15 02:31:36 PM PDT 24 |
Apr 15 02:32:26 PM PDT 24 |
2983929646 ps |
| T894 |
/workspace/coverage/default/19.sram_ctrl_alert_test.2485259799 |
|
|
Apr 15 02:30:58 PM PDT 24 |
Apr 15 02:30:59 PM PDT 24 |
12127502 ps |
| T895 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.73076917 |
|
|
Apr 15 02:34:55 PM PDT 24 |
Apr 15 02:41:19 PM PDT 24 |
60752264717 ps |
| T896 |
/workspace/coverage/default/7.sram_ctrl_regwen.1386925605 |
|
|
Apr 15 02:30:08 PM PDT 24 |
Apr 15 02:59:04 PM PDT 24 |
3102122272 ps |
| T897 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.2982256401 |
|
|
Apr 15 02:33:45 PM PDT 24 |
Apr 15 02:50:21 PM PDT 24 |
17261892390 ps |
| T898 |
/workspace/coverage/default/22.sram_ctrl_multiple_keys.521688539 |
|
|
Apr 15 02:31:07 PM PDT 24 |
Apr 15 02:31:22 PM PDT 24 |
684002533 ps |
| T899 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.2018469957 |
|
|
Apr 15 02:30:59 PM PDT 24 |
Apr 15 02:31:08 PM PDT 24 |
149462719 ps |
| T900 |
/workspace/coverage/default/32.sram_ctrl_multiple_keys.402675562 |
|
|
Apr 15 02:32:18 PM PDT 24 |
Apr 15 02:37:42 PM PDT 24 |
2597455382 ps |
| T901 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.2755138172 |
|
|
Apr 15 02:30:32 PM PDT 24 |
Apr 15 02:37:27 PM PDT 24 |
5915676204 ps |
| T902 |
/workspace/coverage/default/38.sram_ctrl_partial_access.28612272 |
|
|
Apr 15 02:33:14 PM PDT 24 |
Apr 15 02:33:31 PM PDT 24 |
309791849 ps |
| T903 |
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.1110454589 |
|
|
Apr 15 02:32:33 PM PDT 24 |
Apr 15 02:35:24 PM PDT 24 |
6790917587 ps |
| T904 |
/workspace/coverage/default/31.sram_ctrl_ram_cfg.1130427592 |
|
|
Apr 15 02:32:21 PM PDT 24 |
Apr 15 02:32:22 PM PDT 24 |
100046372 ps |
| T905 |
/workspace/coverage/default/41.sram_ctrl_stress_all.3863158758 |
|
|
Apr 15 02:33:54 PM PDT 24 |
Apr 15 02:48:19 PM PDT 24 |
95594895063 ps |
| T906 |
/workspace/coverage/default/4.sram_ctrl_bijection.2023859446 |
|
|
Apr 15 02:29:56 PM PDT 24 |
Apr 15 02:31:02 PM PDT 24 |
15241116434 ps |
| T907 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.2689141201 |
|
|
Apr 15 02:30:05 PM PDT 24 |
Apr 15 02:30:12 PM PDT 24 |
236126050 ps |
| T908 |
/workspace/coverage/default/31.sram_ctrl_regwen.1633644507 |
|
|
Apr 15 02:32:20 PM PDT 24 |
Apr 15 02:36:20 PM PDT 24 |
2635219197 ps |
| T909 |
/workspace/coverage/default/1.sram_ctrl_mem_walk.1030081696 |
|
|
Apr 15 02:29:47 PM PDT 24 |
Apr 15 02:29:57 PM PDT 24 |
545541797 ps |
| T910 |
/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.4259339657 |
|
|
Apr 15 02:31:58 PM PDT 24 |
Apr 15 02:38:26 PM PDT 24 |
22191536075 ps |
| T911 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2956657108 |
|
|
Apr 15 02:34:13 PM PDT 24 |
Apr 15 02:38:15 PM PDT 24 |
13713434516 ps |
| T912 |
/workspace/coverage/default/30.sram_ctrl_stress_all.4001654910 |
|
|
Apr 15 02:32:10 PM PDT 24 |
Apr 15 03:39:14 PM PDT 24 |
19945226879 ps |
| T913 |
/workspace/coverage/default/20.sram_ctrl_regwen.532064917 |
|
|
Apr 15 02:30:56 PM PDT 24 |
Apr 15 02:40:04 PM PDT 24 |
4323464000 ps |
| T914 |
/workspace/coverage/default/36.sram_ctrl_executable.2500052637 |
|
|
Apr 15 02:32:57 PM PDT 24 |
Apr 15 02:46:28 PM PDT 24 |
58824459469 ps |
| T915 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.2009325527 |
|
|
Apr 15 02:34:46 PM PDT 24 |
Apr 15 02:34:59 PM PDT 24 |
74272085 ps |
| T916 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.1928495403 |
|
|
Apr 15 02:34:55 PM PDT 24 |
Apr 15 02:35:58 PM PDT 24 |
526541647 ps |
| T917 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.302419505 |
|
|
Apr 15 02:30:16 PM PDT 24 |
Apr 15 02:31:35 PM PDT 24 |
2749849816 ps |
| T918 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.2995061635 |
|
|
Apr 15 02:30:00 PM PDT 24 |
Apr 15 02:30:18 PM PDT 24 |
143090916 ps |
| T919 |
/workspace/coverage/default/10.sram_ctrl_bijection.3845925092 |
|
|
Apr 15 02:30:22 PM PDT 24 |
Apr 15 02:30:45 PM PDT 24 |
741455041 ps |
| T920 |
/workspace/coverage/default/40.sram_ctrl_mem_partial_access.3506728690 |
|
|
Apr 15 02:33:48 PM PDT 24 |
Apr 15 02:33:51 PM PDT 24 |
43540272 ps |
| T921 |
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1332450141 |
|
|
Apr 15 02:30:02 PM PDT 24 |
Apr 15 02:34:30 PM PDT 24 |
198908622022 ps |
| T922 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.2549457187 |
|
|
Apr 15 02:30:54 PM PDT 24 |
Apr 15 02:33:34 PM PDT 24 |
310623489 ps |
| T923 |
/workspace/coverage/default/29.sram_ctrl_partial_access.4176590530 |
|
|
Apr 15 02:32:00 PM PDT 24 |
Apr 15 02:33:28 PM PDT 24 |
2659040308 ps |
| T924 |
/workspace/coverage/default/11.sram_ctrl_smoke.1083843701 |
|
|
Apr 15 02:30:18 PM PDT 24 |
Apr 15 02:30:20 PM PDT 24 |
125060374 ps |
| T925 |
/workspace/coverage/default/17.sram_ctrl_ram_cfg.2161251579 |
|
|
Apr 15 02:30:48 PM PDT 24 |
Apr 15 02:30:49 PM PDT 24 |
28543424 ps |
| T926 |
/workspace/coverage/default/35.sram_ctrl_access_during_key_req.2371993191 |
|
|
Apr 15 02:32:52 PM PDT 24 |
Apr 15 02:50:25 PM PDT 24 |
4319632157 ps |
| T927 |
/workspace/coverage/default/35.sram_ctrl_smoke.2867400719 |
|
|
Apr 15 02:32:49 PM PDT 24 |
Apr 15 02:33:03 PM PDT 24 |
862614495 ps |
| T928 |
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.1280209360 |
|
|
Apr 15 02:34:14 PM PDT 24 |
Apr 15 02:46:46 PM PDT 24 |
3506955253 ps |
| T929 |
/workspace/coverage/default/48.sram_ctrl_lc_escalation.145985936 |
|
|
Apr 15 02:34:59 PM PDT 24 |
Apr 15 02:35:09 PM PDT 24 |
6243801453 ps |
| T930 |
/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.937914271 |
|
|
Apr 15 02:29:55 PM PDT 24 |
Apr 15 02:29:59 PM PDT 24 |
55430983 ps |
| T931 |
/workspace/coverage/default/49.sram_ctrl_smoke.1628356512 |
|
|
Apr 15 02:35:02 PM PDT 24 |
Apr 15 02:35:18 PM PDT 24 |
9173976237 ps |
| T932 |
/workspace/coverage/default/15.sram_ctrl_executable.2954660974 |
|
|
Apr 15 02:30:36 PM PDT 24 |
Apr 15 02:35:18 PM PDT 24 |
5966517968 ps |
| T933 |
/workspace/coverage/default/47.sram_ctrl_bijection.1702223350 |
|
|
Apr 15 02:34:41 PM PDT 24 |
Apr 15 02:35:52 PM PDT 24 |
4651961472 ps |
| T934 |
/workspace/coverage/default/11.sram_ctrl_stress_all.78660618 |
|
|
Apr 15 02:30:19 PM PDT 24 |
Apr 15 03:25:42 PM PDT 24 |
50579903936 ps |
| T935 |
/workspace/coverage/default/27.sram_ctrl_mem_partial_access.1483611310 |
|
|
Apr 15 02:31:46 PM PDT 24 |
Apr 15 02:31:50 PM PDT 24 |
99946172 ps |
| T936 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.2115441138 |
|
|
Apr 15 02:30:22 PM PDT 24 |
Apr 15 02:30:38 PM PDT 24 |
69443444 ps |
| T937 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.1856049206 |
|
|
Apr 15 02:30:12 PM PDT 24 |
Apr 15 02:47:44 PM PDT 24 |
12354706388 ps |
| T938 |
/workspace/coverage/default/35.sram_ctrl_stress_all.1039565439 |
|
|
Apr 15 02:32:52 PM PDT 24 |
Apr 15 02:58:05 PM PDT 24 |
25944677113 ps |
| T939 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.3527085621 |
|
|
Apr 15 02:34:05 PM PDT 24 |
Apr 15 02:34:22 PM PDT 24 |
445765412 ps |
| T940 |
/workspace/coverage/default/47.sram_ctrl_alert_test.1582307326 |
|
|
Apr 15 02:34:49 PM PDT 24 |
Apr 15 02:34:51 PM PDT 24 |
21809694 ps |
| T941 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.630730970 |
|
|
Apr 15 02:33:36 PM PDT 24 |
Apr 15 02:34:50 PM PDT 24 |
136727722 ps |
| T942 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.1792291990 |
|
|
Apr 15 02:29:51 PM PDT 24 |
Apr 15 02:29:54 PM PDT 24 |
163468258 ps |
| T63 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2122591923 |
|
|
Apr 15 12:29:16 PM PDT 24 |
Apr 15 12:29:18 PM PDT 24 |
36164023 ps |
| T943 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3823862742 |
|
|
Apr 15 12:29:21 PM PDT 24 |
Apr 15 12:29:23 PM PDT 24 |
110995127 ps |
| T944 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.4255592935 |
|
|
Apr 15 12:29:22 PM PDT 24 |
Apr 15 12:29:23 PM PDT 24 |
39891610 ps |
| T101 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.273481402 |
|
|
Apr 15 12:29:13 PM PDT 24 |
Apr 15 12:29:15 PM PDT 24 |
16809147 ps |
| T945 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3653146631 |
|
|
Apr 15 12:29:22 PM PDT 24 |
Apr 15 12:29:23 PM PDT 24 |
103408892 ps |
| T946 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3552891688 |
|
|
Apr 15 12:29:13 PM PDT 24 |
Apr 15 12:29:14 PM PDT 24 |
47934298 ps |
| T93 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1037243596 |
|
|
Apr 15 12:29:15 PM PDT 24 |
Apr 15 12:29:16 PM PDT 24 |
58772792 ps |
| T105 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1297054649 |
|
|
Apr 15 12:29:18 PM PDT 24 |
Apr 15 12:29:21 PM PDT 24 |
229883995 ps |
| T64 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.124853927 |
|
|
Apr 15 12:29:22 PM PDT 24 |
Apr 15 12:29:26 PM PDT 24 |
1211270580 ps |
| T102 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2888157688 |
|
|
Apr 15 12:29:11 PM PDT 24 |
Apr 15 12:29:14 PM PDT 24 |
351733882 ps |
| T103 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1547531200 |
|
|
Apr 15 12:29:16 PM PDT 24 |
Apr 15 12:29:18 PM PDT 24 |
70006841 ps |
| T94 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2681876946 |
|
|
Apr 15 12:29:19 PM PDT 24 |
Apr 15 12:29:20 PM PDT 24 |
257379524 ps |
| T947 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2253152314 |
|
|
Apr 15 12:29:25 PM PDT 24 |
Apr 15 12:29:27 PM PDT 24 |
57357157 ps |
| T106 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.68520260 |
|
|
Apr 15 12:29:26 PM PDT 24 |
Apr 15 12:29:29 PM PDT 24 |
353732195 ps |
| T104 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2233657077 |
|
|
Apr 15 12:29:12 PM PDT 24 |
Apr 15 12:29:13 PM PDT 24 |
36218359 ps |
| T65 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1779509640 |
|
|
Apr 15 12:29:28 PM PDT 24 |
Apr 15 12:29:30 PM PDT 24 |
42851494 ps |
| T948 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2058561264 |
|
|
Apr 15 12:29:29 PM PDT 24 |
Apr 15 12:29:33 PM PDT 24 |
120323715 ps |
| T66 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3816143589 |
|
|
Apr 15 12:29:28 PM PDT 24 |
Apr 15 12:29:30 PM PDT 24 |
25468368 ps |
| T949 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2428387814 |
|
|
Apr 15 12:29:30 PM PDT 24 |
Apr 15 12:29:34 PM PDT 24 |
131936477 ps |
| T950 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1000244309 |
|
|
Apr 15 12:29:15 PM PDT 24 |
Apr 15 12:29:17 PM PDT 24 |
91285500 ps |
| T67 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.432916977 |
|
|
Apr 15 12:29:18 PM PDT 24 |
Apr 15 12:29:21 PM PDT 24 |
816333882 ps |
| T951 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3289960084 |
|
|
Apr 15 12:29:06 PM PDT 24 |
Apr 15 12:29:09 PM PDT 24 |
103792278 ps |
| T107 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3380264017 |
|
|
Apr 15 12:29:22 PM PDT 24 |
Apr 15 12:29:25 PM PDT 24 |
1141411828 ps |
| T952 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1917951025 |
|
|
Apr 15 12:29:23 PM PDT 24 |
Apr 15 12:29:24 PM PDT 24 |
68948818 ps |
| T95 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3389929371 |
|
|
Apr 15 12:29:26 PM PDT 24 |
Apr 15 12:29:27 PM PDT 24 |
36316147 ps |
| T126 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3438678380 |
|
|
Apr 15 12:29:27 PM PDT 24 |
Apr 15 12:29:29 PM PDT 24 |
237265587 ps |
| T953 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1804240544 |
|
|
Apr 15 12:29:11 PM PDT 24 |
Apr 15 12:29:13 PM PDT 24 |
98559747 ps |
| T68 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2993469111 |
|
|
Apr 15 12:29:18 PM PDT 24 |
Apr 15 12:29:19 PM PDT 24 |
49312467 ps |
| T954 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.862051538 |
|
|
Apr 15 12:29:22 PM PDT 24 |
Apr 15 12:29:24 PM PDT 24 |
15440940 ps |
| T69 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3083810577 |
|
|
Apr 15 12:29:27 PM PDT 24 |
Apr 15 12:29:28 PM PDT 24 |
13602294 ps |
| T955 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3044216364 |
|
|
Apr 15 12:29:21 PM PDT 24 |
Apr 15 12:29:23 PM PDT 24 |
25510124 ps |
| T127 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.296997013 |
|
|
Apr 15 12:29:15 PM PDT 24 |
Apr 15 12:29:19 PM PDT 24 |
688766001 ps |
| T70 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2833916193 |
|
|
Apr 15 12:29:15 PM PDT 24 |
Apr 15 12:29:17 PM PDT 24 |
84466854 ps |
| T71 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3621240852 |
|
|
Apr 15 12:29:22 PM PDT 24 |
Apr 15 12:29:23 PM PDT 24 |
47726315 ps |
| T72 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.521196049 |
|
|
Apr 15 12:29:30 PM PDT 24 |
Apr 15 12:29:31 PM PDT 24 |
45645994 ps |
| T956 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1784771250 |
|
|
Apr 15 12:29:32 PM PDT 24 |
Apr 15 12:29:39 PM PDT 24 |
728937098 ps |
| T957 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3249773717 |
|
|
Apr 15 12:29:34 PM PDT 24 |
Apr 15 12:29:38 PM PDT 24 |
207612269 ps |
| T73 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.568970329 |
|
|
Apr 15 12:29:12 PM PDT 24 |
Apr 15 12:29:15 PM PDT 24 |
1408243230 ps |
| T958 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.310017441 |
|
|
Apr 15 12:29:21 PM PDT 24 |
Apr 15 12:29:22 PM PDT 24 |
18312777 ps |
| T959 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3674070355 |
|
|
Apr 15 12:29:22 PM PDT 24 |
Apr 15 12:29:25 PM PDT 24 |
168932906 ps |
| T134 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2640514260 |
|
|
Apr 15 12:29:19 PM PDT 24 |
Apr 15 12:29:22 PM PDT 24 |
98462950 ps |
| T960 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.4056721470 |
|
|
Apr 15 12:29:29 PM PDT 24 |
Apr 15 12:29:30 PM PDT 24 |
31834063 ps |
| T961 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.217951938 |
|
|
Apr 15 12:29:15 PM PDT 24 |
Apr 15 12:29:17 PM PDT 24 |
32138461 ps |
| T132 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.926620032 |
|
|
Apr 15 12:29:25 PM PDT 24 |
Apr 15 12:29:28 PM PDT 24 |
597666854 ps |
| T962 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2263437051 |
|
|
Apr 15 12:29:21 PM PDT 24 |
Apr 15 12:29:26 PM PDT 24 |
494105056 ps |
| T74 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.805041892 |
|
|
Apr 15 12:29:16 PM PDT 24 |
Apr 15 12:29:17 PM PDT 24 |
20552774 ps |
| T75 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.316733627 |
|
|
Apr 15 12:29:32 PM PDT 24 |
Apr 15 12:29:37 PM PDT 24 |
3200435383 ps |
| T76 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3937390407 |
|
|
Apr 15 12:29:26 PM PDT 24 |
Apr 15 12:29:27 PM PDT 24 |
42317692 ps |
| T77 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3711792800 |
|
|
Apr 15 12:29:28 PM PDT 24 |
Apr 15 12:29:34 PM PDT 24 |
845338694 ps |
| T963 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1413573478 |
|
|
Apr 15 12:29:33 PM PDT 24 |
Apr 15 12:29:35 PM PDT 24 |
12658352 ps |
| T964 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3338245587 |
|
|
Apr 15 12:29:25 PM PDT 24 |
Apr 15 12:29:26 PM PDT 24 |
13496536 ps |
| T965 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3364282698 |
|
|
Apr 15 12:29:07 PM PDT 24 |
Apr 15 12:29:10 PM PDT 24 |
59928962 ps |
| T966 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1109104748 |
|
|
Apr 15 12:29:27 PM PDT 24 |
Apr 15 12:29:31 PM PDT 24 |
185678900 ps |
| T967 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1362343381 |
|
|
Apr 15 12:29:16 PM PDT 24 |
Apr 15 12:29:17 PM PDT 24 |
14747085 ps |
| T968 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1501279709 |
|
|
Apr 15 12:29:26 PM PDT 24 |
Apr 15 12:29:27 PM PDT 24 |
29750121 ps |
| T969 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3412920550 |
|
|
Apr 15 12:29:27 PM PDT 24 |
Apr 15 12:29:33 PM PDT 24 |
1854286546 ps |
| T970 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3387122422 |
|
|
Apr 15 12:29:15 PM PDT 24 |
Apr 15 12:29:17 PM PDT 24 |
857031557 ps |
| T78 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.75338577 |
|
|
Apr 15 12:29:07 PM PDT 24 |
Apr 15 12:29:10 PM PDT 24 |
428798127 ps |
| T130 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2285080249 |
|
|
Apr 15 12:29:13 PM PDT 24 |
Apr 15 12:29:15 PM PDT 24 |
206412394 ps |
| T971 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3862342086 |
|
|
Apr 15 12:29:28 PM PDT 24 |
Apr 15 12:29:31 PM PDT 24 |
32158028 ps |
| T972 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.756826220 |
|
|
Apr 15 12:29:25 PM PDT 24 |
Apr 15 12:29:28 PM PDT 24 |
97990897 ps |
| T84 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3013599105 |
|
|
Apr 15 12:29:11 PM PDT 24 |
Apr 15 12:29:13 PM PDT 24 |
48068236 ps |
| T973 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.749506139 |
|
|
Apr 15 12:29:09 PM PDT 24 |
Apr 15 12:29:11 PM PDT 24 |
18268479 ps |
| T974 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1658331336 |
|
|
Apr 15 12:29:11 PM PDT 24 |
Apr 15 12:29:17 PM PDT 24 |
709558773 ps |
| T975 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2225830104 |
|
|
Apr 15 12:29:20 PM PDT 24 |
Apr 15 12:29:21 PM PDT 24 |
138199714 ps |
| T128 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1651630347 |
|
|
Apr 15 12:29:18 PM PDT 24 |
Apr 15 12:29:20 PM PDT 24 |
324715411 ps |
| T85 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1425868924 |
|
|
Apr 15 12:29:14 PM PDT 24 |
Apr 15 12:29:17 PM PDT 24 |
1435993448 ps |
| T976 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1708503088 |
|
|
Apr 15 12:29:14 PM PDT 24 |
Apr 15 12:29:16 PM PDT 24 |
40690648 ps |
| T977 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.470671118 |
|
|
Apr 15 12:29:26 PM PDT 24 |
Apr 15 12:29:27 PM PDT 24 |
27521786 ps |
| T978 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3250448894 |
|
|
Apr 15 12:29:19 PM PDT 24 |
Apr 15 12:29:23 PM PDT 24 |
167220167 ps |
| T979 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.164666054 |
|
|
Apr 15 12:29:26 PM PDT 24 |
Apr 15 12:29:28 PM PDT 24 |
26041544 ps |
| T980 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3318063718 |
|
|
Apr 15 12:29:13 PM PDT 24 |
Apr 15 12:29:14 PM PDT 24 |
47022666 ps |
| T981 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1139907073 |
|
|
Apr 15 12:29:32 PM PDT 24 |
Apr 15 12:29:34 PM PDT 24 |
62139628 ps |
| T982 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.447798741 |
|
|
Apr 15 12:29:21 PM PDT 24 |
Apr 15 12:29:22 PM PDT 24 |
31026471 ps |
| T983 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3846432623 |
|
|
Apr 15 12:29:07 PM PDT 24 |
Apr 15 12:29:08 PM PDT 24 |
40946970 ps |
| T984 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1795268888 |
|
|
Apr 15 12:29:22 PM PDT 24 |
Apr 15 12:29:27 PM PDT 24 |
592664607 ps |
| T985 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1708106074 |
|
|
Apr 15 12:29:25 PM PDT 24 |
Apr 15 12:29:27 PM PDT 24 |
211170161 ps |
| T986 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1784298357 |
|
|
Apr 15 12:29:11 PM PDT 24 |
Apr 15 12:29:14 PM PDT 24 |
1431038394 ps |
| T129 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.940763117 |
|
|
Apr 15 12:29:32 PM PDT 24 |
Apr 15 12:29:35 PM PDT 24 |
464848168 ps |
| T987 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.648145634 |
|
|
Apr 15 12:29:30 PM PDT 24 |
Apr 15 12:29:32 PM PDT 24 |
248343446 ps |
| T131 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.4037896559 |
|
|
Apr 15 12:29:23 PM PDT 24 |
Apr 15 12:29:26 PM PDT 24 |
454727910 ps |
| T988 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1275775520 |
|
|
Apr 15 12:29:25 PM PDT 24 |
Apr 15 12:29:28 PM PDT 24 |
322276650 ps |
| T86 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3169683858 |
|
|
Apr 15 12:29:28 PM PDT 24 |
Apr 15 12:29:32 PM PDT 24 |
1234981902 ps |
| T989 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2161565911 |
|
|
Apr 15 12:29:28 PM PDT 24 |
Apr 15 12:29:30 PM PDT 24 |
499334518 ps |
| T990 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.4147339018 |
|
|
Apr 15 12:29:12 PM PDT 24 |
Apr 15 12:29:13 PM PDT 24 |
23348925 ps |
| T137 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.208378443 |
|
|
Apr 15 12:29:17 PM PDT 24 |
Apr 15 12:29:19 PM PDT 24 |
125149747 ps |
| T991 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1156441891 |
|
|
Apr 15 12:29:17 PM PDT 24 |
Apr 15 12:29:18 PM PDT 24 |
24987140 ps |
| T992 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.211746591 |
|
|
Apr 15 12:29:13 PM PDT 24 |
Apr 15 12:29:17 PM PDT 24 |
134879148 ps |
| T87 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.287676127 |
|
|
Apr 15 12:29:26 PM PDT 24 |
Apr 15 12:29:30 PM PDT 24 |
785897401 ps |
| T993 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3708402995 |
|
|
Apr 15 12:29:26 PM PDT 24 |
Apr 15 12:29:27 PM PDT 24 |
55576738 ps |
| T994 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2936775548 |
|
|
Apr 15 12:29:22 PM PDT 24 |
Apr 15 12:29:27 PM PDT 24 |
45889406 ps |
| T995 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.4146198921 |
|
|
Apr 15 12:29:11 PM PDT 24 |
Apr 15 12:29:13 PM PDT 24 |
28479636 ps |
| T996 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1393628385 |
|
|
Apr 15 12:29:32 PM PDT 24 |
Apr 15 12:29:33 PM PDT 24 |
15680913 ps |
| T997 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1425039672 |
|
|
Apr 15 12:29:18 PM PDT 24 |
Apr 15 12:29:19 PM PDT 24 |
24180230 ps |
| T88 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2387546466 |
|
|
Apr 15 12:29:14 PM PDT 24 |
Apr 15 12:29:18 PM PDT 24 |
515585771 ps |
| T998 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.149070930 |
|
|
Apr 15 12:29:05 PM PDT 24 |
Apr 15 12:29:07 PM PDT 24 |
22556091 ps |
| T999 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1361115788 |
|
|
Apr 15 12:29:23 PM PDT 24 |
Apr 15 12:29:25 PM PDT 24 |
577162734 ps |
| T1000 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.4040933499 |
|
|
Apr 15 12:29:12 PM PDT 24 |
Apr 15 12:29:13 PM PDT 24 |
43214480 ps |
| T1001 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1517857330 |
|
|
Apr 15 12:29:27 PM PDT 24 |
Apr 15 12:29:29 PM PDT 24 |
1086713745 ps |
| T1002 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3790613330 |
|
|
Apr 15 12:29:18 PM PDT 24 |
Apr 15 12:29:20 PM PDT 24 |
31717617 ps |
| T1003 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2448794801 |
|
|
Apr 15 12:29:28 PM PDT 24 |
Apr 15 12:29:30 PM PDT 24 |
16674824 ps |
| T1004 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.4165745037 |
|
|
Apr 15 12:29:24 PM PDT 24 |
Apr 15 12:29:25 PM PDT 24 |
43716207 ps |
| T1005 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.339006815 |
|
|
Apr 15 12:29:34 PM PDT 24 |
Apr 15 12:29:37 PM PDT 24 |
117274098 ps |