Unified Coverage Report :: Module :: sram_ctrl

Module : sram_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.99	100.00	92.63	100.00		100.00	92.31

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	97.39	100.00	94.62	100.00		100.00	92.31

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.39	100.00	94.62	100.00		100.00	92.31

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.18	99.81	96.99	100.00	100.00	98.57	99.70

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
sram_ctrl_regs_csr_assert	100.00						100.00
tlul_assert_device_ram	100.00	100.00				100.00	100.00
tlul_assert_device_regs	100.00	100.00				100.00	100.00
u_lfsr	100.00			100.00
u_prim_alert_sender_parity	100.00			100.00
u_prim_count	100.00			100.00
u_prim_lc_sync	100.00	100.00				100.00	100.00
u_prim_ram_1p_scr	98.40	100.00	92.00	100.00		100.00	100.00
u_prim_sync_reqack_data	100.00	100.00	100.00			100.00	100.00
u_reg_regs	99.92	100.00	99.58	100.00		100.00	100.00
u_tlul_adapter_sram	98.81	99.46	96.34	100.00	100.00	97.04	100.00
u_tlul_data_integ_enc	100.00	100.00
u_tlul_lc_gate	96.79	100.00	100.00		100.00	96.43	87.50

Line Coverage for Module : sram_ctrl

	Line No.	Total	Covered	Percent
TOTAL		49	49	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
ALWAYS	218	3	3	100.00
CONT_ASSIGN	230	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	255	1	1	100.00
CONT_ASSIGN	256	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	276	1	1	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
ALWAYS	290	11	11	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	490	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	492	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	506	1	1	100.00
CONT_ASSIGN	541	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv' or '../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
126	1	1
134	1	1
137	1	1
141	1	1
144	1	1
176	1	1
178	1	1
186	1	1
192	1	1
200	1	1
209	1	1
214	1	1
218	1	1
219	1	1
221	1	1
230	1	1
231	1	1
255	1	1
256	1	1
267	1	1
272	1	1
276	1	1
277	1	1
281	1	1
282	1	1
286	1	1
287	1	1
290	1	1
291	1	1
294	1	1
295	1	1
297	1	1
298	1	1
299	1	1
300	1	1
			MISSING_ELSE
305	1	1
306	1	1
307	1	1
			MISSING_ELSE
334	1	1
377	1	1
484	1	1
490	1	1
491	1	1
492	1	1
493	1	1
494	1	1
495	1	1
506	1	1
541	1	1

---

Cond Coverage for Module : sram_ctrl

	Total	Covered	Percent
Conditions	95	88	92.63
Logical	95	88	92.63
Non-Logical	0	0
Event	0	0

 LINE       134
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T10,T21,T22
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T21,T22

 LINE       144
 EXPRESSION (((|bus_integ_error)) | init_error)
             ----------1---------   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T18,T19,T20
1	0	Covered	T18,T19,T20

 LINE       186
 EXPRESSION (reg2hw.status.escalated.q | reg2hw.status.init_error.q | reg2hw.status.bus_integ_error.q)
             ------------1------------   -------------2------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T18,T19,T20
0	1	0	Covered	T18,T19,T20
1	0	0	Covered	T7,T8,T9

 LINE       192
 EXPRESSION (escalate | init_error | ((|bus_integ_error)) | local_esc_reg)
             ----1---   -----2----   ----------3---------   ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T7,T8,T9
0	0	1	0	Covered	T18,T19,T20
0	1	0	0	Covered	T18,T19,T20
1	0	0	0	Covered	T7,T8,T9

 LINE       209
 EXPRESSION (reg2hw.ctrl.init.q && reg2hw.ctrl.init.qe && ((!init_q)))
             ---------1--------    ---------2---------    -----3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T13,T16,T17
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       214
 EXPRESSION (init_done ? 1'b0 : (init_trig ? 1'b1 : init_q))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       214
 SUB-EXPRESSION (init_trig ? 1'b1 : init_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       230
 EXPRESSION (init_q & ((~key_req_pending_q)))
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       231
 EXPRESSION ((init_cnt == 10'((Depth - 1))) & init_req)
             ---------------1--------------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       231
 SUB-EXPRESSION (init_cnt == 10'((Depth - 1)))
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       255
 EXPRESSION (init_done & ((~init_trig)) & ((~local_esc)))
             ----1----   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T7,T8,T9
1	1	1	Covered	T1,T2,T3

 LINE       256
 EXPRESSION (init_done | init_trig | local_esc)
             ----1----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T7,T8,T9
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       267
 EXPRESSION (reg2hw.ctrl.renew_scr_key.q && reg2hw.ctrl.renew_scr_key.qe && ((!key_req_pending_q)) && ((!init_q)))
             -------------1-------------    --------------2-------------    -----------3----------    -----4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T17,T23,T24
1	0	1	1	Covered	T1,T2,T3
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T2,T3

 LINE       272
 EXPRESSION (key_req ? 1'b1 : (key_ack ? 1'b0 : key_req_pending_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       272
 SUB-EXPRESSION (key_ack ? 1'b0 : key_req_pending_q)
                 ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       276
 EXPRESSION (key_ack & ((~key_req)) & ((~local_esc)))
             ---1---   ------2-----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T7,T8,T9
1	1	1	Covered	T1,T2,T3

 LINE       277
 EXPRESSION (key_req | key_ack | local_esc)
             ---1---   ---2---   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T7,T8,T9
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       281
 EXPRESSION ((key_ack & ((~local_esc))) ? MuBi4True : MuBi4False)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       281
 SUB-EXPRESSION (key_ack & ((~local_esc)))
                 ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T1,T2,T3

 LINE       282
 EXPRESSION (key_ack | local_esc)
             ---1---   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3

 LINE       286
 EXPRESSION (key_seed_valid & ((~local_esc)))
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T7,T8,T9
1	1	Covered	T1,T2,T5

 LINE       287
 EXPRESSION (key_ack | local_esc)
             ---1---   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3

 LINE       484
 EXPRESSION (tlul_req | init_req)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       490
 EXPRESSION (key_valid & ((~init_req)))
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       491
 EXPRESSION (tlul_we | init_req)
             ---1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       492
 EXPRESSION (((|bus_integ_error[2:1])) & ((~init_req)))
             ------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T18,T19,T20

 LINE       493
 EXPRESSION (init_req ? init_cnt : tlul_addr)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       494
 EXPRESSION (init_req ? lfsr_out_integ : tlul_wdata)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       495
 EXPRESSION (init_req ? ({sram_ctrl_pkg::DataWidth {1'b1}}) : tlul_wmask)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       506
 EXPRESSION (key_req_pending_q ? 1'b0 : (reg2hw.status.escalated.q ? (tl_gate_resp_pending & sram_rmw_in_progress) : 1'b1))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       506
 SUB-EXPRESSION (reg2hw.status.escalated.q ? (tl_gate_resp_pending & sram_rmw_in_progress) : 1'b1)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T9

 LINE       506
 SUB-EXPRESSION (tl_gate_resp_pending & sram_rmw_in_progress)
                 ----------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T8,T9
1	1	Covered	T9,T25,T26

---

Toggle Coverage for Module : sram_ctrl

	Total	Covered	Percent
Totals	60	60	100.00
Total Bits	1226	1226	100.00
Total Bits 0->1	613	613	100.00
Total Bits 1->0	613	613	100.00

Ports	60	60	100.00
Port Bits	1226	1226	100.00
Port Bits 0->1	613	613	100.00
Port Bits 1->0	613	613	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T14,T7,T8	Yes	T1,T2,T3	INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T14,T7,T8	Yes	T1,T2,T3	INPUT
ram_tl_i.d_ready	Yes	Yes	T4,T12,T16	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_error	Yes	Yes	T1,T2,T3	Yes	T17,T14,T7	OUTPUT
ram_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T4,T12,T16	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T10,T6,T12	Yes	T10,T6,T12	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T5,T10,T6	Yes	T1,T5,T10	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T6,T12,T27	Yes	T6,T12,T27	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T10,T6,T12	Yes	T10,T6,T12	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T6,T12,T17	Yes	T6,T12,T17	INPUT
regs_tl_i.a_address[31:0]	Yes	Yes	T6,T12,T17	Yes	T6,T12,T17	INPUT
regs_tl_i.a_source[7:0]	Yes	Yes	T5,T10,T6	Yes	T5,T10,T6	INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T5,T10,T6	Yes	T2,T5,T10	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T2,T5,T10	Yes	T1,T5,T10	INPUT
regs_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_error	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	OUTPUT
regs_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T5,*T10,*T6	Yes	T2,T3,T5	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T17,T14,T7	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_source[7:0]	Yes	Yes	T5,T10,T6	Yes	T2,T5,T10	OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T5,T10,T6	Yes	T2,T5,T10	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T17,*T14,*T7	Yes	T17,T14,T7	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T10,T21,T22	Yes	T10,T21,T22	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T10,T21,T22	Yes	T10,T21,T22	OUTPUT
lc_escalate_en_i[3:0]	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T17,T14,T8	Yes	T17,T14,T8	INPUT
otp_en_sram_ifetch_i[7:0]	Yes	Yes	T17,T14,T8	Yes	T17,T14,T8	INPUT
sram_otp_key_o.req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sram_otp_key_i.seed_valid	Yes	Yes	T5,T6,T13	Yes	T5,T6,T13	INPUT
sram_otp_key_i.nonce[127:0]	Yes	Yes	T1,T5,T6	Yes	T2,T5,T6	INPUT
sram_otp_key_i.key[127:0]	Yes	Yes	T5,T6,T13	Yes	T5,T6,T13	INPUT
sram_otp_key_i.ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_i.rf_cfg.cfg[3:0]	Yes	Yes	T11,T27,T31	Yes	T11,T27,T31	INPUT
cfg_i.rf_cfg.cfg_en	Yes	Yes	T11,T27,T31	Yes	T11,T27,T31	INPUT
cfg_i.ram_cfg.cfg[3:0]	Yes	Yes	T11,T27,T31	Yes	T11,T27,T31	INPUT
cfg_i.ram_cfg.cfg_en	Yes	Yes	T11,T27,T31	Yes	T11,T27,T31	INPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : sram_ctrl

	Line No.	Total	Covered	Percent
Branches		24	24	100.00
TERNARY	214	3	3	100.00
TERNARY	272	3	3	100.00
TERNARY	281	2	2	100.00
TERNARY	493	2	2	100.00
TERNARY	494	2	2	100.00
TERNARY	495	2	2	100.00
TERNARY	506	3	3	100.00
IF	218	2	2	100.00
IF	290	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv' or '../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	214	(init_done) ? 
-2-:	214	(init_trig) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	272	(key_req) ? 
-2-:	272	(key_ack) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	281	((key_ack & (~local_esc))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	493	(init_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	494	(init_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	495	(init_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	506	(key_req_pending_q) ? 
-2-:	506	(reg2hw.status.escalated.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	218	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	290	if ((!rst_ni))
-2-:	298	if (key_ack)
-3-:	305	if (local_esc)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	-	Covered	T1,T2,T3
0	-	1	Covered	T7,T8,T9
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : sram_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	12	92.31
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	12	92.31

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertOutKnown_A	323852342	323728728	0	0
FpvSecCmCntCheck_A	323852342	70	0	0
FpvSecCmFifoRptrCheck_A	323852342	70	0	0
FpvSecCmFifoWptrCheck_A	323852342	70	0	0
FpvSecCmLcGateFsmCheck_A	323852342	0	0	0
FpvSecCmRegWeOnehotCheck_A	323852342	70	0	0
NonceWidthsLessThanSource_A	894	894	0	0
RamTlOutKnown_A	323852342	323728728	0	0
RamTlOutPayLoadKnown_A	323852342	142023482	0	0
RamTlOutPayLoadKnown_AKnownEnable	323852342	323728728	0	0
RegsTlOutKnown_A	323852342	323728728	0	0
SramOtpKeyKnown_A	323852342	323728728	0	0
TlulGntIsCorrect_A	323852342	63703156	0	0

AlertOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323852342	323728728	0	0
T1	14287	14236	0	0
T2	4096	4042	0	0
T3	3643	3569	0	0
T4	29169	29119	0	0
T5	438667	438577	0	0
T6	263748	263696	0	0
T10	1208	1138	0	0
T11	2795	2732	0	0
T12	751236	751181	0	0
T13	51409	51348	0	0

FpvSecCmCntCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323852342	70	0	0
T18	21566	20	0	0
T19	0	10	0	0
T20	0	20	0	0
T32	0	10	0	0
T33	0	10	0	0
T34	3979	0	0	0
T35	67794	0	0	0
T36	12879	0	0	0
T37	1064	0	0	0
T38	897283	0	0	0
T39	10581	0	0	0
T40	283631	0	0	0
T41	291218	0	0	0
T42	113762	0	0	0

FpvSecCmFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323852342	70	0	0
T18	21566	20	0	0
T19	0	10	0	0
T20	0	20	0	0
T32	0	10	0	0
T33	0	10	0	0
T34	3979	0	0	0
T35	67794	0	0	0
T36	12879	0	0	0
T37	1064	0	0	0
T38	897283	0	0	0
T39	10581	0	0	0
T40	283631	0	0	0
T41	291218	0	0	0
T42	113762	0	0	0

FpvSecCmFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323852342	70	0	0
T18	21566	20	0	0
T19	0	10	0	0
T20	0	20	0	0
T32	0	10	0	0
T33	0	10	0	0
T34	3979	0	0	0
T35	67794	0	0	0
T36	12879	0	0	0
T37	1064	0	0	0
T38	897283	0	0	0
T39	10581	0	0	0
T40	283631	0	0	0
T41	291218	0	0	0
T42	113762	0	0	0

FpvSecCmLcGateFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323852342	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323852342	70	0	0
T18	21566	20	0	0
T19	0	10	0	0
T20	0	20	0	0
T32	0	10	0	0
T33	0	10	0	0
T34	3979	0	0	0
T35	67794	0	0	0
T36	12879	0	0	0
T37	1064	0	0	0
T38	897283	0	0	0
T39	10581	0	0	0
T40	283631	0	0	0
T41	291218	0	0	0
T42	113762	0	0	0

NonceWidthsLessThanSource_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	894	894	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

RamTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323852342	323728728	0	0
T1	14287	14236	0	0
T2	4096	4042	0	0
T3	3643	3569	0	0
T4	29169	29119	0	0
T5	438667	438577	0	0
T6	263748	263696	0	0
T10	1208	1138	0	0
T11	2795	2732	0	0
T12	751236	751181	0	0
T13	51409	51348	0	0

RamTlOutPayLoadKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323852342	142023482	0	0
T1	14287	9050	0	0
T2	4096	279	0	0
T3	3643	464	0	0
T4	29169	9584	0	0
T5	438667	239066	0	0
T6	263748	152601	0	0
T10	1208	0	0	0
T11	2795	0	0	0
T12	751236	230595	0	0
T13	51409	24576	0	0
T16	0	49152	0	0
T17	0	111381	0	0

RamTlOutPayLoadKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	323852342	323728728	0	0
T1	14287	14236	0	0
T2	4096	4042	0	0
T3	3643	3569	0	0
T4	29169	29119	0	0
T5	438667	438577	0	0
T6	263748	263696	0	0
T10	1208	1138	0	0
T11	2795	2732	0	0
T12	751236	751181	0	0
T13	51409	51348	0	0

RegsTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323852342	323728728	0	0
T1	14287	14236	0	0
T2	4096	4042	0	0
T3	3643	3569	0	0
T4	29169	29119	0	0
T5	438667	438577	0	0
T6	263748	263696	0	0
T10	1208	1138	0	0
T11	2795	2732	0	0
T12	751236	751181	0	0
T13	51409	51348	0	0

SramOtpKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323852342	323728728	0	0
T1	14287	14236	0	0
T2	4096	4042	0	0
T3	3643	3569	0	0
T4	29169	29119	0	0
T5	438667	438577	0	0
T6	263748	263696	0	0
T10	1208	1138	0	0
T11	2795	2732	0	0
T12	751236	751181	0	0
T13	51409	51348	0	0

TlulGntIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323852342	63703156	0	0
T1	14287	9856	0	0
T2	4096	286	0	0
T3	3643	497	0	0
T4	29169	3071	0	0
T5	438667	285826	0	0
T6	263748	180056	0	0
T10	1208	0	0	0
T11	2795	0	0	0
T12	751236	164671	0	0
T13	51409	24576	0	0
T16	0	49152	0	0
T17	0	46966	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		49	49	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
ALWAYS	218	3	3	100.00
CONT_ASSIGN	230	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	255	1	1	100.00
CONT_ASSIGN	256	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	276	1	1	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
ALWAYS	290	11	11	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	490	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	492	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	506	1	1	100.00
CONT_ASSIGN	541	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv' or '../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
126	1	1
134	1	1
137	1	1
141	1	1
144	1	1
176	1	1
178	1	1
186	1	1
192	1	1
200	1	1
209	1	1
214	1	1
218	1	1
219	1	1
221	1	1
230	1	1
231	1	1
255	1	1
256	1	1
267	1	1
272	1	1
276	1	1
277	1	1
281	1	1
282	1	1
286	1	1
287	1	1
290	1	1
291	1	1
294	1	1
295	1	1
297	1	1
298	1	1
299	1	1
300	1	1
			MISSING_ELSE
305	1	1
306	1	1
307	1	1
			MISSING_ELSE
334	1	1
377	1	1
484	1	1
490	1	1
491	1	1
492	1	1
493	1	1
494	1	1
495	1	1
506	1	1
541	1	1

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	93	88	94.62
Logical	93	88	94.62
Non-Logical	0	0
Event	0	0

 LINE       134
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T10,T21,T22
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T21,T22

 LINE       144
 EXPRESSION (((|bus_integ_error)) | init_error)
             ----------1---------   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T18,T19,T20
1	0	Covered	T18,T19,T20

 LINE       186
 EXPRESSION (reg2hw.status.escalated.q | reg2hw.status.init_error.q | reg2hw.status.bus_integ_error.q)
             ------------1------------   -------------2------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T18,T19,T20
0	1	0	Covered	T18,T19,T20
1	0	0	Covered	T7,T8,T9

 LINE       192
 EXPRESSION (escalate | init_error | ((|bus_integ_error)) | local_esc_reg)
             ----1---   -----2----   ----------3---------   ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T7,T8,T9
0	0	1	0	Covered	T18,T19,T20
0	1	0	0	Covered	T18,T19,T20
1	0	0	0	Covered	T7,T8,T9

 LINE       209
 EXPRESSION (reg2hw.ctrl.init.q && reg2hw.ctrl.init.qe && ((!init_q)))
             ---------1--------    ---------2---------    -----3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T13,T16,T17
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       214
 EXPRESSION (init_done ? 1'b0 : (init_trig ? 1'b1 : init_q))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       214
 SUB-EXPRESSION (init_trig ? 1'b1 : init_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       230
 EXPRESSION (init_q & ((~key_req_pending_q)))
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       231
 EXPRESSION ((init_cnt == 10'((Depth - 1))) & init_req)
             ---------------1--------------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       231
 SUB-EXPRESSION (init_cnt == 10'((Depth - 1)))
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       255
 EXPRESSION (init_done & ((~init_trig)) & ((~local_esc)))
             ----1----   -------2------   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		[LOWRISK] we don't issue a new init when there is a unfinished init
1	1	0	Covered	T7,T8,T9
1	1	1	Covered	T1,T2,T3

 LINE       256
 EXPRESSION (init_done | init_trig | local_esc)
             ----1----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T7,T8,T9
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       267
 EXPRESSION (reg2hw.ctrl.renew_scr_key.q && reg2hw.ctrl.renew_scr_key.qe && ((!key_req_pending_q)) && ((!init_q)))
             -------------1-------------    --------------2-------------    -----------3----------    -----4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T17,T23,T24
1	0	1	1	Covered	T1,T2,T3
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T2,T3

 LINE       272
 EXPRESSION (key_req ? 1'b1 : (key_ack ? 1'b0 : key_req_pending_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       272
 SUB-EXPRESSION (key_ack ? 1'b0 : key_req_pending_q)
                 ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       276
 EXPRESSION (key_ack & ((~key_req)) & ((~local_esc)))
             ---1---   ------2-----   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		[UNSUPPORTED] ACK can't come without REQ
1	1	0	Covered	T7,T8,T9
1	1	1	Covered	T1,T2,T3

 LINE       277
 EXPRESSION (key_req | key_ack | local_esc)
             ---1---   ---2---   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T7,T8,T9
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       281
 EXPRESSION ((key_ack & ((~local_esc))) ? MuBi4True : MuBi4False)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       281
 SUB-EXPRESSION (key_ack & ((~local_esc)))
                 ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T1,T2,T3

 LINE       282
 EXPRESSION (key_ack | local_esc)
             ---1---   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3

 LINE       286
 EXPRESSION (key_seed_valid & ((~local_esc)))
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T7,T8,T9
1	1	Covered	T1,T2,T5

 LINE       287
 EXPRESSION (key_ack | local_esc)
             ---1---   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3

 LINE       484
 EXPRESSION (tlul_req | init_req)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       490
 EXPRESSION (key_valid & ((~init_req)))
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       491
 EXPRESSION (tlul_we | init_req)
             ---1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       492
 EXPRESSION (((|bus_integ_error[2:1])) & ((~init_req)))
             ------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T18,T19,T20

 LINE       493
 EXPRESSION (init_req ? init_cnt : tlul_addr)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       494
 EXPRESSION (init_req ? lfsr_out_integ : tlul_wdata)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       495
 EXPRESSION (init_req ? ({sram_ctrl_pkg::DataWidth {1'b1}}) : tlul_wmask)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       506
 EXPRESSION (key_req_pending_q ? 1'b0 : (reg2hw.status.escalated.q ? (tl_gate_resp_pending & sram_rmw_in_progress) : 1'b1))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       506
 SUB-EXPRESSION (reg2hw.status.escalated.q ? (tl_gate_resp_pending & sram_rmw_in_progress) : 1'b1)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T9

 LINE       506
 SUB-EXPRESSION (tl_gate_resp_pending & sram_rmw_in_progress)
                 ----------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T8,T9
1	1	Covered	T9,T25,T26

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	60	60	100.00
Total Bits	1226	1226	100.00
Total Bits 0->1	613	613	100.00
Total Bits 1->0	613	613	100.00

Ports	60	60	100.00
Port Bits	1226	1226	100.00
Port Bits 0->1	613	613	100.00
Port Bits 1->0	613	613	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T14,T7,T8	Yes	T1,T2,T3	INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T14,T7,T8	Yes	T1,T2,T3	INPUT
ram_tl_i.d_ready	Yes	Yes	T4,T12,T16	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_error	Yes	Yes	T1,T2,T3	Yes	T17,T14,T7	OUTPUT
ram_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T4,T12,T16	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T10,T6,T12	Yes	T10,T6,T12	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T5,T10,T6	Yes	T1,T5,T10	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T6,T12,T27	Yes	T6,T12,T27	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T10,T6,T12	Yes	T10,T6,T12	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T6,T12,T17	Yes	T6,T12,T17	INPUT
regs_tl_i.a_address[31:0]	Yes	Yes	T6,T12,T17	Yes	T6,T12,T17	INPUT
regs_tl_i.a_source[7:0]	Yes	Yes	T5,T10,T6	Yes	T5,T10,T6	INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T5,T10,T6	Yes	T2,T5,T10	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T2,T5,T10	Yes	T1,T5,T10	INPUT
regs_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_error	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	OUTPUT
regs_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T5,*T10,*T6	Yes	T2,T3,T5	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T17,T14,T7	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_source[7:0]	Yes	Yes	T5,T10,T6	Yes	T2,T5,T10	OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T5,T10,T6	Yes	T2,T5,T10	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T17,*T14,*T7	Yes	T17,T14,T7	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T10,T21,T22	Yes	T10,T21,T22	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T10,T21,T22	Yes	T10,T21,T22	OUTPUT
lc_escalate_en_i[3:0]	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T17,T14,T8	Yes	T17,T14,T8	INPUT
otp_en_sram_ifetch_i[7:0]	Yes	Yes	T17,T14,T8	Yes	T17,T14,T8	INPUT
sram_otp_key_o.req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
sram_otp_key_i.seed_valid	Yes	Yes	T5,T6,T13	Yes	T5,T6,T13	INPUT
sram_otp_key_i.nonce[127:0]	Yes	Yes	T1,T5,T6	Yes	T2,T5,T6	INPUT
sram_otp_key_i.key[127:0]	Yes	Yes	T5,T6,T13	Yes	T5,T6,T13	INPUT
sram_otp_key_i.ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_i.rf_cfg.cfg[3:0]	Yes	Yes	T11,T27,T31	Yes	T11,T27,T31	INPUT
cfg_i.rf_cfg.cfg_en	Yes	Yes	T11,T27,T31	Yes	T11,T27,T31	INPUT
cfg_i.ram_cfg.cfg[3:0]	Yes	Yes	T11,T27,T31	Yes	T11,T27,T31	INPUT
cfg_i.ram_cfg.cfg_en	Yes	Yes	T11,T27,T31	Yes	T11,T27,T31	INPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		24	24	100.00
TERNARY	214	3	3	100.00
TERNARY	272	3	3	100.00
TERNARY	281	2	2	100.00
TERNARY	493	2	2	100.00
TERNARY	494	2	2	100.00
TERNARY	495	2	2	100.00
TERNARY	506	3	3	100.00
IF	218	2	2	100.00
IF	290	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv' or '../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	214	(init_done) ? 
-2-:	214	(init_trig) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	272	(key_req) ? 
-2-:	272	(key_ack) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	281	((key_ack & (~local_esc))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	493	(init_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	494	(init_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	495	(init_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	506	(key_req_pending_q) ? 
-2-:	506	(reg2hw.status.escalated.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	218	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	290	if ((!rst_ni))
-2-:	298	if (key_ack)
-3-:	305	if (local_esc)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	-	Covered	T1,T2,T3
0	-	1	Covered	T7,T8,T9
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	12	92.31
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	12	92.31

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertOutKnown_A	323852342	323728728	0	0
FpvSecCmCntCheck_A	323852342	70	0	0
FpvSecCmFifoRptrCheck_A	323852342	70	0	0
FpvSecCmFifoWptrCheck_A	323852342	70	0	0
FpvSecCmLcGateFsmCheck_A	323852342	0	0	0
FpvSecCmRegWeOnehotCheck_A	323852342	70	0	0
NonceWidthsLessThanSource_A	894	894	0	0
RamTlOutKnown_A	323852342	323728728	0	0
RamTlOutPayLoadKnown_A	323852342	142023482	0	0
RamTlOutPayLoadKnown_AKnownEnable	323852342	323728728	0	0
RegsTlOutKnown_A	323852342	323728728	0	0
SramOtpKeyKnown_A	323852342	323728728	0	0
TlulGntIsCorrect_A	323852342	63703156	0	0

AlertOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323852342	323728728	0	0
T1	14287	14236	0	0
T2	4096	4042	0	0
T3	3643	3569	0	0
T4	29169	29119	0	0
T5	438667	438577	0	0
T6	263748	263696	0	0
T10	1208	1138	0	0
T11	2795	2732	0	0
T12	751236	751181	0	0
T13	51409	51348	0	0

FpvSecCmCntCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323852342	70	0	0
T18	21566	20	0	0
T19	0	10	0	0
T20	0	20	0	0
T32	0	10	0	0
T33	0	10	0	0
T34	3979	0	0	0
T35	67794	0	0	0
T36	12879	0	0	0
T37	1064	0	0	0
T38	897283	0	0	0
T39	10581	0	0	0
T40	283631	0	0	0
T41	291218	0	0	0
T42	113762	0	0	0

FpvSecCmFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323852342	70	0	0
T18	21566	20	0	0
T19	0	10	0	0
T20	0	20	0	0
T32	0	10	0	0
T33	0	10	0	0
T34	3979	0	0	0
T35	67794	0	0	0
T36	12879	0	0	0
T37	1064	0	0	0
T38	897283	0	0	0
T39	10581	0	0	0
T40	283631	0	0	0
T41	291218	0	0	0
T42	113762	0	0	0

FpvSecCmFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323852342	70	0	0
T18	21566	20	0	0
T19	0	10	0	0
T20	0	20	0	0
T32	0	10	0	0
T33	0	10	0	0
T34	3979	0	0	0
T35	67794	0	0	0
T36	12879	0	0	0
T37	1064	0	0	0
T38	897283	0	0	0
T39	10581	0	0	0
T40	283631	0	0	0
T41	291218	0	0	0
T42	113762	0	0	0

FpvSecCmLcGateFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323852342	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323852342	70	0	0
T18	21566	20	0	0
T19	0	10	0	0
T20	0	20	0	0
T32	0	10	0	0
T33	0	10	0	0
T34	3979	0	0	0
T35	67794	0	0	0
T36	12879	0	0	0
T37	1064	0	0	0
T38	897283	0	0	0
T39	10581	0	0	0
T40	283631	0	0	0
T41	291218	0	0	0
T42	113762	0	0	0

NonceWidthsLessThanSource_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	894	894	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

RamTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323852342	323728728	0	0
T1	14287	14236	0	0
T2	4096	4042	0	0
T3	3643	3569	0	0
T4	29169	29119	0	0
T5	438667	438577	0	0
T6	263748	263696	0	0
T10	1208	1138	0	0
T11	2795	2732	0	0
T12	751236	751181	0	0
T13	51409	51348	0	0

RamTlOutPayLoadKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323852342	142023482	0	0
T1	14287	9050	0	0
T2	4096	279	0	0
T3	3643	464	0	0
T4	29169	9584	0	0
T5	438667	239066	0	0
T6	263748	152601	0	0
T10	1208	0	0	0
T11	2795	0	0	0
T12	751236	230595	0	0
T13	51409	24576	0	0
T16	0	49152	0	0
T17	0	111381	0	0

RamTlOutPayLoadKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	323852342	323728728	0	0
T1	14287	14236	0	0
T2	4096	4042	0	0
T3	3643	3569	0	0
T4	29169	29119	0	0
T5	438667	438577	0	0
T6	263748	263696	0	0
T10	1208	1138	0	0
T11	2795	2732	0	0
T12	751236	751181	0	0
T13	51409	51348	0	0

RegsTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323852342	323728728	0	0
T1	14287	14236	0	0
T2	4096	4042	0	0
T3	3643	3569	0	0
T4	29169	29119	0	0
T5	438667	438577	0	0
T6	263748	263696	0	0
T10	1208	1138	0	0
T11	2795	2732	0	0
T12	751236	751181	0	0
T13	51409	51348	0	0

SramOtpKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323852342	323728728	0	0
T1	14287	14236	0	0
T2	4096	4042	0	0
T3	3643	3569	0	0
T4	29169	29119	0	0
T5	438667	438577	0	0
T6	263748	263696	0	0
T10	1208	1138	0	0
T11	2795	2732	0	0
T12	751236	751181	0	0
T13	51409	51348	0	0

TlulGntIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323852342	63703156	0	0
T1	14287	9856	0	0
T2	4096	286	0	0
T3	3643	497	0	0
T4	29169	3071	0	0
T5	438667	285826	0	0
T6	263748	180056	0	0
T10	1208	0	0	0
T11	2795	0	0	0
T12	751236	164671	0	0
T13	51409	24576	0	0
T16	0	49152	0	0
T17	0	46966	0	0