Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.39	100.00	94.62	100.00		100.00	92.31	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	325153743	123245	0	0
ctrl_regwen_rd_A	325153743	9026	0	0
exec_rd_A	325153743	8406	0	0
exec_regwen_rd_A	325153743	8808	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	325153743	123245	0	0
T25	36325	0	0	0
T28	114132	3794	0	0
T29	0	1037	0	0
T30	0	2207	0	0
T44	493376	0	0	0
T45	0	5073	0	0
T46	0	1882	0	0
T47	0	820	0	0
T48	0	1530	0	0
T49	0	5131	0	0
T50	0	2414	0	0
T51	0	889	0	0
T52	483703	0	0	0
T53	300136	0	0	0
T54	92875	0	0	0
T55	22731	0	0	0
T56	13356	0	0	0
T57	100973	0	0	0
T58	6760	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	325153743	9026	0	0
T24	329524	0	0	0
T29	24568	201	0	0
T46	0	367	0	0
T47	0	190	0	0
T48	0	509	0	0
T51	0	134	0	0
T85	19626	0	0	0
T86	330473	0	0	0
T87	177895	0	0	0
T110	0	415	0	0
T111	0	773	0	0
T112	0	129	0	0
T113	0	372	0	0
T114	0	1017	0	0
T115	43697	0	0	0
T116	43857	0	0	0
T117	143600	0	0	0
T118	5931	0	0	0
T119	3926	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	325153743	8406	0	0
T24	329524	0	0	0
T29	24568	272	0	0
T46	0	287	0	0
T47	0	211	0	0
T48	0	427	0	0
T51	0	252	0	0
T85	19626	0	0	0
T86	330473	0	0	0
T87	177895	0	0	0
T110	0	351	0	0
T111	0	694	0	0
T112	0	164	0	0
T113	0	352	0	0
T114	0	816	0	0
T115	43697	0	0	0
T116	43857	0	0	0
T117	143600	0	0	0
T118	5931	0	0	0
T119	3926	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	325153743	8808	0	0
T24	329524	0	0	0
T29	24568	168	0	0
T46	0	383	0	0
T47	0	146	0	0
T48	0	519	0	0
T51	0	176	0	0
T85	19626	0	0	0
T86	330473	0	0	0
T87	177895	0	0	0
T110	0	418	0	0
T111	0	737	0	0
T112	0	122	0	0
T113	0	343	0	0
T114	0	892	0	0
T115	43697	0	0	0
T116	43857	0	0	0
T117	143600	0	0	0
T118	5931	0	0	0
T119	3926	0	0	0