Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14376578	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

62257462

1

T1

130381

T2

47

T3

23296

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	38194404	1			T1	71733		T2	360		T3	11246
values[0x0]	17783688	1			T1	34493		T2	192		T3	6807
values[0x1]	20655948	1			T1	37082		T2	410		T3	7025

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7161438	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

69472602

1

T1

136868

T2

454

T3

24173

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	353271	1			T1	577		T2	2		T3	76
valid_sources[0x01]	296629	1			T1	563		T3	80		T8	326
valid_sources[0x02]	278911	1			T1	541		T2	1		T3	85
valid_sources[0x03]	273365	1			T1	563		T2	14		T3	102
valid_sources[0x04]	332452	1			T1	543		T2	14		T3	86
valid_sources[0x05]	251800	1			T1	553		T2	10		T3	105
valid_sources[0x06]	261908	1			T1	583		T2	1		T3	84
valid_sources[0x07]	318234	1			T1	573		T3	102		T8	335
valid_sources[0x08]	306837	1			T1	546		T3	104		T8	356
valid_sources[0x09]	295211	1			T1	586		T3	95		T8	363
valid_sources[0x0a]	288884	1			T1	566		T2	3		T3	98
valid_sources[0x0b]	251471	1			T1	594		T3	103		T8	345
valid_sources[0x0c]	248785	1			T1	500		T3	82		T8	352
valid_sources[0x0d]	300793	1			T1	570		T2	2		T3	90
valid_sources[0x0e]	318284	1			T1	588		T2	4		T3	92
valid_sources[0x0f]	361881	1			T1	501		T2	8		T3	105
valid_sources[0x10]	291065	1			T1	512		T2	31		T3	104
valid_sources[0x11]	287603	1			T1	554		T2	2		T3	93
valid_sources[0x12]	371131	1			T1	579		T2	11		T3	96
valid_sources[0x13]	293882	1			T1	552		T2	2		T3	80
valid_sources[0x14]	266468	1			T1	534		T2	13		T3	107
valid_sources[0x15]	339052	1			T1	599		T2	4		T3	120
valid_sources[0x16]	249253	1			T1	553		T3	93		T8	363
valid_sources[0x17]	308749	1			T1	537		T2	3		T3	90
valid_sources[0x18]	272461	1			T1	617		T3	77		T8	368
valid_sources[0x19]	383371	1			T1	568		T2	7		T3	97
valid_sources[0x1a]	324149	1			T1	592		T3	94		T8	352
valid_sources[0x1b]	370278	1			T1	538		T2	1		T3	104
valid_sources[0x1c]	318186	1			T1	572		T3	100		T8	308
valid_sources[0x1d]	288896	1			T1	559		T3	110		T8	353
valid_sources[0x1e]	295374	1			T1	591		T2	9		T3	104
valid_sources[0x1f]	254485	1			T1	587		T2	8		T3	110
valid_sources[0x20]	308062	1			T1	610		T3	102		T8	375
valid_sources[0x21]	286040	1			T1	576		T2	12		T3	92
valid_sources[0x22]	290863	1			T1	572		T3	77		T8	362
valid_sources[0x23]	283542	1			T1	544		T2	1		T3	88
valid_sources[0x24]	283290	1			T1	574		T3	76		T8	339
valid_sources[0x25]	304317	1			T1	547		T2	1		T3	101
valid_sources[0x26]	254234	1			T1	536		T3	106		T8	346
valid_sources[0x27]	322114	1			T1	529		T2	5		T3	108
valid_sources[0x28]	280403	1			T1	574		T2	9		T3	80
valid_sources[0x29]	384000	1			T1	586		T3	69		T8	317
valid_sources[0x2a]	263961	1			T1	543		T3	94		T8	379
valid_sources[0x2b]	267743	1			T1	577		T2	4		T3	94
valid_sources[0x2c]	293212	1			T1	594		T2	7		T3	111
valid_sources[0x2d]	253861	1			T1	549		T2	16		T3	98
valid_sources[0x2e]	313022	1			T1	575		T2	13		T3	83
valid_sources[0x2f]	268494	1			T1	536		T3	101		T8	367
valid_sources[0x30]	342706	1			T1	567		T3	112		T8	352
valid_sources[0x31]	278340	1			T1	532		T2	10		T3	104
valid_sources[0x32]	417246	1			T1	562		T2	3		T3	109
valid_sources[0x33]	277946	1			T1	544		T2	3		T3	75
valid_sources[0x34]	331012	1			T1	571		T3	83		T8	319
valid_sources[0x35]	280469	1			T1	544		T3	100		T8	329
valid_sources[0x36]	264776	1			T1	555		T2	4		T3	115
valid_sources[0x37]	367510	1			T1	536		T2	1		T3	113
valid_sources[0x38]	265303	1			T1	575		T3	120		T8	356
valid_sources[0x39]	326203	1			T1	536		T2	9		T3	110
valid_sources[0x3a]	257716	1			T1	520		T2	15		T3	125
valid_sources[0x3b]	266524	1			T1	552		T3	102		T8	353
valid_sources[0x3c]	376780	1			T1	576		T2	8		T3	88
valid_sources[0x3d]	289472	1			T1	546		T3	116		T8	341
valid_sources[0x3e]	275696	1			T1	600		T3	102		T8	324
valid_sources[0x3f]	312119	1			T1	539		T3	83		T8	356
valid_sources[0x40]	299565	1			T1	533		T3	84		T8	354
valid_sources[0x41]	285292	1			T1	530		T3	98		T8	315
valid_sources[0x42]	319257	1			T1	568		T3	106		T8	342
valid_sources[0x43]	262159	1			T1	550		T2	1		T3	85
valid_sources[0x44]	277991	1			T1	595		T3	109		T8	320
valid_sources[0x45]	277426	1			T1	582		T2	18		T3	101
valid_sources[0x46]	295575	1			T1	563		T2	1		T3	92
valid_sources[0x47]	250039	1			T1	539		T2	9		T3	85
valid_sources[0x48]	299588	1			T1	557		T3	101		T8	372
valid_sources[0x49]	267195	1			T1	542		T2	2		T3	84
valid_sources[0x4a]	292274	1			T1	600		T2	5		T3	82
valid_sources[0x4b]	322244	1			T1	565		T3	93		T8	349
valid_sources[0x4c]	326737	1			T1	549		T3	124		T8	323
valid_sources[0x4d]	263898	1			T1	576		T2	13		T3	113
valid_sources[0x4e]	292539	1			T1	602		T2	4		T3	69
valid_sources[0x4f]	307188	1			T1	613		T2	8		T3	118
valid_sources[0x50]	290731	1			T1	591		T2	2		T3	98
valid_sources[0x51]	281568	1			T1	611		T3	101		T8	368
valid_sources[0x52]	342227	1			T1	535		T2	2		T3	86
valid_sources[0x53]	283710	1			T1	552		T3	93		T8	392
valid_sources[0x54]	270896	1			T1	615		T2	1		T3	87
valid_sources[0x55]	354910	1			T1	529		T3	113		T8	335
valid_sources[0x56]	389734	1			T1	555		T3	106		T8	346
valid_sources[0x57]	289986	1			T1	553		T2	15		T3	106
valid_sources[0x58]	313391	1			T1	543		T3	80		T8	366
valid_sources[0x59]	324858	1			T1	586		T2	1		T3	95
valid_sources[0x5a]	299109	1			T1	568		T3	84		T8	326
valid_sources[0x5b]	353201	1			T1	535		T3	87		T8	353
valid_sources[0x5c]	261222	1			T1	504		T3	91		T8	358
valid_sources[0x5d]	305699	1			T1	547		T2	2		T3	125
valid_sources[0x5e]	270959	1			T1	577		T3	101		T8	364
valid_sources[0x5f]	275173	1			T1	538		T3	105		T8	351
valid_sources[0x60]	301891	1			T1	571		T2	2		T3	108
valid_sources[0x61]	284369	1			T1	538		T2	22		T3	103
valid_sources[0x62]	317952	1			T1	562		T2	20		T3	103
valid_sources[0x63]	322557	1			T1	583		T2	14		T3	82
valid_sources[0x64]	290927	1			T1	552		T2	12		T3	89
valid_sources[0x65]	297593	1			T1	606		T2	5		T3	96
valid_sources[0x66]	327563	1			T1	563		T2	5		T3	87
valid_sources[0x67]	342047	1			T1	529		T2	8		T3	100
valid_sources[0x68]	287083	1			T1	557		T2	1		T3	89
valid_sources[0x69]	310605	1			T1	533		T2	14		T3	96
valid_sources[0x6a]	316925	1			T1	543		T2	4		T3	89
valid_sources[0x6b]	280590	1			T1	524		T3	97		T8	371
valid_sources[0x6c]	298692	1			T1	575		T3	103		T8	339
valid_sources[0x6d]	358269	1			T1	568		T2	1		T3	102
valid_sources[0x6e]	303745	1			T1	558		T3	120		T8	358
valid_sources[0x6f]	355046	1			T1	506		T3	94		T8	326
valid_sources[0x70]	284207	1			T1	537		T2	2		T3	126
valid_sources[0x71]	302363	1			T1	562		T3	82		T8	355
valid_sources[0x72]	257058	1			T1	582		T2	4		T3	93
valid_sources[0x73]	304698	1			T1	604		T2	2		T3	114
valid_sources[0x74]	288822	1			T1	592		T2	6		T3	106
valid_sources[0x75]	365482	1			T1	553		T3	121		T8	322
valid_sources[0x76]	254792	1			T1	524		T3	124		T8	355
valid_sources[0x77]	327558	1			T1	554		T3	114		T8	332
valid_sources[0x78]	352165	1			T1	573		T3	110		T8	388
valid_sources[0x79]	287998	1			T1	543		T3	81		T8	340
valid_sources[0x7a]	268125	1			T1	599		T3	91		T8	365
valid_sources[0x7b]	363027	1			T1	549		T3	97		T8	344
valid_sources[0x7c]	298149	1			T1	577		T3	92		T8	358
valid_sources[0x7d]	345395	1			T1	544		T3	89		T8	345
valid_sources[0x7e]	320368	1			T1	566		T2	20		T3	91
valid_sources[0x7f]	393640	1			T1	564		T2	3		T3	83
valid_sources[0x80]	281923	1			T1	536		T3	71		T8	388

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

31007980

1

T1

65238

T2

3

T3

10363

values[0x0]

all_enables

biggest_size

15627131

1

T1

32578

T2

25

T3

6533

values[0x1]

all_enables

biggest_size

15622351

1

T1

32565

T2

19

T3

6400

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36488	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

152787

1

T1

2

T3

1929

T8

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	54384	1			T3	554		T8	10		T4	15
values[0x0]	65234	1			T1	4		T2	1		T3	755
values[0x1]	69657	1			T1	2		T3	726		T8	25

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27904	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

161371

1

T1

2

T3

1960

T8

21

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	948	1			T3	6		T24	14		T136	1
valid_sources[0x01]	834	1			T3	18		T22	1		T24	26
valid_sources[0x02]	793	1			T3	1		T12	1		T22	89
valid_sources[0x03]	516	1			T3	5		T12	1		T24	22
valid_sources[0x04]	634	1			T3	4		T12	1		T40	1
valid_sources[0x05]	734	1			T3	8		T12	1		T22	1
valid_sources[0x06]	823	1			T3	4		T49	1		T12	2
valid_sources[0x07]	643	1			T3	6		T22	8		T137	2
valid_sources[0x08]	851	1			T3	7		T12	1		T22	6
valid_sources[0x09]	733	1			T3	5		T22	88		T6	1
valid_sources[0x0a]	691	1			T3	4		T22	32		T6	3
valid_sources[0x0b]	504	1			T3	5		T24	40		T50	1
valid_sources[0x0c]	689	1			T3	5		T8	2		T39	4
valid_sources[0x0d]	665	1			T3	7		T22	1		T6	1
valid_sources[0x0e]	646	1			T3	5		T6	1		T24	16
valid_sources[0x0f]	490	1			T3	20		T22	4		T24	35
valid_sources[0x10]	1016	1			T3	9		T23	180		T24	39
valid_sources[0x11]	677	1			T3	17		T24	20		T44	8
valid_sources[0x12]	685	1			T3	2		T38	2		T22	1
valid_sources[0x13]	654	1			T3	10		T12	2		T22	6
valid_sources[0x14]	828	1			T3	6		T22	1		T39	3
valid_sources[0x15]	743	1			T3	6		T22	3		T130	4
valid_sources[0x16]	613	1			T3	18		T12	4		T38	1
valid_sources[0x17]	827	1			T3	9		T4	1		T10	1
valid_sources[0x18]	888	1			T3	4		T22	4		T24	30
valid_sources[0x19]	523	1			T3	9		T12	1		T24	12
valid_sources[0x1a]	679	1			T3	6		T22	5		T39	1
valid_sources[0x1b]	665	1			T3	11		T24	28		T43	3
valid_sources[0x1c]	627	1			T3	5		T12	1		T24	17
valid_sources[0x1d]	702	1			T3	8		T22	7		T24	20
valid_sources[0x1e]	657	1			T3	8		T8	1		T21	19
valid_sources[0x1f]	537	1			T3	18		T10	2		T24	24
valid_sources[0x20]	599	1			T3	17		T22	3		T6	1
valid_sources[0x21]	615	1			T3	1		T24	22		T43	83
valid_sources[0x22]	856	1			T3	15		T22	2		T24	15
valid_sources[0x23]	767	1			T3	7		T10	1		T41	10
valid_sources[0x24]	1031	1			T3	6		T138	1		T24	27
valid_sources[0x25]	893	1			T3	12		T22	1		T6	1
valid_sources[0x26]	939	1			T3	4		T6	1		T24	43
valid_sources[0x27]	1250	1			T3	4		T12	1		T24	43
valid_sources[0x28]	647	1			T3	8		T8	2		T12	1
valid_sources[0x29]	622	1			T3	10		T12	2		T6	2
valid_sources[0x2a]	638	1			T3	2		T22	2		T24	21
valid_sources[0x2b]	671	1			T3	11		T12	1		T22	2
valid_sources[0x2c]	716	1			T3	5		T130	2		T24	57
valid_sources[0x2d]	764	1			T3	9		T38	1		T24	27
valid_sources[0x2e]	567	1			T3	7		T22	1		T130	3
valid_sources[0x2f]	534	1			T3	8		T38	1		T22	2
valid_sources[0x30]	566	1			T3	7		T6	1		T130	2
valid_sources[0x31]	921	1			T3	10		T6	4		T24	28
valid_sources[0x32]	1037	1			T3	1		T22	86		T24	27
valid_sources[0x33]	707	1			T3	5		T24	49		T90	1
valid_sources[0x34]	762	1			T3	2		T38	1		T22	15
valid_sources[0x35]	1098	1			T3	17		T22	218		T6	1
valid_sources[0x36]	753	1			T3	4		T4	1		T22	3
valid_sources[0x37]	543	1			T3	5		T8	5		T12	1
valid_sources[0x38]	593	1			T3	6		T12	2		T22	29
valid_sources[0x39]	1126	1			T3	6		T22	100		T24	18
valid_sources[0x3a]	1128	1			T3	8		T22	105		T6	1
valid_sources[0x3b]	709	1			T3	2		T22	72		T24	38
valid_sources[0x3c]	852	1			T3	5		T38	1		T24	25
valid_sources[0x3d]	931	1			T3	8		T22	142		T24	18
valid_sources[0x3e]	738	1			T3	5		T40	3		T24	12
valid_sources[0x3f]	936	1			T3	13		T8	1		T12	1
valid_sources[0x40]	680	1			T3	16		T10	3		T22	2
valid_sources[0x41]	526	1			T3	7		T22	2		T40	1
valid_sources[0x42]	673	1			T3	6		T5	156		T12	2
valid_sources[0x43]	811	1			T3	9		T12	1		T22	76
valid_sources[0x44]	501	1			T3	7		T24	16		T139	2
valid_sources[0x45]	714	1			T3	9		T22	1		T6	2
valid_sources[0x46]	630	1			T3	9		T22	1		T24	25
valid_sources[0x47]	683	1			T3	16		T22	22		T24	41
valid_sources[0x48]	587	1			T3	4		T12	1		T22	2
valid_sources[0x49]	738	1			T3	13		T22	95		T24	45
valid_sources[0x4a]	825	1			T3	11		T22	27		T24	29
valid_sources[0x4b]	855	1			T3	13		T39	3		T24	37
valid_sources[0x4c]	625	1			T3	15		T40	1		T24	24
valid_sources[0x4d]	493	1			T3	6		T12	1		T22	1
valid_sources[0x4e]	901	1			T3	6		T22	15		T6	2
valid_sources[0x4f]	610	1			T3	13		T8	6		T25	1
valid_sources[0x50]	556	1			T3	6		T10	6		T12	1
valid_sources[0x51]	552	1			T3	5		T10	2		T22	1
valid_sources[0x52]	793	1			T3	9		T12	4		T22	2
valid_sources[0x53]	812	1			T3	12		T24	23		T134	1
valid_sources[0x54]	728	1			T3	9		T12	3		T22	1
valid_sources[0x55]	894	1			T3	7		T24	14		T50	1
valid_sources[0x56]	618	1			T3	5		T24	27		T140	2
valid_sources[0x57]	755	1			T3	2		T10	1		T22	1
valid_sources[0x58]	950	1			T3	12		T22	4		T6	1
valid_sources[0x59]	580	1			T3	13		T10	1		T6	1
valid_sources[0x5a]	559	1			T3	8		T24	32		T141	1
valid_sources[0x5b]	777	1			T3	14		T22	83		T39	5
valid_sources[0x5c]	612	1			T3	8		T24	28		T133	1
valid_sources[0x5d]	680	1			T3	2		T38	2		T40	1
valid_sources[0x5e]	646	1			T3	4		T8	2		T24	20
valid_sources[0x5f]	546	1			T1	6		T3	8		T12	2
valid_sources[0x60]	740	1			T3	9		T6	1		T24	16
valid_sources[0x61]	797	1			T3	5		T12	1		T22	198
valid_sources[0x62]	499	1			T3	11		T10	1		T6	1
valid_sources[0x63]	587	1			T3	7		T10	6		T24	28
valid_sources[0x64]	622	1			T3	5		T24	16		T141	1
valid_sources[0x65]	919	1			T3	9		T22	126		T6	4
valid_sources[0x66]	717	1			T3	11		T24	41		T142	1
valid_sources[0x67]	704	1			T3	3		T40	1		T24	33
valid_sources[0x68]	839	1			T3	8		T22	1		T24	30
valid_sources[0x69]	643	1			T3	4		T24	29		T50	2
valid_sources[0x6a]	1015	1			T3	5		T22	1		T24	29
valid_sources[0x6b]	1481	1			T3	4		T12	1		T22	202
valid_sources[0x6c]	935	1			T3	7		T38	1		T6	3
valid_sources[0x6d]	897	1			T3	8		T24	27		T43	142
valid_sources[0x6e]	1105	1			T3	5		T22	226		T24	47
valid_sources[0x6f]	583	1			T3	14		T22	1		T24	40
valid_sources[0x70]	904	1			T3	9		T24	40		T42	108
valid_sources[0x71]	527	1			T3	3		T24	32		T50	1
valid_sources[0x72]	731	1			T3	8		T12	2		T22	229
valid_sources[0x73]	764	1			T3	6		T143	2		T22	57
valid_sources[0x74]	800	1			T3	7		T6	2		T24	26
valid_sources[0x75]	820	1			T3	11		T22	3		T24	22
valid_sources[0x76]	1218	1			T3	5		T12	2		T22	117
valid_sources[0x77]	762	1			T3	2		T8	1		T22	108
valid_sources[0x78]	668	1			T3	2		T24	50		T51	1
valid_sources[0x79]	622	1			T3	4		T24	14		T131	2
valid_sources[0x7a]	887	1			T3	3		T22	1		T24	19
valid_sources[0x7b]	488	1			T3	9		T130	1		T24	25
valid_sources[0x7c]	542	1			T3	10		T22	2		T39	1
valid_sources[0x7d]	684	1			T3	5		T7	1		T24	25
valid_sources[0x7e]	920	1			T3	7		T12	2		T22	165
valid_sources[0x7f]	564	1			T3	4		T40	1		T130	1
valid_sources[0x80]	804	1			T3	8		T22	1		T6	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

41625

1

T3

501

T8

7

T4

8

values[0x0]

all_enables

biggest_size

56640

1

T1

1

T3

750

T8

6

values[0x1]

all_enables

biggest_size

54522

1

T1

1

T3

678

T8

5