Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14080953

1

T1

12927

T2

915

T3

4266

full_word

57076044

1

T1

130381

T2

47

T3

23615

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	71156707	1			T1	143308		T2	962		T3	27881
auto[TlIntgErrCmd]	101	1			T96	5		T97	4		T98	5
auto[TlIntgErrData]	101	1			T96	3		T97	4		T98	2
auto[TlIntgErrBoth]	88	1			T96	2		T97	2		T98	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32636278

1

T1

71733

T2

360

T3

11824

auto[1]

38520719

1

T1

71575

T2

602

T3

16057

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6721607	1			T1	6495		T2	357		T3	1389
auto[TlIntgErrNone]	partial	auto[1]	7359082	1			T1	6432		T2	558		T3	2877
auto[TlIntgErrNone]	full_word	auto[0]	25914544	1			T1	65238		T2	3		T3	10435
auto[TlIntgErrNone]	full_word	auto[1]	31161474	1			T1	65143		T2	44		T3	13180
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T96	3		T98	1		T120	5
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T96	2		T97	4		T98	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T120	1		T126	1		T127	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T123	1		T122	1		T118	2
auto[TlIntgErrData]	partial	auto[0]	53	1			T96	2		T97	2		T98	1
auto[TlIntgErrData]	partial	auto[1]	36	1			T96	1		T97	1		T98	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T97	1		T123	1		T122	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T120	2		T121	1		T123	1
auto[TlIntgErrBoth]	partial	auto[0]	27	1			T96	2		T97	1		T98	3
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T97	1		T120	4		T121	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T120	1		T128	1		T129	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T122	1		T126	1		T119	1