Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	598663	1			T2	102		T12	4526		T13	92
auto[1]	11465624	1			T1	59811		T2	84		T3	8857
auto[2]	508843	1			T2	64		T12	4173		T13	63
auto[3]	11390678	1			T1	59610		T2	142		T3	8730

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	15840261	1			T1	99846		T3	14577		T8	3507
auto[1]	2270901	1			T1	9354		T2	7		T3	1426
auto[2]	2270301	1			T1	9340		T2	13		T3	1438
auto[3]	3582345	1			T1	881		T2	372		T3	146

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9707022

1

T2

390

T3

17568

T8

4255

auto[1]

14256786

1

T1

119421

T2

2

T3

19

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	265213	1			T12	3706		T41	508		T6	1087
auto[0]	auto[0]	auto[1]	27638	1			T2	1		T12	385		T13	2
auto[0]	auto[0]	auto[2]	27188	1			T12	385		T13	2		T41	62
auto[0]	auto[0]	auto[3]	7616	1			T2	99		T12	44		T13	86
auto[0]	auto[1]	auto[0]	3725432	1			T3	7368		T8	1749		T5	8310
auto[0]	auto[1]	auto[1]	386588	1			T2	1		T3	697		T8	188
auto[0]	auto[1]	auto[2]	378297	1			T2	3		T3	709		T8	184
auto[0]	auto[1]	auto[3]	80213	1			T2	80		T3	71		T8	24
auto[0]	auto[2]	auto[0]	227503	1			T12	3476		T41	482		T6	699
auto[0]	auto[2]	auto[1]	23596	1			T2	5		T12	326		T13	10
auto[0]	auto[2]	auto[2]	21239	1			T12	323		T41	36		T6	106
auto[0]	auto[2]	auto[3]	5862	1			T2	59		T12	45		T13	53
auto[0]	auto[3]	auto[0]	3690789	1			T3	7194		T8	1755		T4	2
auto[0]	auto[3]	auto[1]	374418	1			T3	727		T8	171		T5	915
auto[0]	auto[3]	auto[2]	382728	1			T2	10		T3	728		T8	167
auto[0]	auto[3]	auto[3]	82702	1			T2	132		T3	74		T8	17
auto[1]	auto[0]	auto[0]	9250	1			T12	6		T133	4		T134	1
auto[1]	auto[0]	auto[1]	40266	1			T41	1		T133	3		T91	5207
auto[1]	auto[0]	auto[2]	40191	1			T134	1		T91	5208		T92	1554
auto[1]	auto[0]	auto[3]	181301	1			T2	2		T13	2		T134	1
auto[1]	auto[1]	auto[0]	3957395	1			T1	49992		T3	11		T8	1
auto[1]	auto[1]	auto[1]	702801	1			T1	4443		T9	6813		T38	2
auto[1]	auto[1]	auto[2]	688115	1			T1	4927		T9	6686		T21	1
auto[1]	auto[1]	auto[3]	1546783	1			T1	449		T3	1		T9	707
auto[1]	auto[2]	auto[0]	7807	1			T12	3		T41	2		T6	1
auto[1]	auto[2]	auto[1]	33828	1			T91	4891		T92	938		T108	1
auto[1]	auto[2]	auto[2]	34303	1			T91	3506		T92	1406		T111	4224
auto[1]	auto[2]	auto[3]	154705	1			T91	15756		T92	6367		T111	19040
auto[1]	auto[3]	auto[0]	3956872	1			T1	49854		T3	4		T8	2
auto[1]	auto[3]	auto[1]	681766	1			T1	4911		T3	2		T9	6713
auto[1]	auto[3]	auto[2]	698240	1			T1	4413		T3	1		T9	6727
auto[1]	auto[3]	auto[3]	1523163	1			T1	432		T9	645		T135	4