Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.39	100.00	94.62	100.00		100.00	92.31	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	319561576	156391	0	0
ctrl_regwen_rd_A	319561576	4616	0	0
exec_rd_A	319561576	4135	0	0
exec_regwen_rd_A	319561576	4662	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319561576	156391	0	0
T3	41270	1444	0	0
T4	31293	0	0	0
T5	616608	0	0	0
T7	2870	0	0	0
T8	144124	0	0	0
T9	235900	0	0	0
T10	125056	0	0	0
T11	4976	0	0	0
T14	697627	0	0	0
T22	0	6308	0	0
T24	0	9172	0	0
T42	0	3236	0	0
T43	0	3287	0	0
T44	0	2140	0	0
T45	0	1875	0	0
T46	0	3104	0	0
T47	0	1079	0	0
T48	0	6604	0	0
T49	23656	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319561576	4616	0	0
T34	0	476	0	0
T46	145049	630	0	0
T47	0	262	0	0
T53	0	12	0	0
T100	0	366	0	0
T101	0	335	0	0
T102	0	95	0	0
T103	0	355	0	0
T104	0	417	0	0
T105	0	239	0	0
T106	45563	0	0	0
T107	15204	0	0	0
T108	657251	0	0	0
T109	11794	0	0	0
T110	8753	0	0	0
T111	202619	0	0	0
T112	113004	0	0	0
T113	3421	0	0	0
T114	1956	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319561576	4135	0	0
T34	0	556	0	0
T46	145049	599	0	0
T47	0	216	0	0
T53	0	12	0	0
T100	0	293	0	0
T101	0	213	0	0
T102	0	99	0	0
T103	0	332	0	0
T104	0	304	0	0
T105	0	265	0	0
T106	45563	0	0	0
T107	15204	0	0	0
T108	657251	0	0	0
T109	11794	0	0	0
T110	8753	0	0	0
T111	202619	0	0	0
T112	113004	0	0	0
T113	3421	0	0	0
T114	1956	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319561576	4662	0	0
T34	0	520	0	0
T46	145049	537	0	0
T47	0	161	0	0
T100	0	399	0	0
T101	0	294	0	0
T102	0	157	0	0
T103	0	393	0	0
T104	0	357	0	0
T105	0	300	0	0
T106	45563	0	0	0
T107	15204	0	0	0
T108	657251	0	0	0
T109	11794	0	0	0
T110	8753	0	0	0
T111	202619	0	0	0
T112	113004	0	0	0
T113	3421	0	0	0
T114	1956	0	0	0
T115	0	22	0	0