| T803 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.2891518317 |
|
|
Apr 23 12:24:53 PM PDT 24 |
Apr 23 12:25:00 PM PDT 24 |
64949306 ps |
| T804 |
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.2685105758 |
|
|
Apr 23 12:23:19 PM PDT 24 |
Apr 23 12:25:54 PM PDT 24 |
689201614 ps |
| T805 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.693812123 |
|
|
Apr 23 12:24:15 PM PDT 24 |
Apr 23 12:36:35 PM PDT 24 |
41374181209 ps |
| T806 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2344089796 |
|
|
Apr 23 12:25:29 PM PDT 24 |
Apr 23 12:27:38 PM PDT 24 |
279295900 ps |
| T807 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.3314361066 |
|
|
Apr 23 12:25:18 PM PDT 24 |
Apr 23 12:33:15 PM PDT 24 |
2274801549 ps |
| T808 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.3345195908 |
|
|
Apr 23 12:24:04 PM PDT 24 |
Apr 23 12:24:11 PM PDT 24 |
434092006 ps |
| T809 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.247030825 |
|
|
Apr 23 12:24:34 PM PDT 24 |
Apr 23 12:27:51 PM PDT 24 |
4172879890 ps |
| T810 |
/workspace/coverage/default/29.sram_ctrl_partial_access.1777151704 |
|
|
Apr 23 12:24:56 PM PDT 24 |
Apr 23 12:25:09 PM PDT 24 |
265105919 ps |
| T811 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.1008279910 |
|
|
Apr 23 12:24:56 PM PDT 24 |
Apr 23 01:00:42 PM PDT 24 |
22613282427 ps |
| T812 |
/workspace/coverage/default/32.sram_ctrl_smoke.1357824238 |
|
|
Apr 23 12:25:00 PM PDT 24 |
Apr 23 12:26:29 PM PDT 24 |
369754680 ps |
| T813 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.2624964024 |
|
|
Apr 23 12:25:27 PM PDT 24 |
Apr 23 12:25:32 PM PDT 24 |
83626081 ps |
| T814 |
/workspace/coverage/default/3.sram_ctrl_lc_escalation.3641968745 |
|
|
Apr 23 12:24:34 PM PDT 24 |
Apr 23 12:24:41 PM PDT 24 |
6323888319 ps |
| T815 |
/workspace/coverage/default/19.sram_ctrl_partial_access.45123094 |
|
|
Apr 23 12:24:25 PM PDT 24 |
Apr 23 12:24:43 PM PDT 24 |
4787638839 ps |
| T816 |
/workspace/coverage/default/32.sram_ctrl_stress_all.22865454 |
|
|
Apr 23 12:25:07 PM PDT 24 |
Apr 23 01:51:12 PM PDT 24 |
161418602894 ps |
| T817 |
/workspace/coverage/default/42.sram_ctrl_smoke.3285351625 |
|
|
Apr 23 12:25:26 PM PDT 24 |
Apr 23 12:25:49 PM PDT 24 |
1215416429 ps |
| T818 |
/workspace/coverage/default/41.sram_ctrl_alert_test.2034006478 |
|
|
Apr 23 12:25:20 PM PDT 24 |
Apr 23 12:25:22 PM PDT 24 |
19541136 ps |
| T819 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.2032898418 |
|
|
Apr 23 12:24:11 PM PDT 24 |
Apr 23 12:24:17 PM PDT 24 |
341603209 ps |
| T820 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1337429691 |
|
|
Apr 23 12:25:37 PM PDT 24 |
Apr 23 12:26:06 PM PDT 24 |
367077539 ps |
| T821 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.210595238 |
|
|
Apr 23 12:25:09 PM PDT 24 |
Apr 23 12:25:19 PM PDT 24 |
66551243 ps |
| T822 |
/workspace/coverage/default/8.sram_ctrl_partial_access.61028046 |
|
|
Apr 23 12:23:58 PM PDT 24 |
Apr 23 12:24:05 PM PDT 24 |
1278193053 ps |
| T823 |
/workspace/coverage/default/44.sram_ctrl_bijection.3157714371 |
|
|
Apr 23 12:25:30 PM PDT 24 |
Apr 23 12:26:12 PM PDT 24 |
5446912658 ps |
| T824 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.3848403631 |
|
|
Apr 23 12:24:10 PM PDT 24 |
Apr 23 12:24:18 PM PDT 24 |
117582271 ps |
| T825 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.3548975568 |
|
|
Apr 23 12:25:27 PM PDT 24 |
Apr 23 12:25:34 PM PDT 24 |
2168187131 ps |
| T826 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.573700407 |
|
|
Apr 23 12:23:20 PM PDT 24 |
Apr 23 12:23:24 PM PDT 24 |
57321801 ps |
| T827 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.3065431082 |
|
|
Apr 23 12:23:58 PM PDT 24 |
Apr 23 12:25:24 PM PDT 24 |
300386438 ps |
| T828 |
/workspace/coverage/default/39.sram_ctrl_partial_access.1775492908 |
|
|
Apr 23 12:25:08 PM PDT 24 |
Apr 23 12:25:29 PM PDT 24 |
3477931754 ps |
| T829 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.2664281472 |
|
|
Apr 23 12:24:27 PM PDT 24 |
Apr 23 12:30:59 PM PDT 24 |
20859403995 ps |
| T830 |
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.3918571509 |
|
|
Apr 23 12:25:29 PM PDT 24 |
Apr 23 12:51:27 PM PDT 24 |
3461006132 ps |
| T831 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.1556496533 |
|
|
Apr 23 12:23:23 PM PDT 24 |
Apr 23 12:23:34 PM PDT 24 |
767246802 ps |
| T832 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.2624081821 |
|
|
Apr 23 12:25:32 PM PDT 24 |
Apr 23 12:25:33 PM PDT 24 |
88703387 ps |
| T833 |
/workspace/coverage/default/15.sram_ctrl_ram_cfg.3947599634 |
|
|
Apr 23 12:24:35 PM PDT 24 |
Apr 23 12:24:37 PM PDT 24 |
49955087 ps |
| T834 |
/workspace/coverage/default/31.sram_ctrl_ram_cfg.2831713962 |
|
|
Apr 23 12:25:06 PM PDT 24 |
Apr 23 12:25:10 PM PDT 24 |
94685248 ps |
| T835 |
/workspace/coverage/default/48.sram_ctrl_lc_escalation.2792867109 |
|
|
Apr 23 12:25:46 PM PDT 24 |
Apr 23 12:25:56 PM PDT 24 |
677857070 ps |
| T836 |
/workspace/coverage/default/39.sram_ctrl_mem_partial_access.3337598882 |
|
|
Apr 23 12:25:16 PM PDT 24 |
Apr 23 12:25:24 PM PDT 24 |
308563135 ps |
| T837 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.1890272971 |
|
|
Apr 23 12:25:06 PM PDT 24 |
Apr 23 12:25:14 PM PDT 24 |
132192400 ps |
| T838 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.497621640 |
|
|
Apr 23 12:25:14 PM PDT 24 |
Apr 23 12:27:08 PM PDT 24 |
4190004856 ps |
| T839 |
/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.915409917 |
|
|
Apr 23 12:24:35 PM PDT 24 |
Apr 23 12:24:58 PM PDT 24 |
345372598 ps |
| T840 |
/workspace/coverage/default/9.sram_ctrl_bijection.1035098478 |
|
|
Apr 23 12:23:52 PM PDT 24 |
Apr 23 12:24:20 PM PDT 24 |
7796641255 ps |
| T841 |
/workspace/coverage/default/23.sram_ctrl_stress_all.1657155459 |
|
|
Apr 23 12:24:32 PM PDT 24 |
Apr 23 01:16:58 PM PDT 24 |
19349498153 ps |
| T842 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.606664838 |
|
|
Apr 23 12:25:06 PM PDT 24 |
Apr 23 12:25:11 PM PDT 24 |
38810397 ps |
| T843 |
/workspace/coverage/default/42.sram_ctrl_mem_walk.3838710206 |
|
|
Apr 23 12:25:26 PM PDT 24 |
Apr 23 12:25:33 PM PDT 24 |
643628257 ps |
| T844 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.902275457 |
|
|
Apr 23 12:25:18 PM PDT 24 |
Apr 23 12:30:48 PM PDT 24 |
18223154983 ps |
| T845 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.1633178699 |
|
|
Apr 23 12:25:27 PM PDT 24 |
Apr 23 12:25:31 PM PDT 24 |
336229098 ps |
| T846 |
/workspace/coverage/default/4.sram_ctrl_regwen.2324575091 |
|
|
Apr 23 12:24:29 PM PDT 24 |
Apr 23 12:32:27 PM PDT 24 |
15714420425 ps |
| T847 |
/workspace/coverage/default/49.sram_ctrl_executable.1332955450 |
|
|
Apr 23 12:25:47 PM PDT 24 |
Apr 23 12:42:50 PM PDT 24 |
64254736360 ps |
| T848 |
/workspace/coverage/default/10.sram_ctrl_lc_escalation.3433093462 |
|
|
Apr 23 12:24:01 PM PDT 24 |
Apr 23 12:24:10 PM PDT 24 |
8105140661 ps |
| T849 |
/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.883433080 |
|
|
Apr 23 12:24:49 PM PDT 24 |
Apr 23 12:25:38 PM PDT 24 |
485236553 ps |
| T850 |
/workspace/coverage/default/8.sram_ctrl_bijection.169199840 |
|
|
Apr 23 12:23:51 PM PDT 24 |
Apr 23 12:24:53 PM PDT 24 |
8290781926 ps |
| T851 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.1121496186 |
|
|
Apr 23 12:23:41 PM PDT 24 |
Apr 23 12:23:47 PM PDT 24 |
695644841 ps |
| T852 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.3465882428 |
|
|
Apr 23 12:25:16 PM PDT 24 |
Apr 23 12:27:23 PM PDT 24 |
1041411826 ps |
| T853 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.717951463 |
|
|
Apr 23 12:25:40 PM PDT 24 |
Apr 23 12:26:59 PM PDT 24 |
431758180 ps |
| T854 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.864695682 |
|
|
Apr 23 12:25:25 PM PDT 24 |
Apr 23 12:25:29 PM PDT 24 |
329659557 ps |
| T855 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.522554552 |
|
|
Apr 23 12:23:58 PM PDT 24 |
Apr 23 12:24:09 PM PDT 24 |
244732475 ps |
| T856 |
/workspace/coverage/default/46.sram_ctrl_executable.3383812263 |
|
|
Apr 23 12:25:31 PM PDT 24 |
Apr 23 12:29:57 PM PDT 24 |
1160991908 ps |
| T857 |
/workspace/coverage/default/0.sram_ctrl_stress_all.247996006 |
|
|
Apr 23 12:24:05 PM PDT 24 |
Apr 23 12:58:24 PM PDT 24 |
37027623567 ps |
| T858 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.1492887517 |
|
|
Apr 23 12:24:44 PM PDT 24 |
Apr 23 12:24:53 PM PDT 24 |
525066837 ps |
| T859 |
/workspace/coverage/default/42.sram_ctrl_regwen.2908018133 |
|
|
Apr 23 12:25:23 PM PDT 24 |
Apr 23 12:26:13 PM PDT 24 |
4513395602 ps |
| T860 |
/workspace/coverage/default/17.sram_ctrl_mem_walk.2808270286 |
|
|
Apr 23 12:24:38 PM PDT 24 |
Apr 23 12:24:49 PM PDT 24 |
873200286 ps |
| T861 |
/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.1607862661 |
|
|
Apr 23 12:23:29 PM PDT 24 |
Apr 23 12:23:39 PM PDT 24 |
86587014 ps |
| T862 |
/workspace/coverage/default/32.sram_ctrl_bijection.1709271042 |
|
|
Apr 23 12:25:06 PM PDT 24 |
Apr 23 12:25:43 PM PDT 24 |
2730177359 ps |
| T863 |
/workspace/coverage/default/40.sram_ctrl_multiple_keys.3529583780 |
|
|
Apr 23 12:25:16 PM PDT 24 |
Apr 23 12:39:55 PM PDT 24 |
14950398363 ps |
| T864 |
/workspace/coverage/default/17.sram_ctrl_alert_test.2937279077 |
|
|
Apr 23 12:24:33 PM PDT 24 |
Apr 23 12:24:34 PM PDT 24 |
13607000 ps |
| T865 |
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3034800953 |
|
|
Apr 23 12:25:46 PM PDT 24 |
Apr 23 12:26:37 PM PDT 24 |
313564268 ps |
| T866 |
/workspace/coverage/default/35.sram_ctrl_stress_all.2518455957 |
|
|
Apr 23 12:25:11 PM PDT 24 |
Apr 23 12:54:34 PM PDT 24 |
5488986335 ps |
| T867 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.181122459 |
|
|
Apr 23 12:25:41 PM PDT 24 |
Apr 23 12:25:48 PM PDT 24 |
1480614623 ps |
| T868 |
/workspace/coverage/default/45.sram_ctrl_alert_test.3624906365 |
|
|
Apr 23 12:25:20 PM PDT 24 |
Apr 23 12:25:22 PM PDT 24 |
19211839 ps |
| T869 |
/workspace/coverage/default/3.sram_ctrl_stress_pipeline.2174190254 |
|
|
Apr 23 12:24:28 PM PDT 24 |
Apr 23 12:27:15 PM PDT 24 |
4247911128 ps |
| T870 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.162017528 |
|
|
Apr 23 12:25:19 PM PDT 24 |
Apr 23 12:36:57 PM PDT 24 |
4138680323 ps |
| T871 |
/workspace/coverage/default/36.sram_ctrl_ram_cfg.1227113126 |
|
|
Apr 23 12:25:03 PM PDT 24 |
Apr 23 12:25:05 PM PDT 24 |
232956642 ps |
| T872 |
/workspace/coverage/default/35.sram_ctrl_lc_escalation.3980636708 |
|
|
Apr 23 12:25:12 PM PDT 24 |
Apr 23 12:25:17 PM PDT 24 |
135963826 ps |
| T873 |
/workspace/coverage/default/29.sram_ctrl_ram_cfg.878489671 |
|
|
Apr 23 12:24:45 PM PDT 24 |
Apr 23 12:24:47 PM PDT 24 |
59272310 ps |
| T874 |
/workspace/coverage/default/27.sram_ctrl_executable.4054172693 |
|
|
Apr 23 12:24:59 PM PDT 24 |
Apr 23 12:43:13 PM PDT 24 |
3586387107 ps |
| T875 |
/workspace/coverage/default/19.sram_ctrl_regwen.4197001545 |
|
|
Apr 23 12:24:52 PM PDT 24 |
Apr 23 12:29:11 PM PDT 24 |
12258863348 ps |
| T876 |
/workspace/coverage/default/20.sram_ctrl_executable.225335197 |
|
|
Apr 23 12:24:32 PM PDT 24 |
Apr 23 12:44:17 PM PDT 24 |
12466494600 ps |
| T877 |
/workspace/coverage/default/11.sram_ctrl_lc_escalation.2833657675 |
|
|
Apr 23 12:24:13 PM PDT 24 |
Apr 23 12:24:20 PM PDT 24 |
1694612902 ps |
| T878 |
/workspace/coverage/default/25.sram_ctrl_lc_escalation.3597873161 |
|
|
Apr 23 12:24:36 PM PDT 24 |
Apr 23 12:24:41 PM PDT 24 |
380519587 ps |
| T879 |
/workspace/coverage/default/2.sram_ctrl_multiple_keys.1271744471 |
|
|
Apr 23 12:24:11 PM PDT 24 |
Apr 23 12:39:25 PM PDT 24 |
12329474974 ps |
| T880 |
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.2868191965 |
|
|
Apr 23 12:25:40 PM PDT 24 |
Apr 23 12:25:44 PM PDT 24 |
289856387 ps |
| T881 |
/workspace/coverage/default/34.sram_ctrl_bijection.958032526 |
|
|
Apr 23 12:25:03 PM PDT 24 |
Apr 23 12:25:30 PM PDT 24 |
3644017959 ps |
| T72 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.3050928474 |
|
|
Apr 23 12:24:45 PM PDT 24 |
Apr 23 12:24:50 PM PDT 24 |
526165954 ps |
| T882 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2212373922 |
|
|
Apr 23 12:23:23 PM PDT 24 |
Apr 23 12:24:59 PM PDT 24 |
4324640467 ps |
| T883 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.2845619137 |
|
|
Apr 23 12:24:06 PM PDT 24 |
Apr 23 12:26:49 PM PDT 24 |
1918698049 ps |
| T105 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1557394158 |
|
|
Apr 23 12:23:50 PM PDT 24 |
Apr 23 12:24:06 PM PDT 24 |
1107570468 ps |
| T884 |
/workspace/coverage/default/33.sram_ctrl_stress_all.1577190661 |
|
|
Apr 23 12:25:03 PM PDT 24 |
Apr 23 01:01:25 PM PDT 24 |
34910686388 ps |
| T885 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.750798969 |
|
|
Apr 23 12:24:35 PM PDT 24 |
Apr 23 12:24:42 PM PDT 24 |
929503979 ps |
| T886 |
/workspace/coverage/default/43.sram_ctrl_partial_access.1308167379 |
|
|
Apr 23 12:25:17 PM PDT 24 |
Apr 23 12:25:22 PM PDT 24 |
423752936 ps |
| T887 |
/workspace/coverage/default/24.sram_ctrl_mem_partial_access.388022291 |
|
|
Apr 23 12:24:36 PM PDT 24 |
Apr 23 12:24:41 PM PDT 24 |
341626780 ps |
| T888 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.3035399894 |
|
|
Apr 23 12:19:38 PM PDT 24 |
Apr 23 12:45:12 PM PDT 24 |
15829980664 ps |
| T889 |
/workspace/coverage/default/28.sram_ctrl_multiple_keys.2762076621 |
|
|
Apr 23 12:24:57 PM PDT 24 |
Apr 23 12:35:11 PM PDT 24 |
84905529899 ps |
| T890 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.380141743 |
|
|
Apr 23 12:23:14 PM PDT 24 |
Apr 23 12:23:20 PM PDT 24 |
157950426 ps |
| T891 |
/workspace/coverage/default/48.sram_ctrl_alert_test.907886326 |
|
|
Apr 23 12:25:32 PM PDT 24 |
Apr 23 12:25:34 PM PDT 24 |
13077736 ps |
| T892 |
/workspace/coverage/default/27.sram_ctrl_lc_escalation.3758262412 |
|
|
Apr 23 12:24:46 PM PDT 24 |
Apr 23 12:24:54 PM PDT 24 |
1922355665 ps |
| T893 |
/workspace/coverage/default/21.sram_ctrl_executable.3819439195 |
|
|
Apr 23 12:24:40 PM PDT 24 |
Apr 23 12:30:12 PM PDT 24 |
1365796015 ps |
| T894 |
/workspace/coverage/default/9.sram_ctrl_executable.2987470214 |
|
|
Apr 23 12:24:00 PM PDT 24 |
Apr 23 12:30:37 PM PDT 24 |
31612786555 ps |
| T895 |
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.2172797790 |
|
|
Apr 23 12:25:26 PM PDT 24 |
Apr 23 12:25:31 PM PDT 24 |
92150978 ps |
| T896 |
/workspace/coverage/default/20.sram_ctrl_smoke.626279653 |
|
|
Apr 23 12:24:38 PM PDT 24 |
Apr 23 12:24:46 PM PDT 24 |
304466177 ps |
| T897 |
/workspace/coverage/default/41.sram_ctrl_bijection.563526616 |
|
|
Apr 23 12:25:19 PM PDT 24 |
Apr 23 12:25:54 PM PDT 24 |
10885631838 ps |
| T898 |
/workspace/coverage/default/6.sram_ctrl_smoke.4130287623 |
|
|
Apr 23 12:23:25 PM PDT 24 |
Apr 23 12:24:14 PM PDT 24 |
149749161 ps |
| T899 |
/workspace/coverage/default/33.sram_ctrl_smoke.2836232558 |
|
|
Apr 23 12:25:08 PM PDT 24 |
Apr 23 12:25:20 PM PDT 24 |
453323905 ps |
| T900 |
/workspace/coverage/default/39.sram_ctrl_alert_test.392867244 |
|
|
Apr 23 12:25:08 PM PDT 24 |
Apr 23 12:25:13 PM PDT 24 |
22138454 ps |
| T901 |
/workspace/coverage/default/18.sram_ctrl_bijection.1014560208 |
|
|
Apr 23 12:24:35 PM PDT 24 |
Apr 23 12:25:41 PM PDT 24 |
4074708153 ps |
| T902 |
/workspace/coverage/default/5.sram_ctrl_alert_test.3244272440 |
|
|
Apr 23 12:23:27 PM PDT 24 |
Apr 23 12:23:28 PM PDT 24 |
21683257 ps |
| T903 |
/workspace/coverage/default/11.sram_ctrl_mem_walk.3624201165 |
|
|
Apr 23 12:24:11 PM PDT 24 |
Apr 23 12:24:19 PM PDT 24 |
295245119 ps |
| T904 |
/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.1993357683 |
|
|
Apr 23 12:24:48 PM PDT 24 |
Apr 23 12:24:58 PM PDT 24 |
154353229 ps |
| T905 |
/workspace/coverage/default/32.sram_ctrl_executable.3828403 |
|
|
Apr 23 12:24:55 PM PDT 24 |
Apr 23 12:40:38 PM PDT 24 |
15557757769 ps |
| T906 |
/workspace/coverage/default/30.sram_ctrl_bijection.3893363858 |
|
|
Apr 23 12:24:44 PM PDT 24 |
Apr 23 12:25:28 PM PDT 24 |
2923803155 ps |
| T907 |
/workspace/coverage/default/13.sram_ctrl_regwen.3111130372 |
|
|
Apr 23 12:24:04 PM PDT 24 |
Apr 23 12:33:35 PM PDT 24 |
2222697788 ps |
| T908 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.2512750123 |
|
|
Apr 23 12:24:55 PM PDT 24 |
Apr 23 12:25:15 PM PDT 24 |
152142304 ps |
| T909 |
/workspace/coverage/default/26.sram_ctrl_regwen.966049764 |
|
|
Apr 23 12:24:37 PM PDT 24 |
Apr 23 12:31:02 PM PDT 24 |
9022411645 ps |
| T910 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.3825607621 |
|
|
Apr 23 12:23:30 PM PDT 24 |
Apr 23 12:27:49 PM PDT 24 |
11840729696 ps |
| T911 |
/workspace/coverage/default/38.sram_ctrl_ram_cfg.3861752742 |
|
|
Apr 23 12:25:05 PM PDT 24 |
Apr 23 12:25:08 PM PDT 24 |
113980570 ps |
| T912 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.2645365531 |
|
|
Apr 23 12:25:06 PM PDT 24 |
Apr 23 12:25:18 PM PDT 24 |
2630837017 ps |
| T913 |
/workspace/coverage/default/46.sram_ctrl_mem_walk.3143908312 |
|
|
Apr 23 12:25:30 PM PDT 24 |
Apr 23 12:25:35 PM PDT 24 |
468386777 ps |
| T914 |
/workspace/coverage/default/41.sram_ctrl_mem_walk.1928219496 |
|
|
Apr 23 12:25:25 PM PDT 24 |
Apr 23 12:25:30 PM PDT 24 |
77927480 ps |
| T915 |
/workspace/coverage/default/19.sram_ctrl_smoke.2840005437 |
|
|
Apr 23 12:24:48 PM PDT 24 |
Apr 23 12:26:10 PM PDT 24 |
5512361451 ps |
| T916 |
/workspace/coverage/default/18.sram_ctrl_regwen.2332171431 |
|
|
Apr 23 12:24:37 PM PDT 24 |
Apr 23 12:33:08 PM PDT 24 |
20718963920 ps |
| T917 |
/workspace/coverage/default/21.sram_ctrl_mem_walk.980180104 |
|
|
Apr 23 12:24:37 PM PDT 24 |
Apr 23 12:24:43 PM PDT 24 |
78076609 ps |
| T918 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.308983064 |
|
|
Apr 23 12:23:25 PM PDT 24 |
Apr 23 12:27:03 PM PDT 24 |
39833328672 ps |
| T919 |
/workspace/coverage/default/29.sram_ctrl_regwen.2834334659 |
|
|
Apr 23 12:24:43 PM PDT 24 |
Apr 23 12:40:28 PM PDT 24 |
3197695137 ps |
| T920 |
/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.3676389936 |
|
|
Apr 23 12:24:29 PM PDT 24 |
Apr 23 12:25:05 PM PDT 24 |
214784751 ps |
| T921 |
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.3368063601 |
|
|
Apr 23 12:25:03 PM PDT 24 |
Apr 23 12:26:06 PM PDT 24 |
499416411 ps |
| T922 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.463778627 |
|
|
Apr 23 12:25:36 PM PDT 24 |
Apr 23 12:51:50 PM PDT 24 |
82981163923 ps |
| T923 |
/workspace/coverage/default/29.sram_ctrl_bijection.631614773 |
|
|
Apr 23 12:24:44 PM PDT 24 |
Apr 23 12:25:12 PM PDT 24 |
3313927493 ps |
| T924 |
/workspace/coverage/default/23.sram_ctrl_mem_walk.2538545963 |
|
|
Apr 23 12:24:35 PM PDT 24 |
Apr 23 12:24:48 PM PDT 24 |
2233326200 ps |
| T925 |
/workspace/coverage/default/19.sram_ctrl_alert_test.816413591 |
|
|
Apr 23 12:24:51 PM PDT 24 |
Apr 23 12:24:53 PM PDT 24 |
12656890 ps |
| T926 |
/workspace/coverage/default/47.sram_ctrl_smoke.468969975 |
|
|
Apr 23 12:25:29 PM PDT 24 |
Apr 23 12:25:54 PM PDT 24 |
1245795013 ps |
| T927 |
/workspace/coverage/default/32.sram_ctrl_access_during_key_req.1130133787 |
|
|
Apr 23 12:24:59 PM PDT 24 |
Apr 23 12:45:10 PM PDT 24 |
18382180787 ps |
| T928 |
/workspace/coverage/default/25.sram_ctrl_stress_pipeline.3277029686 |
|
|
Apr 23 12:24:37 PM PDT 24 |
Apr 23 12:29:02 PM PDT 24 |
11757195562 ps |
| T929 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.4049435922 |
|
|
Apr 23 12:25:25 PM PDT 24 |
Apr 23 12:25:37 PM PDT 24 |
871407860 ps |
| T930 |
/workspace/coverage/default/9.sram_ctrl_smoke.2049525873 |
|
|
Apr 23 12:23:55 PM PDT 24 |
Apr 23 12:24:51 PM PDT 24 |
1962002923 ps |
| T931 |
/workspace/coverage/default/9.sram_ctrl_alert_test.1107693072 |
|
|
Apr 23 12:24:16 PM PDT 24 |
Apr 23 12:24:17 PM PDT 24 |
35171801 ps |
| T932 |
/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3385154650 |
|
|
Apr 23 12:25:04 PM PDT 24 |
Apr 23 12:43:10 PM PDT 24 |
3200779585 ps |
| T933 |
/workspace/coverage/default/12.sram_ctrl_stress_all.1373088345 |
|
|
Apr 23 12:24:14 PM PDT 24 |
Apr 23 01:19:27 PM PDT 24 |
139066748662 ps |
| T934 |
/workspace/coverage/default/32.sram_ctrl_partial_access.1813613634 |
|
|
Apr 23 12:24:50 PM PDT 24 |
Apr 23 12:24:53 PM PDT 24 |
42682168 ps |
| T935 |
/workspace/coverage/default/37.sram_ctrl_ram_cfg.284200292 |
|
|
Apr 23 12:25:06 PM PDT 24 |
Apr 23 12:25:11 PM PDT 24 |
36818539 ps |
| T936 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.2917640937 |
|
|
Apr 23 12:25:38 PM PDT 24 |
Apr 23 12:31:38 PM PDT 24 |
3325957172 ps |
| T937 |
/workspace/coverage/default/34.sram_ctrl_lc_escalation.134307496 |
|
|
Apr 23 12:25:08 PM PDT 24 |
Apr 23 12:25:17 PM PDT 24 |
1172390860 ps |
| T938 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.1272645384 |
|
|
Apr 23 12:24:54 PM PDT 24 |
Apr 23 12:46:07 PM PDT 24 |
12311038111 ps |
| T939 |
/workspace/coverage/default/41.sram_ctrl_stress_all.2556259002 |
|
|
Apr 23 12:25:16 PM PDT 24 |
Apr 23 01:23:37 PM PDT 24 |
82508981632 ps |
| T940 |
/workspace/coverage/default/21.sram_ctrl_bijection.1597692406 |
|
|
Apr 23 12:24:27 PM PDT 24 |
Apr 23 12:24:54 PM PDT 24 |
1955750198 ps |
| T941 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.587833065 |
|
|
Apr 23 12:24:09 PM PDT 24 |
Apr 23 12:24:12 PM PDT 24 |
28098836 ps |
| T942 |
/workspace/coverage/default/26.sram_ctrl_multiple_keys.107747769 |
|
|
Apr 23 12:24:54 PM PDT 24 |
Apr 23 12:35:07 PM PDT 24 |
29604876887 ps |
| T943 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.1803494119 |
|
|
Apr 23 12:23:31 PM PDT 24 |
Apr 23 12:23:37 PM PDT 24 |
3743830368 ps |
| T944 |
/workspace/coverage/default/40.sram_ctrl_stress_all.2647556864 |
|
|
Apr 23 12:25:13 PM PDT 24 |
Apr 23 01:10:49 PM PDT 24 |
55590264448 ps |
| T945 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.198143921 |
|
|
Apr 23 12:25:01 PM PDT 24 |
Apr 23 12:25:03 PM PDT 24 |
43319203 ps |
| T946 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.79550647 |
|
|
Apr 23 12:24:09 PM PDT 24 |
Apr 23 12:28:56 PM PDT 24 |
3081986930 ps |
| T947 |
/workspace/coverage/default/37.sram_ctrl_bijection.1149739154 |
|
|
Apr 23 12:25:07 PM PDT 24 |
Apr 23 12:26:31 PM PDT 24 |
3645447661 ps |
| T948 |
/workspace/coverage/default/40.sram_ctrl_mem_walk.2305690561 |
|
|
Apr 23 12:25:11 PM PDT 24 |
Apr 23 12:25:25 PM PDT 24 |
1368724832 ps |
| T949 |
/workspace/coverage/default/46.sram_ctrl_smoke.3882961229 |
|
|
Apr 23 12:25:29 PM PDT 24 |
Apr 23 12:25:41 PM PDT 24 |
645035141 ps |
| T28 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.4067500452 |
|
|
Apr 23 12:24:29 PM PDT 24 |
Apr 23 12:24:32 PM PDT 24 |
138602758 ps |
| T950 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.2405708464 |
|
|
Apr 23 12:23:25 PM PDT 24 |
Apr 23 12:33:20 PM PDT 24 |
2932196288 ps |
| T53 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3820692769 |
|
|
Apr 23 12:23:57 PM PDT 24 |
Apr 23 12:24:00 PM PDT 24 |
16939163 ps |
| T115 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3910936849 |
|
|
Apr 23 12:23:42 PM PDT 24 |
Apr 23 12:23:47 PM PDT 24 |
812033206 ps |
| T96 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2727710194 |
|
|
Apr 23 12:23:29 PM PDT 24 |
Apr 23 12:23:32 PM PDT 24 |
247600729 ps |
| T951 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.398337032 |
|
|
Apr 23 12:22:48 PM PDT 24 |
Apr 23 12:22:50 PM PDT 24 |
116977506 ps |
| T99 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.4032481936 |
|
|
Apr 23 12:23:41 PM PDT 24 |
Apr 23 12:23:43 PM PDT 24 |
54612164 ps |
| T97 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1100710761 |
|
|
Apr 23 12:22:54 PM PDT 24 |
Apr 23 12:22:57 PM PDT 24 |
142470616 ps |
| T98 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.132123064 |
|
|
Apr 23 12:18:01 PM PDT 24 |
Apr 23 12:18:03 PM PDT 24 |
230119826 ps |
| T84 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.536930434 |
|
|
Apr 23 12:19:26 PM PDT 24 |
Apr 23 12:19:28 PM PDT 24 |
34410657 ps |
| T120 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2921887507 |
|
|
Apr 23 12:17:56 PM PDT 24 |
Apr 23 12:18:00 PM PDT 24 |
206580182 ps |
| T54 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.779657020 |
|
|
Apr 23 12:21:27 PM PDT 24 |
Apr 23 12:21:28 PM PDT 24 |
37427371 ps |
| T55 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.327651862 |
|
|
Apr 23 12:23:07 PM PDT 24 |
Apr 23 12:23:11 PM PDT 24 |
1526014953 ps |
| T56 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.501021885 |
|
|
Apr 23 12:18:01 PM PDT 24 |
Apr 23 12:18:03 PM PDT 24 |
14378426 ps |
| T952 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3157231919 |
|
|
Apr 23 12:18:49 PM PDT 24 |
Apr 23 12:18:51 PM PDT 24 |
34275268 ps |
| T93 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1423094899 |
|
|
Apr 23 12:17:56 PM PDT 24 |
Apr 23 12:17:58 PM PDT 24 |
13498697 ps |
| T121 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.347460523 |
|
|
Apr 23 12:18:45 PM PDT 24 |
Apr 23 12:18:47 PM PDT 24 |
96789220 ps |
| T123 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2794945595 |
|
|
Apr 23 12:24:09 PM PDT 24 |
Apr 23 12:24:14 PM PDT 24 |
341541000 ps |
| T953 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3472112309 |
|
|
Apr 23 12:24:09 PM PDT 24 |
Apr 23 12:24:14 PM PDT 24 |
190806451 ps |
| T57 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.618950596 |
|
|
Apr 23 12:21:17 PM PDT 24 |
Apr 23 12:21:18 PM PDT 24 |
34486654 ps |
| T94 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.275757497 |
|
|
Apr 23 12:23:21 PM PDT 24 |
Apr 23 12:23:24 PM PDT 24 |
26705214 ps |
| T58 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2025590460 |
|
|
Apr 23 12:20:43 PM PDT 24 |
Apr 23 12:20:44 PM PDT 24 |
36980558 ps |
| T954 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1164740477 |
|
|
Apr 23 12:23:24 PM PDT 24 |
Apr 23 12:23:26 PM PDT 24 |
135628959 ps |
| T955 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2774247888 |
|
|
Apr 23 12:23:20 PM PDT 24 |
Apr 23 12:23:22 PM PDT 24 |
56105603 ps |
| T59 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1538677143 |
|
|
Apr 23 12:23:28 PM PDT 24 |
Apr 23 12:23:32 PM PDT 24 |
433972955 ps |
| T95 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3261639227 |
|
|
Apr 23 12:24:04 PM PDT 24 |
Apr 23 12:24:06 PM PDT 24 |
15453374 ps |
| T60 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.962844652 |
|
|
Apr 23 12:21:57 PM PDT 24 |
Apr 23 12:22:00 PM PDT 24 |
460026894 ps |
| T61 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1631971337 |
|
|
Apr 23 12:19:33 PM PDT 24 |
Apr 23 12:19:35 PM PDT 24 |
1149245428 ps |
| T62 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2905806310 |
|
|
Apr 23 12:17:58 PM PDT 24 |
Apr 23 12:17:59 PM PDT 24 |
67285288 ps |
| T956 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.700411455 |
|
|
Apr 23 12:19:17 PM PDT 24 |
Apr 23 12:19:20 PM PDT 24 |
599498153 ps |
| T957 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3985946705 |
|
|
Apr 23 12:22:48 PM PDT 24 |
Apr 23 12:22:52 PM PDT 24 |
573372256 ps |
| T958 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3143341483 |
|
|
Apr 23 12:23:36 PM PDT 24 |
Apr 23 12:23:38 PM PDT 24 |
143422507 ps |
| T63 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2616774218 |
|
|
Apr 23 12:22:46 PM PDT 24 |
Apr 23 12:22:49 PM PDT 24 |
274801519 ps |
| T959 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1621906134 |
|
|
Apr 23 12:17:58 PM PDT 24 |
Apr 23 12:18:01 PM PDT 24 |
40194975 ps |
| T960 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1567188566 |
|
|
Apr 23 12:24:09 PM PDT 24 |
Apr 23 12:24:21 PM PDT 24 |
130730414 ps |
| T961 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.496910528 |
|
|
Apr 23 12:20:09 PM PDT 24 |
Apr 23 12:20:11 PM PDT 24 |
35551575 ps |
| T85 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2927731593 |
|
|
Apr 23 12:23:54 PM PDT 24 |
Apr 23 12:23:58 PM PDT 24 |
742822172 ps |
| T64 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2056487892 |
|
|
Apr 23 12:19:36 PM PDT 24 |
Apr 23 12:19:40 PM PDT 24 |
397855119 ps |
| T65 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.37809298 |
|
|
Apr 23 12:18:47 PM PDT 24 |
Apr 23 12:18:48 PM PDT 24 |
21466038 ps |
| T962 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1537735855 |
|
|
Apr 23 12:23:12 PM PDT 24 |
Apr 23 12:23:14 PM PDT 24 |
14554988 ps |
| T66 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3664182155 |
|
|
Apr 23 12:23:32 PM PDT 24 |
Apr 23 12:23:34 PM PDT 24 |
47424509 ps |
| T963 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.382711871 |
|
|
Apr 23 12:23:44 PM PDT 24 |
Apr 23 12:23:45 PM PDT 24 |
13153109 ps |
| T964 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1333793163 |
|
|
Apr 23 12:23:07 PM PDT 24 |
Apr 23 12:23:09 PM PDT 24 |
44761243 ps |
| T965 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1206140512 |
|
|
Apr 23 12:23:20 PM PDT 24 |
Apr 23 12:23:23 PM PDT 24 |
302561471 ps |
| T86 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1233835453 |
|
|
Apr 23 12:23:21 PM PDT 24 |
Apr 23 12:23:23 PM PDT 24 |
40367672 ps |
| T73 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3302753997 |
|
|
Apr 23 12:23:29 PM PDT 24 |
Apr 23 12:23:31 PM PDT 24 |
21051386 ps |
| T966 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3324880911 |
|
|
Apr 23 12:23:01 PM PDT 24 |
Apr 23 12:23:03 PM PDT 24 |
40510132 ps |
| T74 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1426781705 |
|
|
Apr 23 12:23:55 PM PDT 24 |
Apr 23 12:23:59 PM PDT 24 |
404209222 ps |
| T967 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.777905115 |
|
|
Apr 23 12:20:00 PM PDT 24 |
Apr 23 12:20:03 PM PDT 24 |
43077757 ps |
| T968 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3702025456 |
|
|
Apr 23 12:23:21 PM PDT 24 |
Apr 23 12:23:23 PM PDT 24 |
217369506 ps |
| T122 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3383573764 |
|
|
Apr 23 12:23:07 PM PDT 24 |
Apr 23 12:23:10 PM PDT 24 |
339929620 ps |
| T124 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2536460102 |
|
|
Apr 23 12:23:20 PM PDT 24 |
Apr 23 12:23:22 PM PDT 24 |
522653262 ps |
| T969 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.344561358 |
|
|
Apr 23 12:24:20 PM PDT 24 |
Apr 23 12:24:22 PM PDT 24 |
17902532 ps |
| T970 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3046535457 |
|
|
Apr 23 12:23:56 PM PDT 24 |
Apr 23 12:23:58 PM PDT 24 |
35129490 ps |
| T971 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1225415401 |
|
|
Apr 23 12:23:29 PM PDT 24 |
Apr 23 12:23:32 PM PDT 24 |
40472852 ps |
| T972 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1872847953 |
|
|
Apr 23 12:23:39 PM PDT 24 |
Apr 23 12:23:41 PM PDT 24 |
35240438 ps |
| T973 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1685374252 |
|
|
Apr 23 12:23:08 PM PDT 24 |
Apr 23 12:23:11 PM PDT 24 |
28706538 ps |
| T974 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1359888064 |
|
|
Apr 23 12:23:00 PM PDT 24 |
Apr 23 12:23:01 PM PDT 24 |
40291644 ps |
| T975 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1871297733 |
|
|
Apr 23 12:24:11 PM PDT 24 |
Apr 23 12:24:16 PM PDT 24 |
566826330 ps |
| T128 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3969978320 |
|
|
Apr 23 12:19:39 PM PDT 24 |
Apr 23 12:19:41 PM PDT 24 |
97623738 ps |
| T80 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3573306021 |
|
|
Apr 23 12:23:48 PM PDT 24 |
Apr 23 12:23:50 PM PDT 24 |
23681826 ps |
| T976 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3769664597 |
|
|
Apr 23 12:23:29 PM PDT 24 |
Apr 23 12:23:31 PM PDT 24 |
48778279 ps |
| T977 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3472654933 |
|
|
Apr 23 12:18:01 PM PDT 24 |
Apr 23 12:18:04 PM PDT 24 |
46897077 ps |
| T117 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1452946423 |
|
|
Apr 23 12:18:47 PM PDT 24 |
Apr 23 12:18:49 PM PDT 24 |
185294238 ps |
| T81 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2314661890 |
|
|
Apr 23 12:24:07 PM PDT 24 |
Apr 23 12:24:11 PM PDT 24 |
208228814 ps |
| T978 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1895020895 |
|
|
Apr 23 12:22:45 PM PDT 24 |
Apr 23 12:22:47 PM PDT 24 |
23572968 ps |
| T979 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2468197597 |
|
|
Apr 23 12:24:03 PM PDT 24 |
Apr 23 12:24:05 PM PDT 24 |
59712325 ps |
| T980 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3807216633 |
|
|
Apr 23 12:21:17 PM PDT 24 |
Apr 23 12:21:19 PM PDT 24 |
120491917 ps |
| T981 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.101374460 |
|
|
Apr 23 12:17:51 PM PDT 24 |
Apr 23 12:17:55 PM PDT 24 |
369338587 ps |
| T982 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2762137423 |
|
|
Apr 23 12:23:55 PM PDT 24 |
Apr 23 12:23:56 PM PDT 24 |
49464898 ps |
| T983 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.4208359247 |
|
|
Apr 23 12:23:55 PM PDT 24 |
Apr 23 12:23:59 PM PDT 24 |
180668542 ps |
| T984 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3905088641 |
|
|
Apr 23 12:18:01 PM PDT 24 |
Apr 23 12:18:03 PM PDT 24 |
18111599 ps |
| T118 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3208189440 |
|
|
Apr 23 12:23:41 PM PDT 24 |
Apr 23 12:23:45 PM PDT 24 |
166083342 ps |
| T985 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3064675063 |
|
|
Apr 23 12:23:31 PM PDT 24 |
Apr 23 12:23:40 PM PDT 24 |
1789754954 ps |
| T986 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2956449788 |
|
|
Apr 23 12:22:54 PM PDT 24 |
Apr 23 12:22:56 PM PDT 24 |
34609057 ps |
| T987 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2592943290 |
|
|
Apr 23 12:24:29 PM PDT 24 |
Apr 23 12:24:36 PM PDT 24 |
21320923 ps |
| T75 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.246051094 |
|
|
Apr 23 12:23:41 PM PDT 24 |
Apr 23 12:23:45 PM PDT 24 |
825460522 ps |
| T988 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3337607445 |
|
|
Apr 23 12:24:07 PM PDT 24 |
Apr 23 12:24:11 PM PDT 24 |
237863037 ps |
| T989 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1754524277 |
|
|
Apr 23 12:19:50 PM PDT 24 |
Apr 23 12:19:52 PM PDT 24 |
25797233 ps |
| T990 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3722154939 |
|
|
Apr 23 12:23:29 PM PDT 24 |
Apr 23 12:23:31 PM PDT 24 |
38921387 ps |
| T991 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.4147966384 |
|
|
Apr 23 12:23:30 PM PDT 24 |
Apr 23 12:23:32 PM PDT 24 |
221145888 ps |
| T992 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2688273337 |
|
|
Apr 23 12:20:11 PM PDT 24 |
Apr 23 12:20:14 PM PDT 24 |
36801289 ps |
| T82 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3015687551 |
|
|
Apr 23 12:24:00 PM PDT 24 |
Apr 23 12:24:02 PM PDT 24 |
51632453 ps |
| T993 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3671867779 |
|
|
Apr 23 12:18:01 PM PDT 24 |
Apr 23 12:18:05 PM PDT 24 |
105504655 ps |
| T83 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.255481641 |
|
|
Apr 23 12:19:17 PM PDT 24 |
Apr 23 12:19:20 PM PDT 24 |
726113884 ps |
| T125 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.322408751 |
|
|
Apr 23 12:24:08 PM PDT 24 |
Apr 23 12:24:13 PM PDT 24 |
1123019718 ps |
| T126 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.4248936641 |
|
|
Apr 23 12:24:00 PM PDT 24 |
Apr 23 12:24:03 PM PDT 24 |
308016832 ps |
| T994 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2187544 |
|
|
Apr 23 12:19:36 PM PDT 24 |
Apr 23 12:19:39 PM PDT 24 |
388859984 ps |
| T995 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3980438031 |
|
|
Apr 23 12:22:49 PM PDT 24 |
Apr 23 12:22:51 PM PDT 24 |
39829280 ps |
| T996 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1807963499 |
|
|
Apr 23 12:18:48 PM PDT 24 |
Apr 23 12:18:50 PM PDT 24 |
18774553 ps |
| T997 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1442363718 |
|
|
Apr 23 12:19:38 PM PDT 24 |
Apr 23 12:19:39 PM PDT 24 |
36806501 ps |
| T998 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3060413775 |
|
|
Apr 23 12:24:03 PM PDT 24 |
Apr 23 12:24:09 PM PDT 24 |
499238556 ps |
| T999 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3131176242 |
|
|
Apr 23 12:24:20 PM PDT 24 |
Apr 23 12:24:22 PM PDT 24 |
17639736 ps |
| T76 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.122246904 |
|
|
Apr 23 12:23:23 PM PDT 24 |
Apr 23 12:23:29 PM PDT 24 |
958492623 ps |
| T1000 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3696760734 |
|
|
Apr 23 12:23:56 PM PDT 24 |
Apr 23 12:23:58 PM PDT 24 |
23733407 ps |
| T1001 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.324967074 |
|
|
Apr 23 12:24:06 PM PDT 24 |
Apr 23 12:24:08 PM PDT 24 |
39308958 ps |
| T1002 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3412775292 |
|
|
Apr 23 12:21:40 PM PDT 24 |
Apr 23 12:21:43 PM PDT 24 |
168515827 ps |
| T1003 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2374727751 |
|
|
Apr 23 12:23:19 PM PDT 24 |
Apr 23 12:23:22 PM PDT 24 |
230787424 ps |
| T129 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3458715424 |
|
|
Apr 23 12:24:08 PM PDT 24 |
Apr 23 12:24:13 PM PDT 24 |
334820147 ps |
| T1004 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1060869105 |
|
|
Apr 23 12:22:05 PM PDT 24 |
Apr 23 12:22:07 PM PDT 24 |
59851219 ps |
| T1005 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.851442054 |
|
|
Apr 23 12:17:58 PM PDT 24 |
Apr 23 12:18:02 PM PDT 24 |
809380949 ps |