Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.08 99.81 96.99 100.00 100.00 98.57 99.70 98.52


Total test records in report: 1035
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T1006 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1010294832 Apr 23 12:23:41 PM PDT 24 Apr 23 12:23:43 PM PDT 24 26842300 ps
T1007 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2344501650 Apr 23 12:17:56 PM PDT 24 Apr 23 12:18:00 PM PDT 24 41188092 ps
T1008 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2754900592 Apr 23 12:22:13 PM PDT 24 Apr 23 12:22:14 PM PDT 24 18705757 ps
T1009 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2192304470 Apr 23 12:23:26 PM PDT 24 Apr 23 12:23:29 PM PDT 24 337118070 ps
T1010 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.4105870392 Apr 23 12:23:57 PM PDT 24 Apr 23 12:23:59 PM PDT 24 77540224 ps
T1011 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3814539530 Apr 23 12:23:10 PM PDT 24 Apr 23 12:23:15 PM PDT 24 129874651 ps
T1012 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.896286341 Apr 23 12:23:02 PM PDT 24 Apr 23 12:23:05 PM PDT 24 194982669 ps
T1013 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3219265337 Apr 23 12:23:20 PM PDT 24 Apr 23 12:23:22 PM PDT 24 28594809 ps
T1014 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2562483885 Apr 23 12:23:18 PM PDT 24 Apr 23 12:23:20 PM PDT 24 41412428 ps
T77 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2329404333 Apr 23 12:22:52 PM PDT 24 Apr 23 12:22:55 PM PDT 24 2494196179 ps
T1015 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1046505949 Apr 23 12:22:05 PM PDT 24 Apr 23 12:22:06 PM PDT 24 19284932 ps
T1016 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1486536754 Apr 23 12:23:10 PM PDT 24 Apr 23 12:23:12 PM PDT 24 31777395 ps
T1017 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.89542365 Apr 23 12:19:28 PM PDT 24 Apr 23 12:19:29 PM PDT 24 105362642 ps
T1018 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.690474797 Apr 23 12:23:56 PM PDT 24 Apr 23 12:24:00 PM PDT 24 144153728 ps
T1019 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.275314722 Apr 23 12:18:03 PM PDT 24 Apr 23 12:18:04 PM PDT 24 13334600 ps
T78 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1763189869 Apr 23 12:22:50 PM PDT 24 Apr 23 12:22:51 PM PDT 24 13694361 ps
T1020 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2697270716 Apr 23 12:23:55 PM PDT 24 Apr 23 12:23:58 PM PDT 24 142795072 ps
T1021 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1644957551 Apr 23 12:22:32 PM PDT 24 Apr 23 12:22:35 PM PDT 24 75631683 ps
T1022 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3710208552 Apr 23 12:24:06 PM PDT 24 Apr 23 12:24:09 PM PDT 24 782490234 ps
T1023 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3877225172 Apr 23 12:23:32 PM PDT 24 Apr 23 12:23:35 PM PDT 24 31083499 ps
T1024 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.4143680091 Apr 23 12:23:19 PM PDT 24 Apr 23 12:23:24 PM PDT 24 242223217 ps
T1025 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.147168519 Apr 23 12:22:32 PM PDT 24 Apr 23 12:22:35 PM PDT 24 48657440 ps
T119 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2901076044 Apr 23 12:23:21 PM PDT 24 Apr 23 12:23:24 PM PDT 24 600734554 ps
T1026 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1272480839 Apr 23 12:23:57 PM PDT 24 Apr 23 12:24:03 PM PDT 24 120640637 ps
T1027 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1688335948 Apr 23 12:24:12 PM PDT 24 Apr 23 12:24:17 PM PDT 24 142547403 ps
T127 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.4019509093 Apr 23 12:22:32 PM PDT 24 Apr 23 12:22:35 PM PDT 24 213362834 ps
T79 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1144427298 Apr 23 12:17:58 PM PDT 24 Apr 23 12:18:01 PM PDT 24 206755830 ps
T1028 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3084526248 Apr 23 12:23:49 PM PDT 24 Apr 23 12:23:54 PM PDT 24 71397064 ps
T1029 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3408368704 Apr 23 12:23:30 PM PDT 24 Apr 23 12:23:33 PM PDT 24 24895896 ps
T1030 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1036414350 Apr 23 12:18:47 PM PDT 24 Apr 23 12:18:48 PM PDT 24 13288831 ps
T1031 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1241735924 Apr 23 12:23:08 PM PDT 24 Apr 23 12:23:13 PM PDT 24 1554991376 ps
T1032 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1785514039 Apr 23 12:22:50 PM PDT 24 Apr 23 12:22:53 PM PDT 24 106527097 ps
T1033 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3753506395 Apr 23 12:24:15 PM PDT 24 Apr 23 12:24:19 PM PDT 24 110117153 ps
T1034 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3126807763 Apr 23 12:23:41 PM PDT 24 Apr 23 12:23:45 PM PDT 24 126012999 ps
T1035 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1296059997 Apr 23 12:23:57 PM PDT 24 Apr 23 12:23:59 PM PDT 24 150182387 ps

Test location /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.3670279619
Short name T3
Test name
Test status
Simulation time 1528535081 ps
CPU time 175.12 seconds
Started Apr 23 12:24:07 PM PDT 24
Finished Apr 23 12:27:04 PM PDT 24
Peak memory 376524 kb
Host smart-a883cdb8-d155-45d4-a53e-3cb71c0b9f63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3670279619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.3670279619
Directory /workspace/13.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_all.731509204
Short name T6
Test name
Test status
Simulation time 40658566827 ps
CPU time 1786.15 seconds
Started Apr 23 12:24:08 PM PDT 24
Finished Apr 23 12:53:56 PM PDT 24
Peak memory 374440 kb
Host smart-258e5299-a649-4cc9-8772-9d63fe57656b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731509204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 14.sram_ctrl_stress_all.731509204
Directory /workspace/14.sram_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2921887507
Short name T120
Test name
Test status
Simulation time 206580182 ps
CPU time 2.34 seconds
Started Apr 23 12:17:56 PM PDT 24
Finished Apr 23 12:18:00 PM PDT 24
Peak memory 199944 kb
Host smart-9a4e60a0-1d8a-49e0-9e31-f5ca1f50b2db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921887507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 1.sram_ctrl_tl_intg_err.2921887507
Directory /workspace/1.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_all.1156378025
Short name T5
Test name
Test status
Simulation time 22837317416 ps
CPU time 1829.52 seconds
Started Apr 23 12:23:56 PM PDT 24
Finished Apr 23 12:54:27 PM PDT 24
Peak memory 369932 kb
Host smart-b720e053-dda2-433e-bd5a-e9878ad8f71c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156378025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 10.sram_ctrl_stress_all.1156378025
Directory /workspace/10.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sram_ctrl_sec_cm.1500757361
Short name T15
Test name
Test status
Simulation time 250758872 ps
CPU time 1.7 seconds
Started Apr 23 12:24:29 PM PDT 24
Finished Apr 23 12:24:32 PM PDT 24
Peak memory 219896 kb
Host smart-0db428f7-504d-4dd5-bf5e-5dbba55ec0f1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500757361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_sec_cm.1500757361
Directory /workspace/3.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.3346053452
Short name T91
Test name
Test status
Simulation time 23678947595 ps
CPU time 514.3 seconds
Started Apr 23 12:25:09 PM PDT 24
Finished Apr 23 12:33:48 PM PDT 24
Peak memory 201880 kb
Host smart-1e2ddec0-76ff-4b55-9a64-cf97e79fb39b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346053452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 39.sram_ctrl_partial_access_b2b.3346053452
Directory /workspace/39.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/18.sram_ctrl_access_during_key_req.908471385
Short name T39
Test name
Test status
Simulation time 3203928715 ps
CPU time 1261.17 seconds
Started Apr 23 12:24:35 PM PDT 24
Finished Apr 23 12:45:38 PM PDT 24
Peak memory 372656 kb
Host smart-bc4a661d-579e-4ec1-acf2-a275f92a2d47
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908471385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 18.sram_ctrl_access_during_key_req.908471385
Directory /workspace/18.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3820692769
Short name T53
Test name
Test status
Simulation time 16939163 ps
CPU time 0.75 seconds
Started Apr 23 12:23:57 PM PDT 24
Finished Apr 23 12:24:00 PM PDT 24
Peak memory 200572 kb
Host smart-2c0d0858-b3c4-4d9b-b296-9cce9d814ea1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820692769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 12.sram_ctrl_csr_rw.3820692769
Directory /workspace/12.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3383573764
Short name T122
Test name
Test status
Simulation time 339929620 ps
CPU time 2.63 seconds
Started Apr 23 12:23:07 PM PDT 24
Finished Apr 23 12:23:10 PM PDT 24
Peak memory 202296 kb
Host smart-b1a8d1b0-3178-47fe-9c92-3441b593996c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383573764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 18.sram_ctrl_tl_intg_err.3383573764
Directory /workspace/18.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.sram_ctrl_ram_cfg.2095785585
Short name T25
Test name
Test status
Simulation time 50257068 ps
CPU time 0.76 seconds
Started Apr 23 12:24:18 PM PDT 24
Finished Apr 23 12:24:19 PM PDT 24
Peak memory 201940 kb
Host smart-1e36b454-c285-45b9-85dd-91f05dbc5c23
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095785585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.2095785585
Directory /workspace/14.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_all.1637726608
Short name T23
Test name
Test status
Simulation time 14425687043 ps
CPU time 2015.1 seconds
Started Apr 23 12:25:33 PM PDT 24
Finished Apr 23 12:59:09 PM PDT 24
Peak memory 373480 kb
Host smart-fb03e6a4-2585-4943-a4c7-c2a475275eb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637726608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 46.sram_ctrl_stress_all.1637726608
Directory /workspace/46.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.sram_ctrl_alert_test.1268994985
Short name T248
Test name
Test status
Simulation time 72642306 ps
CPU time 0.67 seconds
Started Apr 23 12:24:09 PM PDT 24
Finished Apr 23 12:24:12 PM PDT 24
Peak memory 200732 kb
Host smart-a04a9d82-5746-41b5-9ff7-f4e804d89b77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268994985 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.sram_ctrl_alert_test.1268994985
Directory /workspace/10.sram_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1426781705
Short name T74
Test name
Test status
Simulation time 404209222 ps
CPU time 3.2 seconds
Started Apr 23 12:23:55 PM PDT 24
Finished Apr 23 12:23:59 PM PDT 24
Peak memory 202136 kb
Host smart-c44d6cd6-7327-43f0-bb9f-649e914b576e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426781705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.1426781705
Directory /workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2901076044
Short name T119
Test name
Test status
Simulation time 600734554 ps
CPU time 2.16 seconds
Started Apr 23 12:23:21 PM PDT 24
Finished Apr 23 12:23:24 PM PDT 24
Peak memory 202112 kb
Host smart-0fe72c72-c52d-4fae-ae2b-68816afeb093
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901076044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 10.sram_ctrl_tl_intg_err.2901076044
Directory /workspace/10.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.sram_ctrl_regwen.1682827334
Short name T279
Test name
Test status
Simulation time 8986563176 ps
CPU time 366.53 seconds
Started Apr 23 12:24:08 PM PDT 24
Finished Apr 23 12:30:18 PM PDT 24
Peak memory 358632 kb
Host smart-f62ebdf1-fcab-401b-afa0-c790641780f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682827334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.1682827334
Directory /workspace/11.sram_ctrl_regwen/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3910936849
Short name T115
Test name
Test status
Simulation time 812033206 ps
CPU time 4.26 seconds
Started Apr 23 12:23:42 PM PDT 24
Finished Apr 23 12:23:47 PM PDT 24
Peak memory 201664 kb
Host smart-1cea1077-697c-4d16-9006-b16e99324d7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910936849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.sram_ctrl_tl_errors.3910936849
Directory /workspace/3.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1423094899
Short name T93
Test name
Test status
Simulation time 13498697 ps
CPU time 0.75 seconds
Started Apr 23 12:17:56 PM PDT 24
Finished Apr 23 12:17:58 PM PDT 24
Peak memory 199828 kb
Host smart-0da50b44-16b4-443a-87a8-1c5b239c3db3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423094899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_aliasing.1423094899
Directory /workspace/0.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.700411455
Short name T956
Test name
Test status
Simulation time 599498153 ps
CPU time 2.33 seconds
Started Apr 23 12:19:17 PM PDT 24
Finished Apr 23 12:19:20 PM PDT 24
Peak memory 202292 kb
Host smart-4c339d38-86b8-4ce5-94df-b6d2bf3026ec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700411455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.sram_ctrl_csr_bit_bash.700411455
Directory /workspace/0.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.37809298
Short name T65
Test name
Test status
Simulation time 21466038 ps
CPU time 0.67 seconds
Started Apr 23 12:18:47 PM PDT 24
Finished Apr 23 12:18:48 PM PDT 24
Peak memory 201944 kb
Host smart-e26bbc40-b033-4dbd-9226-854e8409c1d9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37809298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.sram_ctrl_csr_hw_reset.37809298
Directory /workspace/0.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1621906134
Short name T959
Test name
Test status
Simulation time 40194975 ps
CPU time 2.31 seconds
Started Apr 23 12:17:58 PM PDT 24
Finished Apr 23 12:18:01 PM PDT 24
Peak memory 209488 kb
Host smart-974e1125-d41e-42ae-b39a-ed5512a0b329
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621906134 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.1621906134
Directory /workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1036414350
Short name T1030
Test name
Test status
Simulation time 13288831 ps
CPU time 0.66 seconds
Started Apr 23 12:18:47 PM PDT 24
Finished Apr 23 12:18:48 PM PDT 24
Peak memory 201952 kb
Host smart-7510effc-800d-4ab4-bc3f-0b38838b89a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036414350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 0.sram_ctrl_csr_rw.1036414350
Directory /workspace/0.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.851442054
Short name T1005
Test name
Test status
Simulation time 809380949 ps
CPU time 3.12 seconds
Started Apr 23 12:17:58 PM PDT 24
Finished Apr 23 12:18:02 PM PDT 24
Peak memory 201708 kb
Host smart-f6a2966f-e902-4d80-b87e-494499235e07
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851442054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.851442054
Directory /workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3905088641
Short name T984
Test name
Test status
Simulation time 18111599 ps
CPU time 0.75 seconds
Started Apr 23 12:18:01 PM PDT 24
Finished Apr 23 12:18:03 PM PDT 24
Peak memory 199644 kb
Host smart-c8911304-399c-4303-a91e-c828e2cf6a42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905088641 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.3905088641
Directory /workspace/0.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.101374460
Short name T981
Test name
Test status
Simulation time 369338587 ps
CPU time 3.62 seconds
Started Apr 23 12:17:51 PM PDT 24
Finished Apr 23 12:17:55 PM PDT 24
Peak memory 201632 kb
Host smart-9170d059-da0c-4115-a0d7-2e872fc471e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101374460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_tl_errors.101374460
Directory /workspace/0.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.132123064
Short name T98
Test name
Test status
Simulation time 230119826 ps
CPU time 1.56 seconds
Started Apr 23 12:18:01 PM PDT 24
Finished Apr 23 12:18:03 PM PDT 24
Peak memory 199884 kb
Host smart-306782a4-1829-4c34-a0de-ad2098000d84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132123064 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 0.sram_ctrl_tl_intg_err.132123064
Directory /workspace/0.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.275314722
Short name T1019
Test name
Test status
Simulation time 13334600 ps
CPU time 0.67 seconds
Started Apr 23 12:18:03 PM PDT 24
Finished Apr 23 12:18:04 PM PDT 24
Peak memory 202000 kb
Host smart-df842655-4214-4a6a-9619-ce19eed89d3b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275314722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.sram_ctrl_csr_aliasing.275314722
Directory /workspace/1.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3472654933
Short name T977
Test name
Test status
Simulation time 46897077 ps
CPU time 1.79 seconds
Started Apr 23 12:18:01 PM PDT 24
Finished Apr 23 12:18:04 PM PDT 24
Peak memory 199864 kb
Host smart-cf0eeb23-8ff0-46e0-b6b6-d86862d9f2a3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472654933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_bit_bash.3472654933
Directory /workspace/1.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2905806310
Short name T62
Test name
Test status
Simulation time 67285288 ps
CPU time 0.71 seconds
Started Apr 23 12:17:58 PM PDT 24
Finished Apr 23 12:17:59 PM PDT 24
Peak memory 200180 kb
Host smart-d61292e9-806b-4623-a5ab-0ba38fa717af
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905806310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_hw_reset.2905806310
Directory /workspace/1.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2344501650
Short name T1007
Test name
Test status
Simulation time 41188092 ps
CPU time 2.26 seconds
Started Apr 23 12:17:56 PM PDT 24
Finished Apr 23 12:18:00 PM PDT 24
Peak memory 208696 kb
Host smart-91c82237-ddaf-4bd1-8d14-b88fd80cf7e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344501650 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.2344501650
Directory /workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.501021885
Short name T56
Test name
Test status
Simulation time 14378426 ps
CPU time 0.68 seconds
Started Apr 23 12:18:01 PM PDT 24
Finished Apr 23 12:18:03 PM PDT 24
Peak memory 200068 kb
Host smart-2119e1d4-79fe-4f67-80aa-c7fa89cd0bbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501021885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.sram_ctrl_csr_rw.501021885
Directory /workspace/1.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1144427298
Short name T79
Test name
Test status
Simulation time 206755830 ps
CPU time 1.88 seconds
Started Apr 23 12:17:58 PM PDT 24
Finished Apr 23 12:18:01 PM PDT 24
Peak memory 201240 kb
Host smart-8bf46199-8848-407d-9da7-63e196af77cc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144427298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.1144427298
Directory /workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.536930434
Short name T84
Test name
Test status
Simulation time 34410657 ps
CPU time 0.75 seconds
Started Apr 23 12:19:26 PM PDT 24
Finished Apr 23 12:19:28 PM PDT 24
Peak memory 202004 kb
Host smart-312a98b4-be83-4752-9f41-3308f90064fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536930434 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.536930434
Directory /workspace/1.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.4208359247
Short name T983
Test name
Test status
Simulation time 180668542 ps
CPU time 3.42 seconds
Started Apr 23 12:23:55 PM PDT 24
Finished Apr 23 12:23:59 PM PDT 24
Peak memory 201968 kb
Host smart-c6a986d1-d12b-4459-b22a-48c17d3cb2dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208359247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.sram_ctrl_tl_errors.4208359247
Directory /workspace/1.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1871297733
Short name T975
Test name
Test status
Simulation time 566826330 ps
CPU time 2.45 seconds
Started Apr 23 12:24:11 PM PDT 24
Finished Apr 23 12:24:16 PM PDT 24
Peak memory 210096 kb
Host smart-e0f7943c-77ec-4c0c-8d0a-0435dd92a9f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871297733 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.1871297733
Directory /workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2754900592
Short name T1008
Test name
Test status
Simulation time 18705757 ps
CPU time 0.67 seconds
Started Apr 23 12:22:13 PM PDT 24
Finished Apr 23 12:22:14 PM PDT 24
Peak memory 201432 kb
Host smart-78aaf972-8139-453b-b841-e8716aec7243
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754900592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 10.sram_ctrl_csr_rw.2754900592
Directory /workspace/10.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2374727751
Short name T1003
Test name
Test status
Simulation time 230787424 ps
CPU time 1.86 seconds
Started Apr 23 12:23:19 PM PDT 24
Finished Apr 23 12:23:22 PM PDT 24
Peak memory 201404 kb
Host smart-04a38e23-39de-4ed4-bbb7-2402fd43af46
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374727751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.2374727751
Directory /workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2562483885
Short name T1014
Test name
Test status
Simulation time 41412428 ps
CPU time 0.69 seconds
Started Apr 23 12:23:18 PM PDT 24
Finished Apr 23 12:23:20 PM PDT 24
Peak memory 200780 kb
Host smart-6139cdce-3393-4af3-a3f3-74870413379a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562483885 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.2562483885
Directory /workspace/10.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1688335948
Short name T1027
Test name
Test status
Simulation time 142547403 ps
CPU time 2.72 seconds
Started Apr 23 12:24:12 PM PDT 24
Finished Apr 23 12:24:17 PM PDT 24
Peak memory 202176 kb
Host smart-ab9f107e-d16a-4154-be94-1e44a2e3dce1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688335948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 10.sram_ctrl_tl_errors.1688335948
Directory /workspace/10.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2688273337
Short name T992
Test name
Test status
Simulation time 36801289 ps
CPU time 1.83 seconds
Started Apr 23 12:20:11 PM PDT 24
Finished Apr 23 12:20:14 PM PDT 24
Peak memory 210412 kb
Host smart-dcb856e0-602b-4e75-bd63-31074d488553
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688273337 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.2688273337
Directory /workspace/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3664182155
Short name T66
Test name
Test status
Simulation time 47424509 ps
CPU time 0.64 seconds
Started Apr 23 12:23:32 PM PDT 24
Finished Apr 23 12:23:34 PM PDT 24
Peak memory 200636 kb
Host smart-fe3ccd19-20f3-44a7-8457-d3674c0c0804
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664182155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 11.sram_ctrl_csr_rw.3664182155
Directory /workspace/11.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2192304470
Short name T1009
Test name
Test status
Simulation time 337118070 ps
CPU time 2.31 seconds
Started Apr 23 12:23:26 PM PDT 24
Finished Apr 23 12:23:29 PM PDT 24
Peak memory 201196 kb
Host smart-1976447f-cdd1-489a-ab5d-e4da6c4c35c8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192304470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.2192304470
Directory /workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1046505949
Short name T1015
Test name
Test status
Simulation time 19284932 ps
CPU time 0.68 seconds
Started Apr 23 12:22:05 PM PDT 24
Finished Apr 23 12:22:06 PM PDT 24
Peak memory 202152 kb
Host smart-dc9ecf79-c4d4-4e8f-ac00-417f9ff5a2b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046505949 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.1046505949
Directory /workspace/11.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3877225172
Short name T1023
Test name
Test status
Simulation time 31083499 ps
CPU time 1.6 seconds
Started Apr 23 12:23:32 PM PDT 24
Finished Apr 23 12:23:35 PM PDT 24
Peak memory 201956 kb
Host smart-19964612-efa1-4262-99fe-d03761a68f87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877225172 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 11.sram_ctrl_tl_errors.3877225172
Directory /workspace/11.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2794945595
Short name T123
Test name
Test status
Simulation time 341541000 ps
CPU time 2.35 seconds
Started Apr 23 12:24:09 PM PDT 24
Finished Apr 23 12:24:14 PM PDT 24
Peak memory 201332 kb
Host smart-5c8699cc-b556-48d7-84c3-d74752ce2f1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794945595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 11.sram_ctrl_tl_intg_err.2794945595
Directory /workspace/11.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.777905115
Short name T967
Test name
Test status
Simulation time 43077757 ps
CPU time 2.43 seconds
Started Apr 23 12:20:00 PM PDT 24
Finished Apr 23 12:20:03 PM PDT 24
Peak memory 211556 kb
Host smart-1791e50c-2b60-43d0-ab0a-c2c496e3719d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777905115 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.777905115
Directory /workspace/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1225415401
Short name T971
Test name
Test status
Simulation time 40472852 ps
CPU time 0.71 seconds
Started Apr 23 12:23:29 PM PDT 24
Finished Apr 23 12:23:32 PM PDT 24
Peak memory 200860 kb
Host smart-659a28e4-2a6c-4a0e-9f5c-b1bf020448b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225415401 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.1225415401
Directory /workspace/12.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1272480839
Short name T1026
Test name
Test status
Simulation time 120640637 ps
CPU time 3.86 seconds
Started Apr 23 12:23:57 PM PDT 24
Finished Apr 23 12:24:03 PM PDT 24
Peak memory 201028 kb
Host smart-5f5bf73b-6830-4ab8-a9f7-ed2a39268b18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272480839 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.sram_ctrl_tl_errors.1272480839
Directory /workspace/12.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2697270716
Short name T1020
Test name
Test status
Simulation time 142795072 ps
CPU time 1.59 seconds
Started Apr 23 12:23:55 PM PDT 24
Finished Apr 23 12:23:58 PM PDT 24
Peak memory 201988 kb
Host smart-97668244-b12e-4466-8391-6274fd8c6a9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697270716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 12.sram_ctrl_tl_intg_err.2697270716
Directory /workspace/12.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1754524277
Short name T989
Test name
Test status
Simulation time 25797233 ps
CPU time 0.9 seconds
Started Apr 23 12:19:50 PM PDT 24
Finished Apr 23 12:19:52 PM PDT 24
Peak memory 201916 kb
Host smart-87a9aea1-a143-4c93-a1fa-db09533ea579
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754524277 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.1754524277
Directory /workspace/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3131176242
Short name T999
Test name
Test status
Simulation time 17639736 ps
CPU time 0.69 seconds
Started Apr 23 12:24:20 PM PDT 24
Finished Apr 23 12:24:22 PM PDT 24
Peak memory 199640 kb
Host smart-71b4b686-8ff4-4cb1-a7d3-c7549f291738
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131176242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.sram_ctrl_csr_rw.3131176242
Directory /workspace/13.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3064675063
Short name T985
Test name
Test status
Simulation time 1789754954 ps
CPU time 7.29 seconds
Started Apr 23 12:23:31 PM PDT 24
Finished Apr 23 12:23:40 PM PDT 24
Peak memory 201608 kb
Host smart-fc0a26a5-654b-4385-9914-e2fa749b487a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064675063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.3064675063
Directory /workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.344561358
Short name T969
Test name
Test status
Simulation time 17902532 ps
CPU time 0.73 seconds
Started Apr 23 12:24:20 PM PDT 24
Finished Apr 23 12:24:22 PM PDT 24
Peak memory 200648 kb
Host smart-61475ddd-dcf3-4b20-8a90-16a23433c157
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344561358 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.344561358
Directory /workspace/13.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3753506395
Short name T1033
Test name
Test status
Simulation time 110117153 ps
CPU time 2.85 seconds
Started Apr 23 12:24:15 PM PDT 24
Finished Apr 23 12:24:19 PM PDT 24
Peak memory 201348 kb
Host smart-1d9a05a3-49de-418f-850e-7e5cd072e035
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753506395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.sram_ctrl_tl_errors.3753506395
Directory /workspace/13.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3969978320
Short name T128
Test name
Test status
Simulation time 97623738 ps
CPU time 1.53 seconds
Started Apr 23 12:19:39 PM PDT 24
Finished Apr 23 12:19:41 PM PDT 24
Peak memory 202204 kb
Host smart-59493836-45ac-4c76-945f-b7957aa99bf7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969978320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 13.sram_ctrl_tl_intg_err.3969978320
Directory /workspace/13.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.324967074
Short name T1001
Test name
Test status
Simulation time 39308958 ps
CPU time 1.18 seconds
Started Apr 23 12:24:06 PM PDT 24
Finished Apr 23 12:24:08 PM PDT 24
Peak memory 210220 kb
Host smart-b0e09738-f98b-436b-a818-d8db7d35c6ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324967074 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.324967074
Directory /workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1644957551
Short name T1021
Test name
Test status
Simulation time 75631683 ps
CPU time 0.66 seconds
Started Apr 23 12:22:32 PM PDT 24
Finished Apr 23 12:22:35 PM PDT 24
Peak memory 200556 kb
Host smart-ab8f8dc4-fd03-4d73-9a0f-989258ab0aa6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644957551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 14.sram_ctrl_csr_rw.1644957551
Directory /workspace/14.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3710208552
Short name T1022
Test name
Test status
Simulation time 782490234 ps
CPU time 2.04 seconds
Started Apr 23 12:24:06 PM PDT 24
Finished Apr 23 12:24:09 PM PDT 24
Peak memory 202152 kb
Host smart-b5492e4b-4a11-4d36-af06-9e8705bc4d14
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710208552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.3710208552
Directory /workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.147168519
Short name T1025
Test name
Test status
Simulation time 48657440 ps
CPU time 0.67 seconds
Started Apr 23 12:22:32 PM PDT 24
Finished Apr 23 12:22:35 PM PDT 24
Peak memory 200628 kb
Host smart-c8412f2f-0972-40bc-9025-c36dd523a96d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147168519 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.147168519
Directory /workspace/14.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3084526248
Short name T1028
Test name
Test status
Simulation time 71397064 ps
CPU time 3.52 seconds
Started Apr 23 12:23:49 PM PDT 24
Finished Apr 23 12:23:54 PM PDT 24
Peak memory 201404 kb
Host smart-f7ee3f93-0559-4de7-93e5-bdcd58a6431a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084526248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 14.sram_ctrl_tl_errors.3084526248
Directory /workspace/14.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.4019509093
Short name T127
Test name
Test status
Simulation time 213362834 ps
CPU time 2.24 seconds
Started Apr 23 12:22:32 PM PDT 24
Finished Apr 23 12:22:35 PM PDT 24
Peak memory 201884 kb
Host smart-b8dd0633-e543-4d0b-baed-e65ae5877a81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019509093 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 14.sram_ctrl_tl_intg_err.4019509093
Directory /workspace/14.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.398337032
Short name T951
Test name
Test status
Simulation time 116977506 ps
CPU time 1.81 seconds
Started Apr 23 12:22:48 PM PDT 24
Finished Apr 23 12:22:50 PM PDT 24
Peak memory 210576 kb
Host smart-3f0016db-0a79-468f-af41-c8ab00b65073
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398337032 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.398337032
Directory /workspace/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3015687551
Short name T82
Test name
Test status
Simulation time 51632453 ps
CPU time 0.69 seconds
Started Apr 23 12:24:00 PM PDT 24
Finished Apr 23 12:24:02 PM PDT 24
Peak memory 200628 kb
Host smart-36dd539c-5343-4f8f-9437-c2db9d4abd8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015687551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 15.sram_ctrl_csr_rw.3015687551
Directory /workspace/15.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1631971337
Short name T61
Test name
Test status
Simulation time 1149245428 ps
CPU time 1.96 seconds
Started Apr 23 12:19:33 PM PDT 24
Finished Apr 23 12:19:35 PM PDT 24
Peak memory 202156 kb
Host smart-05e5bab6-103f-428d-9855-07993e853099
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631971337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.1631971337
Directory /workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1895020895
Short name T978
Test name
Test status
Simulation time 23572968 ps
CPU time 0.74 seconds
Started Apr 23 12:22:45 PM PDT 24
Finished Apr 23 12:22:47 PM PDT 24
Peak memory 201920 kb
Host smart-abfbbabf-4053-43ed-b951-fcdb52a16232
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895020895 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.1895020895
Directory /workspace/15.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3472112309
Short name T953
Test name
Test status
Simulation time 190806451 ps
CPU time 1.93 seconds
Started Apr 23 12:24:09 PM PDT 24
Finished Apr 23 12:24:14 PM PDT 24
Peak memory 201808 kb
Host smart-e19609fc-ea47-427a-9cfc-d39bdf570bb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472112309 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.sram_ctrl_tl_errors.3472112309
Directory /workspace/15.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3458715424
Short name T129
Test name
Test status
Simulation time 334820147 ps
CPU time 2.11 seconds
Started Apr 23 12:24:08 PM PDT 24
Finished Apr 23 12:24:13 PM PDT 24
Peak memory 201092 kb
Host smart-cced5158-744b-49c3-a545-787d3da5100e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458715424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 15.sram_ctrl_tl_intg_err.3458715424
Directory /workspace/15.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1763189869
Short name T78
Test name
Test status
Simulation time 13694361 ps
CPU time 0.64 seconds
Started Apr 23 12:22:50 PM PDT 24
Finished Apr 23 12:22:51 PM PDT 24
Peak memory 202016 kb
Host smart-fdacd05c-6362-447f-8e53-1d7df535a153
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763189869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 16.sram_ctrl_csr_rw.1763189869
Directory /workspace/16.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2616774218
Short name T63
Test name
Test status
Simulation time 274801519 ps
CPU time 1.98 seconds
Started Apr 23 12:22:46 PM PDT 24
Finished Apr 23 12:22:49 PM PDT 24
Peak memory 202152 kb
Host smart-e806be78-f6ca-4d2b-a9fb-b588c4b1c492
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616774218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.2616774218
Directory /workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3980438031
Short name T995
Test name
Test status
Simulation time 39829280 ps
CPU time 0.73 seconds
Started Apr 23 12:22:49 PM PDT 24
Finished Apr 23 12:22:51 PM PDT 24
Peak memory 202152 kb
Host smart-c59f8502-7fd8-410d-95b5-af71b23a5c6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980438031 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.3980438031
Directory /workspace/16.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3985946705
Short name T957
Test name
Test status
Simulation time 573372256 ps
CPU time 2.71 seconds
Started Apr 23 12:22:48 PM PDT 24
Finished Apr 23 12:22:52 PM PDT 24
Peak memory 202144 kb
Host smart-a7a86028-2064-4fab-82ac-b7170cd98b55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985946705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.sram_ctrl_tl_errors.3985946705
Directory /workspace/16.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.4248936641
Short name T126
Test name
Test status
Simulation time 308016832 ps
CPU time 1.55 seconds
Started Apr 23 12:24:00 PM PDT 24
Finished Apr 23 12:24:03 PM PDT 24
Peak memory 201012 kb
Host smart-41145e58-7d8b-40ce-8495-49d4f530188c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248936641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 16.sram_ctrl_tl_intg_err.4248936641
Directory /workspace/16.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3324880911
Short name T966
Test name
Test status
Simulation time 40510132 ps
CPU time 1.95 seconds
Started Apr 23 12:23:01 PM PDT 24
Finished Apr 23 12:23:03 PM PDT 24
Peak memory 210332 kb
Host smart-6505ee61-7e58-4c1e-afc0-f4296a397543
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324880911 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.3324880911
Directory /workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2956449788
Short name T986
Test name
Test status
Simulation time 34609057 ps
CPU time 0.66 seconds
Started Apr 23 12:22:54 PM PDT 24
Finished Apr 23 12:22:56 PM PDT 24
Peak memory 201356 kb
Host smart-6fe45d98-380c-4866-8c6f-f6fcd8c628c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956449788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 17.sram_ctrl_csr_rw.2956449788
Directory /workspace/17.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2329404333
Short name T77
Test name
Test status
Simulation time 2494196179 ps
CPU time 2.3 seconds
Started Apr 23 12:22:52 PM PDT 24
Finished Apr 23 12:22:55 PM PDT 24
Peak memory 202320 kb
Host smart-d080c841-6d27-43f1-973b-0d5102d90166
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329404333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.2329404333
Directory /workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1359888064
Short name T974
Test name
Test status
Simulation time 40291644 ps
CPU time 0.73 seconds
Started Apr 23 12:23:00 PM PDT 24
Finished Apr 23 12:23:01 PM PDT 24
Peak memory 201940 kb
Host smart-dbef2d12-5560-4a3d-948b-40dd7d4df1dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359888064 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.1359888064
Directory /workspace/17.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1785514039
Short name T1032
Test name
Test status
Simulation time 106527097 ps
CPU time 3.2 seconds
Started Apr 23 12:22:50 PM PDT 24
Finished Apr 23 12:22:53 PM PDT 24
Peak memory 202176 kb
Host smart-02fea886-8efc-4471-942c-093c44ef5106
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785514039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.sram_ctrl_tl_errors.1785514039
Directory /workspace/17.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1100710761
Short name T97
Test name
Test status
Simulation time 142470616 ps
CPU time 1.41 seconds
Started Apr 23 12:22:54 PM PDT 24
Finished Apr 23 12:22:57 PM PDT 24
Peak memory 202212 kb
Host smart-f9fe80a0-b549-4a63-96d7-b4d90e5d62b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100710761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 17.sram_ctrl_tl_intg_err.1100710761
Directory /workspace/17.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1685374252
Short name T973
Test name
Test status
Simulation time 28706538 ps
CPU time 1.1 seconds
Started Apr 23 12:23:08 PM PDT 24
Finished Apr 23 12:23:11 PM PDT 24
Peak memory 210204 kb
Host smart-6a9d3976-7996-4f4d-85c3-c6dcb82d88a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685374252 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.1685374252
Directory /workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1333793163
Short name T964
Test name
Test status
Simulation time 44761243 ps
CPU time 0.71 seconds
Started Apr 23 12:23:07 PM PDT 24
Finished Apr 23 12:23:09 PM PDT 24
Peak memory 201956 kb
Host smart-fb4b9a7f-df55-443b-8b6e-da16f03844e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333793163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 18.sram_ctrl_csr_rw.1333793163
Directory /workspace/18.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.327651862
Short name T55
Test name
Test status
Simulation time 1526014953 ps
CPU time 3.21 seconds
Started Apr 23 12:23:07 PM PDT 24
Finished Apr 23 12:23:11 PM PDT 24
Peak memory 202492 kb
Host smart-07404d39-b66e-47bd-9445-783e43e9f038
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327651862 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.327651862
Directory /workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1486536754
Short name T1016
Test name
Test status
Simulation time 31777395 ps
CPU time 0.77 seconds
Started Apr 23 12:23:10 PM PDT 24
Finished Apr 23 12:23:12 PM PDT 24
Peak memory 202140 kb
Host smart-5ac70034-90e0-4bfa-974d-ffc19ac8f999
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486536754 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.1486536754
Directory /workspace/18.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.896286341
Short name T1012
Test name
Test status
Simulation time 194982669 ps
CPU time 2.43 seconds
Started Apr 23 12:23:02 PM PDT 24
Finished Apr 23 12:23:05 PM PDT 24
Peak memory 202204 kb
Host smart-142d8a06-12c6-45bc-976f-1b97c9d8e189
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896286341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
18.sram_ctrl_tl_errors.896286341
Directory /workspace/18.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3702025456
Short name T968
Test name
Test status
Simulation time 217369506 ps
CPU time 1.16 seconds
Started Apr 23 12:23:21 PM PDT 24
Finished Apr 23 12:23:23 PM PDT 24
Peak memory 210188 kb
Host smart-dcf3730d-af30-46e2-8c14-6c12b8516692
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702025456 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.3702025456
Directory /workspace/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1537735855
Short name T962
Test name
Test status
Simulation time 14554988 ps
CPU time 0.67 seconds
Started Apr 23 12:23:12 PM PDT 24
Finished Apr 23 12:23:14 PM PDT 24
Peak memory 202008 kb
Host smart-0d7eb448-b378-4067-aad8-88b2782a43ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537735855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 19.sram_ctrl_csr_rw.1537735855
Directory /workspace/19.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1241735924
Short name T1031
Test name
Test status
Simulation time 1554991376 ps
CPU time 3.55 seconds
Started Apr 23 12:23:08 PM PDT 24
Finished Apr 23 12:23:13 PM PDT 24
Peak memory 202372 kb
Host smart-1a59f82e-39da-4d2a-bc61-3cb9072b33e2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241735924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.1241735924
Directory /workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2592943290
Short name T987
Test name
Test status
Simulation time 21320923 ps
CPU time 0.69 seconds
Started Apr 23 12:24:29 PM PDT 24
Finished Apr 23 12:24:36 PM PDT 24
Peak memory 200908 kb
Host smart-7575aa2b-2d1e-495a-9849-f2a3b3996ac2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592943290 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.2592943290
Directory /workspace/19.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3814539530
Short name T1011
Test name
Test status
Simulation time 129874651 ps
CPU time 4.08 seconds
Started Apr 23 12:23:10 PM PDT 24
Finished Apr 23 12:23:15 PM PDT 24
Peak memory 202380 kb
Host smart-3dc25ade-5281-4811-b3e7-c5c01651034d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814539530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 19.sram_ctrl_tl_errors.3814539530
Directory /workspace/19.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2536460102
Short name T124
Test name
Test status
Simulation time 522653262 ps
CPU time 2.13 seconds
Started Apr 23 12:23:20 PM PDT 24
Finished Apr 23 12:23:22 PM PDT 24
Peak memory 202248 kb
Host smart-6828e0f3-7f5d-4d4c-87d4-387b5bae34db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536460102 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 19.sram_ctrl_tl_intg_err.2536460102
Directory /workspace/19.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.382711871
Short name T963
Test name
Test status
Simulation time 13153109 ps
CPU time 0.72 seconds
Started Apr 23 12:23:44 PM PDT 24
Finished Apr 23 12:23:45 PM PDT 24
Peak memory 201160 kb
Host smart-20ed5d5e-b23b-427e-9f60-5b90602a3369
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382711871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.sram_ctrl_csr_aliasing.382711871
Directory /workspace/2.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.4147966384
Short name T991
Test name
Test status
Simulation time 221145888 ps
CPU time 1.28 seconds
Started Apr 23 12:23:30 PM PDT 24
Finished Apr 23 12:23:32 PM PDT 24
Peak memory 201884 kb
Host smart-965539d7-7e2c-4c39-9bda-65fe927d7e7a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147966384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_bit_bash.4147966384
Directory /workspace/2.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.779657020
Short name T54
Test name
Test status
Simulation time 37427371 ps
CPU time 0.67 seconds
Started Apr 23 12:21:27 PM PDT 24
Finished Apr 23 12:21:28 PM PDT 24
Peak memory 202052 kb
Host smart-e5f91648-b966-4e43-8743-0c0088a4fe50
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779657020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.sram_ctrl_csr_hw_reset.779657020
Directory /workspace/2.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1060869105
Short name T1004
Test name
Test status
Simulation time 59851219 ps
CPU time 1.09 seconds
Started Apr 23 12:22:05 PM PDT 24
Finished Apr 23 12:22:07 PM PDT 24
Peak memory 210152 kb
Host smart-a7abad12-ea97-40ac-9170-d2e32d76ceed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060869105 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.1060869105
Directory /workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1010294832
Short name T1006
Test name
Test status
Simulation time 26842300 ps
CPU time 0.73 seconds
Started Apr 23 12:23:41 PM PDT 24
Finished Apr 23 12:23:43 PM PDT 24
Peak memory 200136 kb
Host smart-fcb4fef3-f53d-45be-ae76-e6bd8be0609c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010294832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 2.sram_ctrl_csr_rw.1010294832
Directory /workspace/2.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.255481641
Short name T83
Test name
Test status
Simulation time 726113884 ps
CPU time 2.88 seconds
Started Apr 23 12:19:17 PM PDT 24
Finished Apr 23 12:19:20 PM PDT 24
Peak memory 202492 kb
Host smart-d2681807-e3f8-4ea4-b74f-e18b495b7b9b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255481641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.255481641
Directory /workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3696760734
Short name T1000
Test name
Test status
Simulation time 23733407 ps
CPU time 0.7 seconds
Started Apr 23 12:23:56 PM PDT 24
Finished Apr 23 12:23:58 PM PDT 24
Peak memory 201840 kb
Host smart-4a75c0cf-c75b-42c2-bf16-aede6be53169
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696760734 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.3696760734
Directory /workspace/2.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3671867779
Short name T993
Test name
Test status
Simulation time 105504655 ps
CPU time 2.73 seconds
Started Apr 23 12:18:01 PM PDT 24
Finished Apr 23 12:18:05 PM PDT 24
Peak memory 208732 kb
Host smart-f4f7f589-3add-45e9-8a07-21fbb1e9357c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671867779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.sram_ctrl_tl_errors.3671867779
Directory /workspace/2.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.322408751
Short name T125
Test name
Test status
Simulation time 1123019718 ps
CPU time 2.17 seconds
Started Apr 23 12:24:08 PM PDT 24
Finished Apr 23 12:24:13 PM PDT 24
Peak memory 201304 kb
Host smart-a53d734a-3293-449c-9a96-d0ce6a86525d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322408751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 2.sram_ctrl_tl_intg_err.322408751
Directory /workspace/2.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2025590460
Short name T58
Test name
Test status
Simulation time 36980558 ps
CPU time 0.65 seconds
Started Apr 23 12:20:43 PM PDT 24
Finished Apr 23 12:20:44 PM PDT 24
Peak memory 201924 kb
Host smart-64624ecd-9b05-4479-a2c4-71af482b65a1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025590460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_aliasing.2025590460
Directory /workspace/3.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3807216633
Short name T980
Test name
Test status
Simulation time 120491917 ps
CPU time 2.15 seconds
Started Apr 23 12:21:17 PM PDT 24
Finished Apr 23 12:21:19 PM PDT 24
Peak memory 202148 kb
Host smart-22023d1f-2f6e-4320-b6e9-f81f4fb867bf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807216633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_bit_bash.3807216633
Directory /workspace/3.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.89542365
Short name T1017
Test name
Test status
Simulation time 105362642 ps
CPU time 0.67 seconds
Started Apr 23 12:19:28 PM PDT 24
Finished Apr 23 12:19:29 PM PDT 24
Peak memory 201996 kb
Host smart-57781108-a5af-4e5e-9213-4ee774472ed8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89542365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.sram_ctrl_csr_hw_reset.89542365
Directory /workspace/3.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3157231919
Short name T952
Test name
Test status
Simulation time 34275268 ps
CPU time 1.12 seconds
Started Apr 23 12:18:49 PM PDT 24
Finished Apr 23 12:18:51 PM PDT 24
Peak memory 210160 kb
Host smart-376ad5fb-178c-4f9f-964a-b6ae1595e521
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157231919 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.3157231919
Directory /workspace/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.618950596
Short name T57
Test name
Test status
Simulation time 34486654 ps
CPU time 0.66 seconds
Started Apr 23 12:21:17 PM PDT 24
Finished Apr 23 12:21:18 PM PDT 24
Peak memory 201836 kb
Host smart-19f6ae4a-6b43-4e7d-bc27-4207f4b34220
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618950596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.sram_ctrl_csr_rw.618950596
Directory /workspace/3.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2056487892
Short name T64
Test name
Test status
Simulation time 397855119 ps
CPU time 3.24 seconds
Started Apr 23 12:19:36 PM PDT 24
Finished Apr 23 12:19:40 PM PDT 24
Peak memory 202360 kb
Host smart-68d08b78-4c21-4472-a85f-954759582950
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056487892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.2056487892
Directory /workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2762137423
Short name T982
Test name
Test status
Simulation time 49464898 ps
CPU time 0.66 seconds
Started Apr 23 12:23:55 PM PDT 24
Finished Apr 23 12:23:56 PM PDT 24
Peak memory 201676 kb
Host smart-ca82abef-38ad-4859-9649-9a12507dc557
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762137423 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.2762137423
Directory /workspace/3.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2727710194
Short name T96
Test name
Test status
Simulation time 247600729 ps
CPU time 1.35 seconds
Started Apr 23 12:23:29 PM PDT 24
Finished Apr 23 12:23:32 PM PDT 24
Peak memory 201048 kb
Host smart-2230b602-64af-4415-a09b-ed291d3f6fd4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727710194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 3.sram_ctrl_tl_intg_err.2727710194
Directory /workspace/3.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3302753997
Short name T73
Test name
Test status
Simulation time 21051386 ps
CPU time 0.65 seconds
Started Apr 23 12:23:29 PM PDT 24
Finished Apr 23 12:23:31 PM PDT 24
Peak memory 201596 kb
Host smart-f80ee31f-06e4-482f-8c1e-f7f12f624111
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302753997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_aliasing.3302753997
Directory /workspace/4.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3126807763
Short name T1034
Test name
Test status
Simulation time 126012999 ps
CPU time 2.2 seconds
Started Apr 23 12:23:41 PM PDT 24
Finished Apr 23 12:23:45 PM PDT 24
Peak memory 200056 kb
Host smart-059c1033-7774-48e5-b263-5ecad5bf81ec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126807763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_bit_bash.3126807763
Directory /workspace/4.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.4032481936
Short name T99
Test name
Test status
Simulation time 54612164 ps
CPU time 0.74 seconds
Started Apr 23 12:23:41 PM PDT 24
Finished Apr 23 12:23:43 PM PDT 24
Peak memory 199792 kb
Host smart-737ba50d-3113-4a44-a80a-d8b33c4ad0a7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032481936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_hw_reset.4032481936
Directory /workspace/4.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3046535457
Short name T970
Test name
Test status
Simulation time 35129490 ps
CPU time 0.98 seconds
Started Apr 23 12:23:56 PM PDT 24
Finished Apr 23 12:23:58 PM PDT 24
Peak memory 201772 kb
Host smart-917eba8e-b351-4efb-a7fa-a111ff69224f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046535457 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.3046535457
Directory /workspace/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3722154939
Short name T990
Test name
Test status
Simulation time 38921387 ps
CPU time 0.64 seconds
Started Apr 23 12:23:29 PM PDT 24
Finished Apr 23 12:23:31 PM PDT 24
Peak memory 201440 kb
Host smart-f97d4135-99a0-42e0-863f-75d9ac865096
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722154939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 4.sram_ctrl_csr_rw.3722154939
Directory /workspace/4.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.246051094
Short name T75
Test name
Test status
Simulation time 825460522 ps
CPU time 2.93 seconds
Started Apr 23 12:23:41 PM PDT 24
Finished Apr 23 12:23:45 PM PDT 24
Peak memory 200276 kb
Host smart-7ec0dcfc-d351-496a-99d3-a963903639ce
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246051094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.246051094
Directory /workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3769664597
Short name T976
Test name
Test status
Simulation time 48778279 ps
CPU time 0.7 seconds
Started Apr 23 12:23:29 PM PDT 24
Finished Apr 23 12:23:31 PM PDT 24
Peak memory 200716 kb
Host smart-d49f9555-60b1-48bb-8f99-fb476329c8d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769664597 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.3769664597
Directory /workspace/4.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3408368704
Short name T1029
Test name
Test status
Simulation time 24895896 ps
CPU time 2.17 seconds
Started Apr 23 12:23:30 PM PDT 24
Finished Apr 23 12:23:33 PM PDT 24
Peak memory 201956 kb
Host smart-87fb353d-4716-499c-ba0c-a41af1e2e3cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408368704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.sram_ctrl_tl_errors.3408368704
Directory /workspace/4.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3208189440
Short name T118
Test name
Test status
Simulation time 166083342 ps
CPU time 2.07 seconds
Started Apr 23 12:23:41 PM PDT 24
Finished Apr 23 12:23:45 PM PDT 24
Peak memory 200764 kb
Host smart-7478952d-5070-4350-9027-b730401d3680
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208189440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 4.sram_ctrl_tl_intg_err.3208189440
Directory /workspace/4.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3143341483
Short name T958
Test name
Test status
Simulation time 143422507 ps
CPU time 1.22 seconds
Started Apr 23 12:23:36 PM PDT 24
Finished Apr 23 12:23:38 PM PDT 24
Peak memory 211056 kb
Host smart-c75e1b5d-024b-493e-995b-d936159d3adc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143341483 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.3143341483
Directory /workspace/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3573306021
Short name T80
Test name
Test status
Simulation time 23681826 ps
CPU time 0.76 seconds
Started Apr 23 12:23:48 PM PDT 24
Finished Apr 23 12:23:50 PM PDT 24
Peak memory 201024 kb
Host smart-fa54ab54-c7df-4c7e-bb30-d18a2a4a2f89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573306021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 5.sram_ctrl_csr_rw.3573306021
Directory /workspace/5.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2314661890
Short name T81
Test name
Test status
Simulation time 208228814 ps
CPU time 1.92 seconds
Started Apr 23 12:24:07 PM PDT 24
Finished Apr 23 12:24:11 PM PDT 24
Peak memory 202172 kb
Host smart-9d14089f-32a6-453c-944c-5b46b9d1116e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314661890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.2314661890
Directory /workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.4105870392
Short name T1010
Test name
Test status
Simulation time 77540224 ps
CPU time 0.75 seconds
Started Apr 23 12:23:57 PM PDT 24
Finished Apr 23 12:23:59 PM PDT 24
Peak memory 201900 kb
Host smart-9e684ca7-0fb0-4959-96d8-8c345c9100a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105870392 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.4105870392
Directory /workspace/5.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3337607445
Short name T988
Test name
Test status
Simulation time 237863037 ps
CPU time 2.13 seconds
Started Apr 23 12:24:07 PM PDT 24
Finished Apr 23 12:24:11 PM PDT 24
Peak memory 202204 kb
Host smart-c7d2bcaa-bb7e-46bf-b18a-29f29466e2ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337607445 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 5.sram_ctrl_tl_errors.3337607445
Directory /workspace/5.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2187544
Short name T994
Test name
Test status
Simulation time 388859984 ps
CPU time 2.69 seconds
Started Apr 23 12:19:36 PM PDT 24
Finished Apr 23 12:19:39 PM PDT 24
Peak memory 202160 kb
Host smart-fa58373f-d82c-4eec-915d-6cedb722f2dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 5.sram_ctrl_tl_intg_err.2187544
Directory /workspace/5.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1872847953
Short name T972
Test name
Test status
Simulation time 35240438 ps
CPU time 1.68 seconds
Started Apr 23 12:23:39 PM PDT 24
Finished Apr 23 12:23:41 PM PDT 24
Peak memory 211544 kb
Host smart-a14b6a55-308e-4b3a-bca6-af191e3e13e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872847953 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.1872847953
Directory /workspace/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.275757497
Short name T94
Test name
Test status
Simulation time 26705214 ps
CPU time 0.75 seconds
Started Apr 23 12:23:21 PM PDT 24
Finished Apr 23 12:23:24 PM PDT 24
Peak memory 201240 kb
Host smart-b46515d0-9c51-4bcd-a830-32a371b135fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275757497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 6.sram_ctrl_csr_rw.275757497
Directory /workspace/6.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2927731593
Short name T85
Test name
Test status
Simulation time 742822172 ps
CPU time 2.65 seconds
Started Apr 23 12:23:54 PM PDT 24
Finished Apr 23 12:23:58 PM PDT 24
Peak memory 201464 kb
Host smart-3bc614cd-a0a5-4dbd-9748-1e7b7c816433
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927731593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.2927731593
Directory /workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1296059997
Short name T1035
Test name
Test status
Simulation time 150182387 ps
CPU time 0.72 seconds
Started Apr 23 12:23:57 PM PDT 24
Finished Apr 23 12:23:59 PM PDT 24
Peak memory 201864 kb
Host smart-2bf55c83-57f0-4a2c-8253-80a20b10630c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296059997 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.1296059997
Directory /workspace/6.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3412775292
Short name T1002
Test name
Test status
Simulation time 168515827 ps
CPU time 2.38 seconds
Started Apr 23 12:21:40 PM PDT 24
Finished Apr 23 12:21:43 PM PDT 24
Peak memory 202204 kb
Host smart-b7574a39-7b6c-4001-b7d5-1df091b5cd79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412775292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.sram_ctrl_tl_errors.3412775292
Directory /workspace/6.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.347460523
Short name T121
Test name
Test status
Simulation time 96789220 ps
CPU time 1.48 seconds
Started Apr 23 12:18:45 PM PDT 24
Finished Apr 23 12:18:47 PM PDT 24
Peak memory 202256 kb
Host smart-dce64493-101c-4feb-8cea-e73b338f9eb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347460523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 6.sram_ctrl_tl_intg_err.347460523
Directory /workspace/6.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.496910528
Short name T961
Test name
Test status
Simulation time 35551575 ps
CPU time 0.98 seconds
Started Apr 23 12:20:09 PM PDT 24
Finished Apr 23 12:20:11 PM PDT 24
Peak memory 210336 kb
Host smart-eb098c20-b87a-4361-9d25-9a0e64b1313c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496910528 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.496910528
Directory /workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3261639227
Short name T95
Test name
Test status
Simulation time 15453374 ps
CPU time 0.7 seconds
Started Apr 23 12:24:04 PM PDT 24
Finished Apr 23 12:24:06 PM PDT 24
Peak memory 200912 kb
Host smart-9bf4acbe-0929-4173-9569-46b7b0d98efa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261639227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 7.sram_ctrl_csr_rw.3261639227
Directory /workspace/7.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.122246904
Short name T76
Test name
Test status
Simulation time 958492623 ps
CPU time 4.15 seconds
Started Apr 23 12:23:23 PM PDT 24
Finished Apr 23 12:23:29 PM PDT 24
Peak memory 201644 kb
Host smart-217280d9-213e-4a03-9e14-8343408cb49d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122246904 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.122246904
Directory /workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2468197597
Short name T979
Test name
Test status
Simulation time 59712325 ps
CPU time 0.75 seconds
Started Apr 23 12:24:03 PM PDT 24
Finished Apr 23 12:24:05 PM PDT 24
Peak memory 201696 kb
Host smart-35c69d9b-e76c-490e-ad4f-87a23dd91bb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468197597 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.2468197597
Directory /workspace/7.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.690474797
Short name T1018
Test name
Test status
Simulation time 144153728 ps
CPU time 3.41 seconds
Started Apr 23 12:23:56 PM PDT 24
Finished Apr 23 12:24:00 PM PDT 24
Peak memory 201948 kb
Host smart-90f7d955-022f-408e-a201-f23f9b356d89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690474797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
7.sram_ctrl_tl_errors.690474797
Directory /workspace/7.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1164740477
Short name T954
Test name
Test status
Simulation time 135628959 ps
CPU time 1.55 seconds
Started Apr 23 12:23:24 PM PDT 24
Finished Apr 23 12:23:26 PM PDT 24
Peak memory 201896 kb
Host smart-c5173596-e5d7-43a3-bc06-71f9b34000cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164740477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 7.sram_ctrl_tl_intg_err.1164740477
Directory /workspace/7.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2774247888
Short name T955
Test name
Test status
Simulation time 56105603 ps
CPU time 1.08 seconds
Started Apr 23 12:23:20 PM PDT 24
Finished Apr 23 12:23:22 PM PDT 24
Peak memory 208504 kb
Host smart-46122e63-4b7f-434a-a608-bb97848d4c15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774247888 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.2774247888
Directory /workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1442363718
Short name T997
Test name
Test status
Simulation time 36806501 ps
CPU time 0.61 seconds
Started Apr 23 12:19:38 PM PDT 24
Finished Apr 23 12:19:39 PM PDT 24
Peak memory 200892 kb
Host smart-61870138-9644-45ad-a7e4-136f96488781
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442363718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 8.sram_ctrl_csr_rw.1442363718
Directory /workspace/8.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.962844652
Short name T60
Test name
Test status
Simulation time 460026894 ps
CPU time 1.98 seconds
Started Apr 23 12:21:57 PM PDT 24
Finished Apr 23 12:22:00 PM PDT 24
Peak memory 202140 kb
Host smart-188edf33-6a51-44c0-9545-cff3faf8b0ec
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962844652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.962844652
Directory /workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3219265337
Short name T1013
Test name
Test status
Simulation time 28594809 ps
CPU time 0.81 seconds
Started Apr 23 12:23:20 PM PDT 24
Finished Apr 23 12:23:22 PM PDT 24
Peak memory 200536 kb
Host smart-2b8c60fa-84c3-4ec6-a42b-28ed4166884e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219265337 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.3219265337
Directory /workspace/8.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3060413775
Short name T998
Test name
Test status
Simulation time 499238556 ps
CPU time 5.06 seconds
Started Apr 23 12:24:03 PM PDT 24
Finished Apr 23 12:24:09 PM PDT 24
Peak memory 201248 kb
Host smart-844e7ec7-c381-45a9-88b2-4d1e6fc32252
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060413775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 8.sram_ctrl_tl_errors.3060413775
Directory /workspace/8.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1206140512
Short name T965
Test name
Test status
Simulation time 302561471 ps
CPU time 1.4 seconds
Started Apr 23 12:23:20 PM PDT 24
Finished Apr 23 12:23:23 PM PDT 24
Peak memory 200712 kb
Host smart-5e9e5dc4-bca2-4b9a-a905-0385c4c2c2ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206140512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 8.sram_ctrl_tl_intg_err.1206140512
Directory /workspace/8.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1567188566
Short name T960
Test name
Test status
Simulation time 130730414 ps
CPU time 1.43 seconds
Started Apr 23 12:24:09 PM PDT 24
Finished Apr 23 12:24:21 PM PDT 24
Peak memory 210856 kb
Host smart-a7e9718b-692b-463e-8b9f-1701b81c9cac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567188566 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.1567188566
Directory /workspace/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1807963499
Short name T996
Test name
Test status
Simulation time 18774553 ps
CPU time 0.62 seconds
Started Apr 23 12:18:48 PM PDT 24
Finished Apr 23 12:18:50 PM PDT 24
Peak memory 200888 kb
Host smart-7bafd891-adc7-42dd-85cd-606f0dc02389
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807963499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 9.sram_ctrl_csr_rw.1807963499
Directory /workspace/9.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1538677143
Short name T59
Test name
Test status
Simulation time 433972955 ps
CPU time 3.09 seconds
Started Apr 23 12:23:28 PM PDT 24
Finished Apr 23 12:23:32 PM PDT 24
Peak memory 201212 kb
Host smart-17d09148-e058-4a2e-ab11-4cb4aefceac9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538677143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.1538677143
Directory /workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1233835453
Short name T86
Test name
Test status
Simulation time 40367672 ps
CPU time 0.67 seconds
Started Apr 23 12:23:21 PM PDT 24
Finished Apr 23 12:23:23 PM PDT 24
Peak memory 201732 kb
Host smart-1a5472cc-8086-43ae-af7c-5b2e5259eb62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233835453 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.1233835453
Directory /workspace/9.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.4143680091
Short name T1024
Test name
Test status
Simulation time 242223217 ps
CPU time 3.65 seconds
Started Apr 23 12:23:19 PM PDT 24
Finished Apr 23 12:23:24 PM PDT 24
Peak memory 201404 kb
Host smart-a6c0c1ed-7167-4efb-90a6-56794320ffe9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143680091 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 9.sram_ctrl_tl_errors.4143680091
Directory /workspace/9.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1452946423
Short name T117
Test name
Test status
Simulation time 185294238 ps
CPU time 1.61 seconds
Started Apr 23 12:18:47 PM PDT 24
Finished Apr 23 12:18:49 PM PDT 24
Peak memory 202172 kb
Host smart-579a2aa4-6801-435b-abb2-3495a953eeef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452946423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 9.sram_ctrl_tl_intg_err.1452946423
Directory /workspace/9.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sram_ctrl_access_during_key_req.1573549432
Short name T514
Test name
Test status
Simulation time 2762771918 ps
CPU time 1069.79 seconds
Started Apr 23 12:23:47 PM PDT 24
Finished Apr 23 12:41:38 PM PDT 24
Peak memory 373448 kb
Host smart-dec2de54-4056-48c5-92a2-d0896312cafa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573549432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.sram_ctrl_access_during_key_req.1573549432
Directory /workspace/0.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/0.sram_ctrl_alert_test.968028949
Short name T233
Test name
Test status
Simulation time 30538065 ps
CPU time 0.6 seconds
Started Apr 23 12:23:01 PM PDT 24
Finished Apr 23 12:23:02 PM PDT 24
Peak memory 200492 kb
Host smart-6643e914-badb-4940-b357-711c57b3bf02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968028949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_alert_test.968028949
Directory /workspace/0.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sram_ctrl_bijection.1238383927
Short name T651
Test name
Test status
Simulation time 754167912 ps
CPU time 44.85 seconds
Started Apr 23 12:18:45 PM PDT 24
Finished Apr 23 12:19:31 PM PDT 24
Peak memory 201908 kb
Host smart-bbbe2038-de3a-469a-adf4-2abb731ceed8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238383927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.
1238383927
Directory /workspace/0.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/0.sram_ctrl_executable.490894802
Short name T360
Test name
Test status
Simulation time 6985693403 ps
CPU time 400.24 seconds
Started Apr 23 12:24:09 PM PDT 24
Finished Apr 23 12:30:52 PM PDT 24
Peak memory 364952 kb
Host smart-0b68078b-b21a-4da2-89c4-933d1fedcbed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490894802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executable
.490894802
Directory /workspace/0.sram_ctrl_executable/latest

Test location /workspace/coverage/default/0.sram_ctrl_lc_escalation.4082431337
Short name T647
Test name
Test status
Simulation time 608588590 ps
CPU time 6.06 seconds
Started Apr 23 12:23:39 PM PDT 24
Finished Apr 23 12:23:46 PM PDT 24
Peak memory 201124 kb
Host smart-1ef61aae-1023-4108-978d-34cf29e4f1f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082431337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_esc
alation.4082431337
Directory /workspace/0.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/0.sram_ctrl_max_throughput.3571353906
Short name T354
Test name
Test status
Simulation time 133082899 ps
CPU time 106.28 seconds
Started Apr 23 12:19:01 PM PDT 24
Finished Apr 23 12:20:48 PM PDT 24
Peak memory 368016 kb
Host smart-c4d916b0-cd8a-4f50-b065-2c5ba278a8d4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571353906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.sram_ctrl_max_throughput.3571353906
Directory /workspace/0.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_partial_access.573700407
Short name T826
Test name
Test status
Simulation time 57321801 ps
CPU time 2.33 seconds
Started Apr 23 12:23:20 PM PDT 24
Finished Apr 23 12:23:24 PM PDT 24
Peak memory 209212 kb
Host smart-86b333b3-85ca-4027-9690-d471031372ba
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573700407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
sram_ctrl_mem_partial_access.573700407
Directory /workspace/0.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_walk.2001840758
Short name T433
Test name
Test status
Simulation time 141451848 ps
CPU time 7.87 seconds
Started Apr 23 12:23:21 PM PDT 24
Finished Apr 23 12:23:29 PM PDT 24
Peak memory 201228 kb
Host smart-39840b38-4d5f-4f47-a256-308c40a43450
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001840758 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl
_mem_walk.2001840758
Directory /workspace/0.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/0.sram_ctrl_multiple_keys.3035399894
Short name T888
Test name
Test status
Simulation time 15829980664 ps
CPU time 1533.39 seconds
Started Apr 23 12:19:38 PM PDT 24
Finished Apr 23 12:45:12 PM PDT 24
Peak memory 369632 kb
Host smart-2928a83a-0c98-456d-9f28-71c751c20bec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035399894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multip
le_keys.3035399894
Directory /workspace/0.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access.276136638
Short name T262
Test name
Test status
Simulation time 823848732 ps
CPU time 13.46 seconds
Started Apr 23 12:24:10 PM PDT 24
Finished Apr 23 12:24:26 PM PDT 24
Peak memory 201060 kb
Host smart-601a9c5c-1e77-44e5-b067-73aa0b26973c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276136638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sr
am_ctrl_partial_access.276136638
Directory /workspace/0.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.308983064
Short name T918
Test name
Test status
Simulation time 39833328672 ps
CPU time 216.77 seconds
Started Apr 23 12:23:25 PM PDT 24
Finished Apr 23 12:27:03 PM PDT 24
Peak memory 201168 kb
Host smart-36eef068-24e0-4900-935b-f32e136ab2a2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308983064 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.sram_ctrl_partial_access_b2b.308983064
Directory /workspace/0.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/0.sram_ctrl_ram_cfg.1163262823
Short name T301
Test name
Test status
Simulation time 82652353 ps
CPU time 0.8 seconds
Started Apr 23 12:24:09 PM PDT 24
Finished Apr 23 12:24:12 PM PDT 24
Peak memory 201000 kb
Host smart-7ad52c10-f1f2-4826-b639-52299728e39a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163262823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.1163262823
Directory /workspace/0.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/0.sram_ctrl_regwen.3578077975
Short name T418
Test name
Test status
Simulation time 6389173281 ps
CPU time 1273.59 seconds
Started Apr 23 12:23:47 PM PDT 24
Finished Apr 23 12:45:01 PM PDT 24
Peak memory 373224 kb
Host smart-2965ea8f-9f5c-4e87-84fc-6b4d44b2d46e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578077975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.3578077975
Directory /workspace/0.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/0.sram_ctrl_sec_cm.3048610442
Short name T17
Test name
Test status
Simulation time 153193510 ps
CPU time 1.99 seconds
Started Apr 23 12:20:48 PM PDT 24
Finished Apr 23 12:20:50 PM PDT 24
Peak memory 223636 kb
Host smart-dc0a18af-7314-4720-86f8-efc998a818c7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048610442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_sec_cm.3048610442
Directory /workspace/0.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.sram_ctrl_smoke.2214161236
Short name T523
Test name
Test status
Simulation time 1112661754 ps
CPU time 36.02 seconds
Started Apr 23 12:20:54 PM PDT 24
Finished Apr 23 12:21:30 PM PDT 24
Peak memory 285152 kb
Host smart-baf6af5c-8957-4414-8980-18cd0dff371b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214161236 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.2214161236
Directory /workspace/0.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_all.247996006
Short name T857
Test name
Test status
Simulation time 37027623567 ps
CPU time 2057.87 seconds
Started Apr 23 12:24:05 PM PDT 24
Finished Apr 23 12:58:24 PM PDT 24
Peak memory 381732 kb
Host smart-56e7bd97-9585-46ef-9391-70cd397fabb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247996006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.sram_ctrl_stress_all.247996006
Directory /workspace/0.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.3114885601
Short name T667
Test name
Test status
Simulation time 2536824604 ps
CPU time 153.16 seconds
Started Apr 23 12:23:28 PM PDT 24
Finished Apr 23 12:26:02 PM PDT 24
Peak memory 374716 kb
Host smart-f023b036-271c-4804-ae27-2603777eb5d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3114885601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.3114885601
Directory /workspace/0.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_pipeline.1828307361
Short name T255
Test name
Test status
Simulation time 5195215896 ps
CPU time 217.1 seconds
Started Apr 23 12:24:12 PM PDT 24
Finished Apr 23 12:27:52 PM PDT 24
Peak memory 201712 kb
Host smart-a5052b1b-dabf-46bb-8bd9-5034ea316094
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828307361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.sram_ctrl_stress_pipeline.1828307361
Directory /workspace/0.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2753542353
Short name T517
Test name
Test status
Simulation time 99297431 ps
CPU time 33.65 seconds
Started Apr 23 12:21:22 PM PDT 24
Finished Apr 23 12:21:56 PM PDT 24
Peak memory 290008 kb
Host smart-cc6721ba-e546-4629-8a2a-44c83831454a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753542353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.sram_ctrl_throughput_w_partial_write.2753542353
Directory /workspace/0.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/1.sram_ctrl_access_during_key_req.2685105758
Short name T804
Test name
Test status
Simulation time 689201614 ps
CPU time 154.31 seconds
Started Apr 23 12:23:19 PM PDT 24
Finished Apr 23 12:25:54 PM PDT 24
Peak memory 349020 kb
Host smart-b5677521-bcc9-4e69-9297-c9c7a084d45b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685105758 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.sram_ctrl_access_during_key_req.2685105758
Directory /workspace/1.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/1.sram_ctrl_alert_test.1644519316
Short name T740
Test name
Test status
Simulation time 14813799 ps
CPU time 0.64 seconds
Started Apr 23 12:23:32 PM PDT 24
Finished Apr 23 12:23:34 PM PDT 24
Peak memory 200808 kb
Host smart-6aced148-82ac-44e4-9591-53ac2f7b4be7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644519316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_alert_test.1644519316
Directory /workspace/1.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sram_ctrl_bijection.1522027648
Short name T784
Test name
Test status
Simulation time 13728903870 ps
CPU time 59.97 seconds
Started Apr 23 12:23:57 PM PDT 24
Finished Apr 23 12:24:59 PM PDT 24
Peak memory 201732 kb
Host smart-77e0a0fb-2ebb-4145-9b18-29a56bb378e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522027648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.
1522027648
Directory /workspace/1.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/1.sram_ctrl_executable.2715911096
Short name T388
Test name
Test status
Simulation time 2678944279 ps
CPU time 976.24 seconds
Started Apr 23 12:23:20 PM PDT 24
Finished Apr 23 12:39:38 PM PDT 24
Peak memory 369012 kb
Host smart-725d71a8-69e7-4018-8e4a-01b3cc3b038d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715911096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executabl
e.2715911096
Directory /workspace/1.sram_ctrl_executable/latest

Test location /workspace/coverage/default/1.sram_ctrl_lc_escalation.2782901352
Short name T318
Test name
Test status
Simulation time 1485937319 ps
CPU time 6.87 seconds
Started Apr 23 12:23:20 PM PDT 24
Finished Apr 23 12:23:28 PM PDT 24
Peak memory 201004 kb
Host smart-755768d2-826b-445a-ae52-ab69ffd060ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782901352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_esc
alation.2782901352
Directory /workspace/1.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/1.sram_ctrl_max_throughput.2867383223
Short name T412
Test name
Test status
Simulation time 470467237 ps
CPU time 58.74 seconds
Started Apr 23 12:19:38 PM PDT 24
Finished Apr 23 12:20:38 PM PDT 24
Peak memory 339764 kb
Host smart-08620ae2-92e5-42e3-8fa1-6108b5064ae7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867383223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.sram_ctrl_max_throughput.2867383223
Directory /workspace/1.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_partial_access.2388353146
Short name T613
Test name
Test status
Simulation time 90751289 ps
CPU time 2.71 seconds
Started Apr 23 12:23:19 PM PDT 24
Finished Apr 23 12:23:23 PM PDT 24
Peak memory 208296 kb
Host smart-d6c44d67-2da6-4a5e-8254-4c7a6c40c735
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388353146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.sram_ctrl_mem_partial_access.2388353146
Directory /workspace/1.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_walk.3777065540
Short name T313
Test name
Test status
Simulation time 312856462 ps
CPU time 5.44 seconds
Started Apr 23 12:23:21 PM PDT 24
Finished Apr 23 12:23:28 PM PDT 24
Peak memory 201572 kb
Host smart-5a81ccea-bfbb-4998-91b4-4dc0492ad24e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777065540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl
_mem_walk.3777065540
Directory /workspace/1.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/1.sram_ctrl_multiple_keys.2611386046
Short name T232
Test name
Test status
Simulation time 9425616500 ps
CPU time 1421.08 seconds
Started Apr 23 12:24:03 PM PDT 24
Finished Apr 23 12:47:45 PM PDT 24
Peak memory 373000 kb
Host smart-fb85c5d7-9868-4e35-ad7e-acaef3e84057
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611386046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multip
le_keys.2611386046
Directory /workspace/1.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access.2095376014
Short name T756
Test name
Test status
Simulation time 561469223 ps
CPU time 10.48 seconds
Started Apr 23 12:24:02 PM PDT 24
Finished Apr 23 12:24:13 PM PDT 24
Peak memory 201112 kb
Host smart-5b598623-5002-423d-9212-ef7ba02645ed
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095376014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.s
ram_ctrl_partial_access.2095376014
Directory /workspace/1.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3197285034
Short name T599
Test name
Test status
Simulation time 5817721018 ps
CPU time 409.25 seconds
Started Apr 23 12:18:47 PM PDT 24
Finished Apr 23 12:25:37 PM PDT 24
Peak memory 201932 kb
Host smart-dad7254b-72b2-4c60-964d-9658c9d7c280
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197285034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.sram_ctrl_partial_access_b2b.3197285034
Directory /workspace/1.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/1.sram_ctrl_ram_cfg.587833065
Short name T941
Test name
Test status
Simulation time 28098836 ps
CPU time 0.77 seconds
Started Apr 23 12:24:09 PM PDT 24
Finished Apr 23 12:24:12 PM PDT 24
Peak memory 201672 kb
Host smart-89617009-0454-4304-98b7-deba3bdf7866
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587833065 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.587833065
Directory /workspace/1.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/1.sram_ctrl_regwen.3937680721
Short name T334
Test name
Test status
Simulation time 11046089434 ps
CPU time 669.39 seconds
Started Apr 23 12:20:11 PM PDT 24
Finished Apr 23 12:31:21 PM PDT 24
Peak memory 371168 kb
Host smart-25a05342-74a2-455d-a908-467ce4af5990
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937680721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.3937680721
Directory /workspace/1.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/1.sram_ctrl_sec_cm.3215606464
Short name T27
Test name
Test status
Simulation time 1098769928 ps
CPU time 2.13 seconds
Started Apr 23 12:23:18 PM PDT 24
Finished Apr 23 12:23:22 PM PDT 24
Peak memory 222116 kb
Host smart-6404d425-5c35-411c-a86f-4811031baf17
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215606464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_sec_cm.3215606464
Directory /workspace/1.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sram_ctrl_smoke.2246684252
Short name T486
Test name
Test status
Simulation time 104798190 ps
CPU time 34.9 seconds
Started Apr 23 12:23:00 PM PDT 24
Finished Apr 23 12:23:37 PM PDT 24
Peak memory 317408 kb
Host smart-60189102-0027-4137-827d-712e3374abea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246684252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.2246684252
Directory /workspace/1.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_all.1743786508
Short name T421
Test name
Test status
Simulation time 75532175204 ps
CPU time 1408.54 seconds
Started Apr 23 12:23:33 PM PDT 24
Finished Apr 23 12:47:02 PM PDT 24
Peak memory 380928 kb
Host smart-cbdbf6e7-e608-448d-a8b2-9f152c7efcc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743786508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 1.sram_ctrl_stress_all.1743786508
Directory /workspace/1.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.45282382
Short name T441
Test name
Test status
Simulation time 732734567 ps
CPU time 37.04 seconds
Started Apr 23 12:24:11 PM PDT 24
Finished Apr 23 12:24:51 PM PDT 24
Peak memory 302088 kb
Host smart-c2717a53-84ca-4238-acbc-8d558cca349e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=45282382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.45282382
Directory /workspace/1.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_pipeline.2124998682
Short name T701
Test name
Test status
Simulation time 4281161872 ps
CPU time 237.36 seconds
Started Apr 23 12:24:02 PM PDT 24
Finished Apr 23 12:28:01 PM PDT 24
Peak memory 200892 kb
Host smart-1b241237-59d1-42c8-9cd1-91b8acf4624b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124998682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.sram_ctrl_stress_pipeline.2124998682
Directory /workspace/1.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3864293512
Short name T383
Test name
Test status
Simulation time 727692381 ps
CPU time 86.67 seconds
Started Apr 23 12:23:19 PM PDT 24
Finished Apr 23 12:24:47 PM PDT 24
Peak memory 353580 kb
Host smart-e64977e2-bf6b-4129-9745-1868dff687df
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864293512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.sram_ctrl_throughput_w_partial_write.3864293512
Directory /workspace/1.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/10.sram_ctrl_access_during_key_req.4192752942
Short name T505
Test name
Test status
Simulation time 15621181997 ps
CPU time 1066.36 seconds
Started Apr 23 12:24:00 PM PDT 24
Finished Apr 23 12:41:47 PM PDT 24
Peak memory 372652 kb
Host smart-11be0aa4-8d66-43ec-9a14-7a27074b6260
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192752942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.sram_ctrl_access_during_key_req.4192752942
Directory /workspace/10.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/10.sram_ctrl_bijection.1390908533
Short name T236
Test name
Test status
Simulation time 1323110089 ps
CPU time 39.66 seconds
Started Apr 23 12:24:21 PM PDT 24
Finished Apr 23 12:25:01 PM PDT 24
Peak memory 201888 kb
Host smart-bda352cc-d4ed-4f89-8c34-0656e134db26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390908533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection
.1390908533
Directory /workspace/10.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/10.sram_ctrl_executable.101313988
Short name T303
Test name
Test status
Simulation time 9959555815 ps
CPU time 653.25 seconds
Started Apr 23 12:24:13 PM PDT 24
Finished Apr 23 12:35:09 PM PDT 24
Peak memory 372648 kb
Host smart-5408eafa-9f38-4f6c-9f6b-ed5bbc30159b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101313988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executabl
e.101313988
Directory /workspace/10.sram_ctrl_executable/latest

Test location /workspace/coverage/default/10.sram_ctrl_lc_escalation.3433093462
Short name T848
Test name
Test status
Simulation time 8105140661 ps
CPU time 7.53 seconds
Started Apr 23 12:24:01 PM PDT 24
Finished Apr 23 12:24:10 PM PDT 24
Peak memory 201780 kb
Host smart-187923d3-03e0-4048-b611-b3dd1ac753df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433093462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_es
calation.3433093462
Directory /workspace/10.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/10.sram_ctrl_max_throughput.522554552
Short name T855
Test name
Test status
Simulation time 244732475 ps
CPU time 9.46 seconds
Started Apr 23 12:23:58 PM PDT 24
Finished Apr 23 12:24:09 PM PDT 24
Peak memory 251000 kb
Host smart-c39c6bdd-e79c-47b7-beb2-5eeff221f139
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522554552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.sram_ctrl_max_throughput.522554552
Directory /workspace/10.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_partial_access.4191650021
Short name T766
Test name
Test status
Simulation time 85955606 ps
CPU time 2.49 seconds
Started Apr 23 12:24:06 PM PDT 24
Finished Apr 23 12:24:10 PM PDT 24
Peak memory 210036 kb
Host smart-4dbcedb4-568c-408f-a392-9a8d9d76e9e1
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191650021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.sram_ctrl_mem_partial_access.4191650021
Directory /workspace/10.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_walk.2623258437
Short name T681
Test name
Test status
Simulation time 544130685 ps
CPU time 4.21 seconds
Started Apr 23 12:24:06 PM PDT 24
Finished Apr 23 12:24:12 PM PDT 24
Peak memory 201824 kb
Host smart-3415a7d6-ff10-465b-bfde-1375c49cf739
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623258437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr
l_mem_walk.2623258437
Directory /workspace/10.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/10.sram_ctrl_multiple_keys.827165120
Short name T749
Test name
Test status
Simulation time 1919117423 ps
CPU time 519.09 seconds
Started Apr 23 12:24:01 PM PDT 24
Finished Apr 23 12:32:41 PM PDT 24
Peak memory 372652 kb
Host smart-c151d62b-e4bf-4579-b85a-a063077df1ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827165120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multip
le_keys.827165120
Directory /workspace/10.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access.1425924922
Short name T680
Test name
Test status
Simulation time 420460117 ps
CPU time 27.54 seconds
Started Apr 23 12:24:09 PM PDT 24
Finished Apr 23 12:24:39 PM PDT 24
Peak memory 283520 kb
Host smart-050de203-8dbb-4061-b8cd-a3961b6b18de
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425924922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
sram_ctrl_partial_access.1425924922
Directory /workspace/10.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2273637999
Short name T213
Test name
Test status
Simulation time 54962350790 ps
CPU time 249.13 seconds
Started Apr 23 12:24:09 PM PDT 24
Finished Apr 23 12:28:20 PM PDT 24
Peak memory 201836 kb
Host smart-021cae76-f68e-4adf-8490-93d30e976a9f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273637999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 10.sram_ctrl_partial_access_b2b.2273637999
Directory /workspace/10.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/10.sram_ctrl_ram_cfg.19552701
Short name T623
Test name
Test status
Simulation time 42972630 ps
CPU time 0.71 seconds
Started Apr 23 12:24:21 PM PDT 24
Finished Apr 23 12:24:23 PM PDT 24
Peak memory 201928 kb
Host smart-bf0f3e5d-e380-4d31-a250-3fa9a9170962
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19552701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf
g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.19552701
Directory /workspace/10.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/10.sram_ctrl_regwen.305850260
Short name T735
Test name
Test status
Simulation time 12579676452 ps
CPU time 1024.4 seconds
Started Apr 23 12:24:09 PM PDT 24
Finished Apr 23 12:41:16 PM PDT 24
Peak memory 373612 kb
Host smart-7aafef7f-7aab-4e40-9535-c68888531443
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305850260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.305850260
Directory /workspace/10.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/10.sram_ctrl_smoke.326699350
Short name T591
Test name
Test status
Simulation time 1897866658 ps
CPU time 19.62 seconds
Started Apr 23 12:24:10 PM PDT 24
Finished Apr 23 12:24:33 PM PDT 24
Peak memory 261644 kb
Host smart-55889a51-ea6e-4c34-a7ff-3bd7e4b51568
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326699350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.326699350
Directory /workspace/10.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.850509879
Short name T261
Test name
Test status
Simulation time 662426478 ps
CPU time 225.43 seconds
Started Apr 23 12:24:00 PM PDT 24
Finished Apr 23 12:27:47 PM PDT 24
Peak memory 378872 kb
Host smart-cb16eb1e-0543-4012-a054-4967417338ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=850509879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.850509879
Directory /workspace/10.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_pipeline.857586825
Short name T526
Test name
Test status
Simulation time 4885803234 ps
CPU time 115.93 seconds
Started Apr 23 12:24:07 PM PDT 24
Finished Apr 23 12:26:04 PM PDT 24
Peak memory 201956 kb
Host smart-dd387eed-801b-4aad-a36d-00825867868b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857586825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.sram_ctrl_stress_pipeline.857586825
Directory /workspace/10.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2298822370
Short name T548
Test name
Test status
Simulation time 332207332 ps
CPU time 57.23 seconds
Started Apr 23 12:24:09 PM PDT 24
Finished Apr 23 12:25:08 PM PDT 24
Peak memory 326956 kb
Host smart-b8562c9e-c9ed-429e-abea-57779f184748
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298822370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.sram_ctrl_throughput_w_partial_write.2298822370
Directory /workspace/10.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/11.sram_ctrl_access_during_key_req.165428315
Short name T278
Test name
Test status
Simulation time 8834389988 ps
CPU time 674.37 seconds
Started Apr 23 12:24:13 PM PDT 24
Finished Apr 23 12:35:30 PM PDT 24
Peak memory 372300 kb
Host smart-2ef30461-e174-4a5d-8692-fff4090aff03
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165428315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 11.sram_ctrl_access_during_key_req.165428315
Directory /workspace/11.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/11.sram_ctrl_alert_test.1861508943
Short name T698
Test name
Test status
Simulation time 69505090 ps
CPU time 0.63 seconds
Started Apr 23 12:24:07 PM PDT 24
Finished Apr 23 12:24:09 PM PDT 24
Peak memory 200760 kb
Host smart-84897d83-c358-4164-bc6d-39d6cc104962
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861508943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.sram_ctrl_alert_test.1861508943
Directory /workspace/11.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sram_ctrl_bijection.2923911054
Short name T350
Test name
Test status
Simulation time 8548648682 ps
CPU time 45.6 seconds
Started Apr 23 12:24:06 PM PDT 24
Finished Apr 23 12:24:53 PM PDT 24
Peak memory 202012 kb
Host smart-4eb8edf3-f57b-45d8-8bf0-e5a9cc156940
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923911054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection
.2923911054
Directory /workspace/11.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/11.sram_ctrl_executable.2166350596
Short name T748
Test name
Test status
Simulation time 12498282164 ps
CPU time 1581.92 seconds
Started Apr 23 12:24:01 PM PDT 24
Finished Apr 23 12:50:24 PM PDT 24
Peak memory 373408 kb
Host smart-ec02c3c5-d0a3-49b9-8404-973bd2ae5d8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166350596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executab
le.2166350596
Directory /workspace/11.sram_ctrl_executable/latest

Test location /workspace/coverage/default/11.sram_ctrl_lc_escalation.2833657675
Short name T877
Test name
Test status
Simulation time 1694612902 ps
CPU time 4.83 seconds
Started Apr 23 12:24:13 PM PDT 24
Finished Apr 23 12:24:20 PM PDT 24
Peak memory 201528 kb
Host smart-be134b4c-42d6-45ef-9cc2-d76f69e7edb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833657675 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_es
calation.2833657675
Directory /workspace/11.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/11.sram_ctrl_max_throughput.3748655229
Short name T639
Test name
Test status
Simulation time 146188145 ps
CPU time 52.47 seconds
Started Apr 23 12:24:00 PM PDT 24
Finished Apr 23 12:24:54 PM PDT 24
Peak memory 325832 kb
Host smart-d7d2b9a6-7142-4b82-a977-5bf0dfca9184
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748655229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.sram_ctrl_max_throughput.3748655229
Directory /workspace/11.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_partial_access.1049424301
Short name T751
Test name
Test status
Simulation time 165041930 ps
CPU time 4.95 seconds
Started Apr 23 12:24:13 PM PDT 24
Finished Apr 23 12:24:20 PM PDT 24
Peak memory 210056 kb
Host smart-f119af63-cfa2-45b2-81a8-0f803d62a085
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049424301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.sram_ctrl_mem_partial_access.1049424301
Directory /workspace/11.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_walk.3624201165
Short name T903
Test name
Test status
Simulation time 295245119 ps
CPU time 5.11 seconds
Started Apr 23 12:24:11 PM PDT 24
Finished Apr 23 12:24:19 PM PDT 24
Peak memory 201804 kb
Host smart-7f180664-e059-4251-a7e8-4b740c658a74
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624201165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctr
l_mem_walk.3624201165
Directory /workspace/11.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/11.sram_ctrl_multiple_keys.2818953880
Short name T513
Test name
Test status
Simulation time 20379371785 ps
CPU time 58.89 seconds
Started Apr 23 12:24:09 PM PDT 24
Finished Apr 23 12:25:10 PM PDT 24
Peak memory 313652 kb
Host smart-4ef41eb5-4515-4c28-9256-5085799fa617
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818953880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multi
ple_keys.2818953880
Directory /workspace/11.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access.2641057725
Short name T348
Test name
Test status
Simulation time 742232301 ps
CPU time 55.48 seconds
Started Apr 23 12:24:15 PM PDT 24
Finished Apr 23 12:25:12 PM PDT 24
Peak memory 341820 kb
Host smart-c41434b3-27df-4d54-9de5-927ecd5975fc
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641057725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
sram_ctrl_partial_access.2641057725
Directory /workspace/11.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3700463275
Short name T516
Test name
Test status
Simulation time 26488381521 ps
CPU time 207.99 seconds
Started Apr 23 12:24:13 PM PDT 24
Finished Apr 23 12:27:43 PM PDT 24
Peak memory 201860 kb
Host smart-5c8b8ccb-cec3-4321-ab71-bc95081dec4e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700463275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 11.sram_ctrl_partial_access_b2b.3700463275
Directory /workspace/11.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/11.sram_ctrl_ram_cfg.4223548767
Short name T274
Test name
Test status
Simulation time 100550811 ps
CPU time 0.73 seconds
Started Apr 23 12:24:00 PM PDT 24
Finished Apr 23 12:24:02 PM PDT 24
Peak memory 201888 kb
Host smart-ddd0109e-ae0d-4660-8c32-3598acfe3af9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223548767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.4223548767
Directory /workspace/11.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/11.sram_ctrl_smoke.3420028971
Short name T258
Test name
Test status
Simulation time 3074480593 ps
CPU time 9.75 seconds
Started Apr 23 12:23:59 PM PDT 24
Finished Apr 23 12:24:10 PM PDT 24
Peak memory 201892 kb
Host smart-1d75fbe8-285e-4d5a-9b24-ad8037abbba6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420028971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.3420028971
Directory /workspace/11.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_all.1286742942
Short name T312
Test name
Test status
Simulation time 9251723241 ps
CPU time 413.22 seconds
Started Apr 23 12:24:15 PM PDT 24
Finished Apr 23 12:31:10 PM PDT 24
Peak memory 366412 kb
Host smart-15537173-bc10-4e19-ab8d-cc75983405de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286742942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 11.sram_ctrl_stress_all.1286742942
Directory /workspace/11.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.160510464
Short name T46
Test name
Test status
Simulation time 1511001278 ps
CPU time 41.25 seconds
Started Apr 23 12:24:06 PM PDT 24
Finished Apr 23 12:24:48 PM PDT 24
Peak memory 242152 kb
Host smart-c7ec551d-ecf7-4620-94e3-0561a67165f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=160510464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.160510464
Directory /workspace/11.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_pipeline.2845619137
Short name T883
Test name
Test status
Simulation time 1918698049 ps
CPU time 161.74 seconds
Started Apr 23 12:24:06 PM PDT 24
Finished Apr 23 12:26:49 PM PDT 24
Peak memory 201904 kb
Host smart-2aacd983-f8eb-4e6c-ad22-e5074ac4a53b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845619137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.sram_ctrl_stress_pipeline.2845619137
Directory /workspace/11.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.708251826
Short name T765
Test name
Test status
Simulation time 136290886 ps
CPU time 34.12 seconds
Started Apr 23 12:24:02 PM PDT 24
Finished Apr 23 12:24:37 PM PDT 24
Peak memory 292320 kb
Host smart-d7ae141c-e398-4c6a-b97f-36c3dc27e7c6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708251826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.sram_ctrl_throughput_w_partial_write.708251826
Directory /workspace/11.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/12.sram_ctrl_access_during_key_req.3651114103
Short name T774
Test name
Test status
Simulation time 5882091924 ps
CPU time 815.86 seconds
Started Apr 23 12:24:05 PM PDT 24
Finished Apr 23 12:37:42 PM PDT 24
Peak memory 372680 kb
Host smart-3e921739-230f-4618-b2d2-545496abd2cc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651114103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.sram_ctrl_access_during_key_req.3651114103
Directory /workspace/12.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/12.sram_ctrl_alert_test.3647796564
Short name T315
Test name
Test status
Simulation time 53499848 ps
CPU time 0.63 seconds
Started Apr 23 12:24:16 PM PDT 24
Finished Apr 23 12:24:18 PM PDT 24
Peak memory 200920 kb
Host smart-6ede8a6a-e0e3-4de4-b323-7b5f6f950745
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647796564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.sram_ctrl_alert_test.3647796564
Directory /workspace/12.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sram_ctrl_bijection.938082185
Short name T764
Test name
Test status
Simulation time 16915854343 ps
CPU time 49 seconds
Started Apr 23 12:24:09 PM PDT 24
Finished Apr 23 12:25:00 PM PDT 24
Peak memory 201896 kb
Host smart-e7e9f94f-4343-47bc-80d3-c4fa588525f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938082185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection.
938082185
Directory /workspace/12.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/12.sram_ctrl_executable.2006559
Short name T231
Test name
Test status
Simulation time 14732455137 ps
CPU time 509.51 seconds
Started Apr 23 12:24:40 PM PDT 24
Finished Apr 23 12:33:11 PM PDT 24
Peak memory 372948 kb
Host smart-74fab0a5-f658-47d3-b3b6-fe8edd95120d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executa
ble_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executable.2006559
Directory /workspace/12.sram_ctrl_executable/latest

Test location /workspace/coverage/default/12.sram_ctrl_lc_escalation.3345195908
Short name T808
Test name
Test status
Simulation time 434092006 ps
CPU time 5.4 seconds
Started Apr 23 12:24:04 PM PDT 24
Finished Apr 23 12:24:11 PM PDT 24
Peak memory 201964 kb
Host smart-312313cf-ba19-4595-be4f-0fcc4e83e358
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345195908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_es
calation.3345195908
Directory /workspace/12.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/12.sram_ctrl_max_throughput.2667404655
Short name T189
Test name
Test status
Simulation time 220897273 ps
CPU time 6.16 seconds
Started Apr 23 12:24:13 PM PDT 24
Finished Apr 23 12:24:21 PM PDT 24
Peak memory 234648 kb
Host smart-a504b81c-dd47-4225-86d0-948fa523dd6e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667404655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.sram_ctrl_max_throughput.2667404655
Directory /workspace/12.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_partial_access.3848403631
Short name T824
Test name
Test status
Simulation time 117582271 ps
CPU time 4.63 seconds
Started Apr 23 12:24:10 PM PDT 24
Finished Apr 23 12:24:18 PM PDT 24
Peak memory 210064 kb
Host smart-63d2621c-8a80-4b87-a5ed-0f5702d8de53
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848403631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.sram_ctrl_mem_partial_access.3848403631
Directory /workspace/12.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_walk.3299610187
Short name T568
Test name
Test status
Simulation time 76639037 ps
CPU time 4.12 seconds
Started Apr 23 12:24:14 PM PDT 24
Finished Apr 23 12:24:20 PM PDT 24
Peak memory 201868 kb
Host smart-d2b19eac-662e-48b9-877e-c47614d1b4ab
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299610187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctr
l_mem_walk.3299610187
Directory /workspace/12.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/12.sram_ctrl_multiple_keys.1911287446
Short name T215
Test name
Test status
Simulation time 15433748739 ps
CPU time 762.13 seconds
Started Apr 23 12:24:06 PM PDT 24
Finished Apr 23 12:36:49 PM PDT 24
Peak memory 374772 kb
Host smart-937bfa59-b5bb-4bf8-9865-9eed97ad7b44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911287446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multi
ple_keys.1911287446
Directory /workspace/12.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access.81832173
Short name T221
Test name
Test status
Simulation time 34215951 ps
CPU time 1.55 seconds
Started Apr 23 12:23:59 PM PDT 24
Finished Apr 23 12:24:02 PM PDT 24
Peak memory 201796 kb
Host smart-fd40f5be-f312-48b9-a08d-c52170269f4a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81832173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sr
am_ctrl_partial_access.81832173
Directory /workspace/12.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.349876514
Short name T289
Test name
Test status
Simulation time 75836050131 ps
CPU time 430.03 seconds
Started Apr 23 12:24:09 PM PDT 24
Finished Apr 23 12:31:21 PM PDT 24
Peak memory 201720 kb
Host smart-040fe5dc-b021-4a3f-aae5-f945c8aadb28
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349876514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.sram_ctrl_partial_access_b2b.349876514
Directory /workspace/12.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/12.sram_ctrl_ram_cfg.1840037325
Short name T650
Test name
Test status
Simulation time 32927050 ps
CPU time 0.77 seconds
Started Apr 23 12:24:04 PM PDT 24
Finished Apr 23 12:24:06 PM PDT 24
Peak memory 202044 kb
Host smart-101738e1-b1b6-4296-9c73-95003f3ecf90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840037325 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.1840037325
Directory /workspace/12.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/12.sram_ctrl_regwen.1828942355
Short name T139
Test name
Test status
Simulation time 6876337605 ps
CPU time 1281.49 seconds
Started Apr 23 12:24:07 PM PDT 24
Finished Apr 23 12:45:31 PM PDT 24
Peak memory 364520 kb
Host smart-e085c1ea-2fb6-4df3-9868-a63d2252e5ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828942355 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.1828942355
Directory /workspace/12.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/12.sram_ctrl_smoke.3973585327
Short name T169
Test name
Test status
Simulation time 301073509 ps
CPU time 8.67 seconds
Started Apr 23 12:24:13 PM PDT 24
Finished Apr 23 12:24:24 PM PDT 24
Peak memory 202008 kb
Host smart-1dac70a7-09c9-45ab-8330-5ae4f0706091
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973585327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.3973585327
Directory /workspace/12.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_all.1373088345
Short name T933
Test name
Test status
Simulation time 139066748662 ps
CPU time 3311.38 seconds
Started Apr 23 12:24:14 PM PDT 24
Finished Apr 23 01:19:27 PM PDT 24
Peak memory 378876 kb
Host smart-fd3db502-0fc7-4f16-8aaf-fa0d99098aa8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373088345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 12.sram_ctrl_stress_all.1373088345
Directory /workspace/12.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.1846011454
Short name T649
Test name
Test status
Simulation time 2076088473 ps
CPU time 101.19 seconds
Started Apr 23 12:24:06 PM PDT 24
Finished Apr 23 12:25:48 PM PDT 24
Peak memory 340684 kb
Host smart-3b3997e0-a998-4ddd-b21f-331fa1e1f93e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1846011454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.1846011454
Directory /workspace/12.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_pipeline.79550647
Short name T946
Test name
Test status
Simulation time 3081986930 ps
CPU time 284.11 seconds
Started Apr 23 12:24:09 PM PDT 24
Finished Apr 23 12:28:56 PM PDT 24
Peak memory 201960 kb
Host smart-27ff2460-6ae3-4969-8be3-ba4e9151d1f8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79550647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
sram_ctrl_stress_pipeline.79550647
Directory /workspace/12.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1747347390
Short name T728
Test name
Test status
Simulation time 150109015 ps
CPU time 103.09 seconds
Started Apr 23 12:24:02 PM PDT 24
Finished Apr 23 12:25:46 PM PDT 24
Peak memory 363436 kb
Host smart-2affde0f-76ff-4b91-a4bd-cd0cb94f4253
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747347390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.sram_ctrl_throughput_w_partial_write.1747347390
Directory /workspace/12.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/13.sram_ctrl_access_during_key_req.554974973
Short name T70
Test name
Test status
Simulation time 3313077286 ps
CPU time 562.92 seconds
Started Apr 23 12:24:06 PM PDT 24
Finished Apr 23 12:33:30 PM PDT 24
Peak memory 371700 kb
Host smart-a4bcfb6d-3cb6-4776-9068-582a8b843152
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554974973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 13.sram_ctrl_access_during_key_req.554974973
Directory /workspace/13.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/13.sram_ctrl_alert_test.2245696259
Short name T243
Test name
Test status
Simulation time 11737635 ps
CPU time 0.63 seconds
Started Apr 23 12:24:16 PM PDT 24
Finished Apr 23 12:24:18 PM PDT 24
Peak memory 200760 kb
Host smart-0e4e95c9-5956-4f5c-b5ab-d3082c049175
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245696259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.sram_ctrl_alert_test.2245696259
Directory /workspace/13.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sram_ctrl_bijection.1400533060
Short name T710
Test name
Test status
Simulation time 5789202770 ps
CPU time 62.18 seconds
Started Apr 23 12:24:06 PM PDT 24
Finished Apr 23 12:25:09 PM PDT 24
Peak memory 201940 kb
Host smart-4a97627f-4e40-4ea9-87a7-2af80a0bb573
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400533060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection
.1400533060
Directory /workspace/13.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/13.sram_ctrl_executable.1224254945
Short name T41
Test name
Test status
Simulation time 37316495178 ps
CPU time 266.19 seconds
Started Apr 23 12:24:06 PM PDT 24
Finished Apr 23 12:28:34 PM PDT 24
Peak memory 354276 kb
Host smart-80e0b694-db8f-4cef-a7d2-3b83e0846619
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224254945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executab
le.1224254945
Directory /workspace/13.sram_ctrl_executable/latest

Test location /workspace/coverage/default/13.sram_ctrl_lc_escalation.4116009012
Short name T707
Test name
Test status
Simulation time 1411922623 ps
CPU time 7.97 seconds
Started Apr 23 12:24:12 PM PDT 24
Finished Apr 23 12:24:23 PM PDT 24
Peak memory 210140 kb
Host smart-da1e2e5f-d4ce-4655-9ff7-b09d548de4c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116009012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_es
calation.4116009012
Directory /workspace/13.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/13.sram_ctrl_max_throughput.646657546
Short name T32
Test name
Test status
Simulation time 454107092 ps
CPU time 84.17 seconds
Started Apr 23 12:24:08 PM PDT 24
Finished Apr 23 12:25:35 PM PDT 24
Peak memory 335828 kb
Host smart-9036a885-082c-4d74-93a5-8c2604f4a484
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646657546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.sram_ctrl_max_throughput.646657546
Directory /workspace/13.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_partial_access.330532141
Short name T349
Test name
Test status
Simulation time 184123096 ps
CPU time 4.95 seconds
Started Apr 23 12:24:30 PM PDT 24
Finished Apr 23 12:24:36 PM PDT 24
Peak memory 210060 kb
Host smart-ac7c9bd5-257a-4a70-b280-75a9a39f8380
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330532141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.sram_ctrl_mem_partial_access.330532141
Directory /workspace/13.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_walk.1279709769
Short name T453
Test name
Test status
Simulation time 465187349 ps
CPU time 4.81 seconds
Started Apr 23 12:24:24 PM PDT 24
Finished Apr 23 12:24:30 PM PDT 24
Peak memory 201740 kb
Host smart-8eefb4cd-861b-4f09-9943-f012e53840f3
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279709769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctr
l_mem_walk.1279709769
Directory /workspace/13.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/13.sram_ctrl_multiple_keys.4184333505
Short name T186
Test name
Test status
Simulation time 3364296763 ps
CPU time 1774.22 seconds
Started Apr 23 12:24:36 PM PDT 24
Finished Apr 23 12:54:13 PM PDT 24
Peak memory 372840 kb
Host smart-3d92657e-a38a-4c81-b026-4e23048882bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184333505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multi
ple_keys.4184333505
Directory /workspace/13.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access.3727830166
Short name T353
Test name
Test status
Simulation time 2062200502 ps
CPU time 61.55 seconds
Started Apr 23 12:24:08 PM PDT 24
Finished Apr 23 12:25:12 PM PDT 24
Peak memory 320280 kb
Host smart-41720eed-224a-4726-958a-ed516a596be6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727830166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
sram_ctrl_partial_access.3727830166
Directory /workspace/13.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.451085541
Short name T761
Test name
Test status
Simulation time 25770351323 ps
CPU time 309.7 seconds
Started Apr 23 12:24:12 PM PDT 24
Finished Apr 23 12:29:24 PM PDT 24
Peak memory 201924 kb
Host smart-5a7c9661-9cb9-4cda-bf80-eb58aefdd497
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451085541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.sram_ctrl_partial_access_b2b.451085541
Directory /workspace/13.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/13.sram_ctrl_ram_cfg.3726929271
Short name T527
Test name
Test status
Simulation time 29960665 ps
CPU time 0.74 seconds
Started Apr 23 12:24:04 PM PDT 24
Finished Apr 23 12:24:06 PM PDT 24
Peak memory 201892 kb
Host smart-eb093656-3c2c-41aa-b874-3c669262da42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726929271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.3726929271
Directory /workspace/13.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/13.sram_ctrl_regwen.3111130372
Short name T907
Test name
Test status
Simulation time 2222697788 ps
CPU time 569.9 seconds
Started Apr 23 12:24:04 PM PDT 24
Finished Apr 23 12:33:35 PM PDT 24
Peak memory 362184 kb
Host smart-f897cae9-acdc-4bcd-9e8b-003ca3a9c8a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111130372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.3111130372
Directory /workspace/13.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/13.sram_ctrl_smoke.1096591791
Short name T502
Test name
Test status
Simulation time 761975296 ps
CPU time 4.35 seconds
Started Apr 23 12:24:08 PM PDT 24
Finished Apr 23 12:24:14 PM PDT 24
Peak memory 218088 kb
Host smart-5a757207-959c-45e5-b983-90d8a902fd06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096591791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.1096591791
Directory /workspace/13.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_all.273442610
Short name T302
Test name
Test status
Simulation time 69151736709 ps
CPU time 5048.97 seconds
Started Apr 23 12:24:19 PM PDT 24
Finished Apr 23 01:48:29 PM PDT 24
Peak memory 373976 kb
Host smart-feca5b42-263a-4474-85cd-1a98001be0bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273442610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 13.sram_ctrl_stress_all.273442610
Directory /workspace/13.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_pipeline.2463494821
Short name T254
Test name
Test status
Simulation time 20048723665 ps
CPU time 297.58 seconds
Started Apr 23 12:24:09 PM PDT 24
Finished Apr 23 12:29:10 PM PDT 24
Peak memory 201944 kb
Host smart-2526cffa-34f2-47df-b491-2871956bf103
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463494821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.sram_ctrl_stress_pipeline.2463494821
Directory /workspace/13.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.3410398065
Short name T435
Test name
Test status
Simulation time 534343506 ps
CPU time 36.21 seconds
Started Apr 23 12:24:17 PM PDT 24
Finished Apr 23 12:24:54 PM PDT 24
Peak memory 306836 kb
Host smart-0b9610a4-f7e3-40ef-9da6-a79ea649aa7e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410398065 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.sram_ctrl_throughput_w_partial_write.3410398065
Directory /workspace/13.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/14.sram_ctrl_access_during_key_req.1417227104
Short name T386
Test name
Test status
Simulation time 4496863108 ps
CPU time 1078.26 seconds
Started Apr 23 12:24:12 PM PDT 24
Finished Apr 23 12:42:13 PM PDT 24
Peak memory 372176 kb
Host smart-b0d0623f-602e-4674-867a-6e227daa0908
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417227104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.sram_ctrl_access_during_key_req.1417227104
Directory /workspace/14.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/14.sram_ctrl_alert_test.3468131845
Short name T314
Test name
Test status
Simulation time 12148312 ps
CPU time 0.64 seconds
Started Apr 23 12:24:15 PM PDT 24
Finished Apr 23 12:24:17 PM PDT 24
Peak memory 201100 kb
Host smart-b10d64eb-b4ff-4e9e-b9b6-2c4cd87b9266
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468131845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.sram_ctrl_alert_test.3468131845
Directory /workspace/14.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sram_ctrl_bijection.3774249738
Short name T473
Test name
Test status
Simulation time 5351739979 ps
CPU time 74.37 seconds
Started Apr 23 12:24:04 PM PDT 24
Finished Apr 23 12:25:20 PM PDT 24
Peak memory 201928 kb
Host smart-55ccad3c-6593-4e36-877e-ac04560ea7db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774249738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection
.3774249738
Directory /workspace/14.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/14.sram_ctrl_executable.2487223875
Short name T244
Test name
Test status
Simulation time 10478383798 ps
CPU time 469.4 seconds
Started Apr 23 12:24:08 PM PDT 24
Finished Apr 23 12:32:01 PM PDT 24
Peak memory 344136 kb
Host smart-f7b70914-7220-4b2f-89e8-9a5566e5ebff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487223875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executab
le.2487223875
Directory /workspace/14.sram_ctrl_executable/latest

Test location /workspace/coverage/default/14.sram_ctrl_lc_escalation.3915518393
Short name T775
Test name
Test status
Simulation time 1060721708 ps
CPU time 8.85 seconds
Started Apr 23 12:24:31 PM PDT 24
Finished Apr 23 12:24:40 PM PDT 24
Peak memory 201912 kb
Host smart-e2b38460-ed0b-451d-b939-256dd820d1da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915518393 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_es
calation.3915518393
Directory /workspace/14.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/14.sram_ctrl_max_throughput.3259878132
Short name T785
Test name
Test status
Simulation time 92630909 ps
CPU time 25.92 seconds
Started Apr 23 12:24:12 PM PDT 24
Finished Apr 23 12:24:41 PM PDT 24
Peak memory 291580 kb
Host smart-309f561e-e011-4d2f-bfcd-e744276f6290
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259878132 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.sram_ctrl_max_throughput.3259878132
Directory /workspace/14.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_partial_access.3901840408
Short name T107
Test name
Test status
Simulation time 304110585 ps
CPU time 5.23 seconds
Started Apr 23 12:24:11 PM PDT 24
Finished Apr 23 12:24:19 PM PDT 24
Peak memory 210064 kb
Host smart-7822bd78-566d-4388-b918-c7353faa693c
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901840408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.sram_ctrl_mem_partial_access.3901840408
Directory /workspace/14.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_walk.3921867221
Short name T678
Test name
Test status
Simulation time 1325748677 ps
CPU time 9.95 seconds
Started Apr 23 12:24:29 PM PDT 24
Finished Apr 23 12:24:40 PM PDT 24
Peak memory 201784 kb
Host smart-53d5b681-f0f1-4fc3-b358-9ba7c162ea35
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921867221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctr
l_mem_walk.3921867221
Directory /workspace/14.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/14.sram_ctrl_multiple_keys.3811668229
Short name T561
Test name
Test status
Simulation time 29379803691 ps
CPU time 296.42 seconds
Started Apr 23 12:24:08 PM PDT 24
Finished Apr 23 12:29:07 PM PDT 24
Peak memory 358112 kb
Host smart-8488d0bf-a5d4-488b-8ea7-d63feeafc7e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811668229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multi
ple_keys.3811668229
Directory /workspace/14.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access.700447299
Short name T654
Test name
Test status
Simulation time 3167747676 ps
CPU time 17.15 seconds
Started Apr 23 12:24:32 PM PDT 24
Finished Apr 23 12:24:50 PM PDT 24
Peak memory 201976 kb
Host smart-0bb2a1a7-948d-4ff1-bd85-ef15b3fbf490
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700447299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.s
ram_ctrl_partial_access.700447299
Directory /workspace/14.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.3436362169
Short name T345
Test name
Test status
Simulation time 18955501781 ps
CPU time 475.37 seconds
Started Apr 23 12:24:24 PM PDT 24
Finished Apr 23 12:32:20 PM PDT 24
Peak memory 201952 kb
Host smart-13e6ca47-6b99-44ae-a38e-b0d24347bc72
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436362169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 14.sram_ctrl_partial_access_b2b.3436362169
Directory /workspace/14.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/14.sram_ctrl_regwen.3856058713
Short name T21
Test name
Test status
Simulation time 57461540033 ps
CPU time 891.25 seconds
Started Apr 23 12:24:42 PM PDT 24
Finished Apr 23 12:39:34 PM PDT 24
Peak memory 373740 kb
Host smart-989e647a-cd19-49ae-ba91-e8a87fe41dee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856058713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.3856058713
Directory /workspace/14.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/14.sram_ctrl_smoke.4194086261
Short name T109
Test name
Test status
Simulation time 240717252 ps
CPU time 82.52 seconds
Started Apr 23 12:24:10 PM PDT 24
Finished Apr 23 12:25:35 PM PDT 24
Peak memory 336832 kb
Host smart-7f1eabc6-6445-4ca3-9766-de7a2bdc8719
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194086261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.4194086261
Directory /workspace/14.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1861422265
Short name T508
Test name
Test status
Simulation time 9031157504 ps
CPU time 24.33 seconds
Started Apr 23 12:24:07 PM PDT 24
Finished Apr 23 12:24:33 PM PDT 24
Peak memory 226412 kb
Host smart-c0a60cae-35e6-4c23-884f-f5cff9fe6b61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1861422265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.1861422265
Directory /workspace/14.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_pipeline.2787570478
Short name T351
Test name
Test status
Simulation time 15920239458 ps
CPU time 357.28 seconds
Started Apr 23 12:24:04 PM PDT 24
Finished Apr 23 12:30:03 PM PDT 24
Peak memory 201852 kb
Host smart-4e6f05d0-4c56-4c21-a036-7e03e1d8e0b7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787570478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.sram_ctrl_stress_pipeline.2787570478
Directory /workspace/14.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.3011996520
Short name T629
Test name
Test status
Simulation time 62621772 ps
CPU time 5.59 seconds
Started Apr 23 12:24:37 PM PDT 24
Finished Apr 23 12:24:45 PM PDT 24
Peak memory 234448 kb
Host smart-eab2948e-4fe2-4e71-b9c6-f2ec392aac59
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011996520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.3011996520
Directory /workspace/14.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/15.sram_ctrl_access_during_key_req.1195878066
Short name T590
Test name
Test status
Simulation time 2302952311 ps
CPU time 260.88 seconds
Started Apr 23 12:24:31 PM PDT 24
Finished Apr 23 12:28:53 PM PDT 24
Peak memory 341900 kb
Host smart-0a7740f4-77b0-4651-8615-d9fcb529c3a2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195878066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.sram_ctrl_access_during_key_req.1195878066
Directory /workspace/15.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/15.sram_ctrl_alert_test.257550560
Short name T246
Test name
Test status
Simulation time 15114950 ps
CPU time 0.63 seconds
Started Apr 23 12:24:21 PM PDT 24
Finished Apr 23 12:24:23 PM PDT 24
Peak memory 201636 kb
Host smart-086cf7ac-ef87-4920-8afb-52fd734d1ecb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257550560 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.sram_ctrl_alert_test.257550560
Directory /workspace/15.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sram_ctrl_bijection.2645789567
Short name T795
Test name
Test status
Simulation time 471972755 ps
CPU time 14.18 seconds
Started Apr 23 12:24:30 PM PDT 24
Finished Apr 23 12:24:45 PM PDT 24
Peak memory 201908 kb
Host smart-77c1c602-e169-4980-b47b-d830db6106a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645789567 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection
.2645789567
Directory /workspace/15.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/15.sram_ctrl_executable.1299492402
Short name T670
Test name
Test status
Simulation time 52977004381 ps
CPU time 1111.29 seconds
Started Apr 23 12:24:35 PM PDT 24
Finished Apr 23 12:43:09 PM PDT 24
Peak memory 374784 kb
Host smart-9ea5329c-b178-45f2-b7e3-89eada94578c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299492402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executab
le.1299492402
Directory /workspace/15.sram_ctrl_executable/latest

Test location /workspace/coverage/default/15.sram_ctrl_lc_escalation.1673596099
Short name T783
Test name
Test status
Simulation time 617828196 ps
CPU time 4.99 seconds
Started Apr 23 12:24:10 PM PDT 24
Finished Apr 23 12:24:17 PM PDT 24
Peak memory 201880 kb
Host smart-1e64f707-6ad8-43a8-907f-eb436ac9cb8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673596099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_es
calation.1673596099
Directory /workspace/15.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/15.sram_ctrl_max_throughput.2501599591
Short name T143
Test name
Test status
Simulation time 139157891 ps
CPU time 125.4 seconds
Started Apr 23 12:24:11 PM PDT 24
Finished Apr 23 12:26:19 PM PDT 24
Peak memory 368128 kb
Host smart-d5f9180a-4d56-4582-b21c-239d101af89b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501599591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.sram_ctrl_max_throughput.2501599591
Directory /workspace/15.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_partial_access.2032898418
Short name T819
Test name
Test status
Simulation time 341603209 ps
CPU time 3.05 seconds
Started Apr 23 12:24:11 PM PDT 24
Finished Apr 23 12:24:17 PM PDT 24
Peak memory 210088 kb
Host smart-1ab7f491-db27-4bd0-94cc-b6a953624f26
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032898418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.sram_ctrl_mem_partial_access.2032898418
Directory /workspace/15.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_walk.26821710
Short name T380
Test name
Test status
Simulation time 340977219 ps
CPU time 5.21 seconds
Started Apr 23 12:24:16 PM PDT 24
Finished Apr 23 12:24:22 PM PDT 24
Peak memory 201792 kb
Host smart-bd5e40ef-ae45-4297-aa62-7eb4a26e9eb8
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26821710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr
am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_
mem_walk.26821710
Directory /workspace/15.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/15.sram_ctrl_multiple_keys.693812123
Short name T805
Test name
Test status
Simulation time 41374181209 ps
CPU time 738.46 seconds
Started Apr 23 12:24:15 PM PDT 24
Finished Apr 23 12:36:35 PM PDT 24
Peak memory 363556 kb
Host smart-503783d0-07ad-45de-80b4-74380f78b322
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693812123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multip
le_keys.693812123
Directory /workspace/15.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access.595511977
Short name T238
Test name
Test status
Simulation time 11269054019 ps
CPU time 11.49 seconds
Started Apr 23 12:24:19 PM PDT 24
Finished Apr 23 12:24:31 PM PDT 24
Peak memory 201884 kb
Host smart-5b6025ad-4037-449c-ba86-fe5968779f89
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595511977 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.s
ram_ctrl_partial_access.595511977
Directory /workspace/15.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.2532424396
Short name T470
Test name
Test status
Simulation time 37841559699 ps
CPU time 198.82 seconds
Started Apr 23 12:24:30 PM PDT 24
Finished Apr 23 12:27:50 PM PDT 24
Peak memory 201876 kb
Host smart-341b1bdf-3812-4503-86a0-32b8814970e8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532424396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 15.sram_ctrl_partial_access_b2b.2532424396
Directory /workspace/15.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/15.sram_ctrl_ram_cfg.3947599634
Short name T833
Test name
Test status
Simulation time 49955087 ps
CPU time 0.77 seconds
Started Apr 23 12:24:35 PM PDT 24
Finished Apr 23 12:24:37 PM PDT 24
Peak memory 201980 kb
Host smart-343c5808-8597-49ee-b863-57f41d3bbea6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947599634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.3947599634
Directory /workspace/15.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/15.sram_ctrl_regwen.1400762333
Short name T283
Test name
Test status
Simulation time 50618666174 ps
CPU time 1138.52 seconds
Started Apr 23 12:24:29 PM PDT 24
Finished Apr 23 12:43:29 PM PDT 24
Peak memory 373676 kb
Host smart-8f42b6f1-e395-44a9-89a7-5cc278da026f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400762333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.1400762333
Directory /workspace/15.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/15.sram_ctrl_smoke.330477172
Short name T336
Test name
Test status
Simulation time 1447034640 ps
CPU time 25.17 seconds
Started Apr 23 12:24:24 PM PDT 24
Finished Apr 23 12:24:49 PM PDT 24
Peak memory 285936 kb
Host smart-d5e9b557-e3b3-4004-aee3-c5d9c17885d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330477172 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.330477172
Directory /workspace/15.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_all.1109035591
Short name T177
Test name
Test status
Simulation time 119412872131 ps
CPU time 2729.93 seconds
Started Apr 23 12:24:25 PM PDT 24
Finished Apr 23 01:09:56 PM PDT 24
Peak memory 373720 kb
Host smart-87314eba-c85c-4483-b47b-9989602fffc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109035591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 15.sram_ctrl_stress_all.1109035591
Directory /workspace/15.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3173599754
Short name T45
Test name
Test status
Simulation time 532901439 ps
CPU time 14.32 seconds
Started Apr 23 12:24:19 PM PDT 24
Finished Apr 23 12:24:34 PM PDT 24
Peak memory 210144 kb
Host smart-5a210e14-2dfe-4fc4-b7f2-60284f33121c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3173599754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.3173599754
Directory /workspace/15.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_pipeline.3119096698
Short name T607
Test name
Test status
Simulation time 5734530035 ps
CPU time 272.22 seconds
Started Apr 23 12:24:15 PM PDT 24
Finished Apr 23 12:28:49 PM PDT 24
Peak memory 201920 kb
Host smart-48e65cae-e467-4213-9fda-514c05112165
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119096698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.sram_ctrl_stress_pipeline.3119096698
Directory /workspace/15.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.2740891272
Short name T547
Test name
Test status
Simulation time 157079130 ps
CPU time 13.81 seconds
Started Apr 23 12:24:14 PM PDT 24
Finished Apr 23 12:24:29 PM PDT 24
Peak memory 261104 kb
Host smart-f8c323a2-4e15-41b3-83fe-f43ac03ff4ce
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740891272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.sram_ctrl_throughput_w_partial_write.2740891272
Directory /workspace/15.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/16.sram_ctrl_access_during_key_req.1709353431
Short name T668
Test name
Test status
Simulation time 2985715181 ps
CPU time 396.78 seconds
Started Apr 23 12:24:09 PM PDT 24
Finished Apr 23 12:30:48 PM PDT 24
Peak memory 366692 kb
Host smart-2f886aa0-5106-4bed-9f74-48fe084bf041
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709353431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.sram_ctrl_access_during_key_req.1709353431
Directory /workspace/16.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/16.sram_ctrl_alert_test.111632823
Short name T413
Test name
Test status
Simulation time 33675569 ps
CPU time 0.62 seconds
Started Apr 23 12:24:10 PM PDT 24
Finished Apr 23 12:24:13 PM PDT 24
Peak memory 201072 kb
Host smart-670da354-bbf9-4559-9c9d-66dddc4e6fd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111632823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.sram_ctrl_alert_test.111632823
Directory /workspace/16.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sram_ctrl_bijection.1893536840
Short name T165
Test name
Test status
Simulation time 1970742376 ps
CPU time 58.1 seconds
Started Apr 23 12:24:36 PM PDT 24
Finished Apr 23 12:25:37 PM PDT 24
Peak memory 201864 kb
Host smart-ca455067-99b9-411c-a9c2-d9a7f7f9d15a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893536840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection
.1893536840
Directory /workspace/16.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/16.sram_ctrl_executable.2715209806
Short name T130
Test name
Test status
Simulation time 11244290999 ps
CPU time 1158.62 seconds
Started Apr 23 12:24:17 PM PDT 24
Finished Apr 23 12:43:36 PM PDT 24
Peak memory 371776 kb
Host smart-72f9d058-71b8-4ba1-a2d5-6eb53414539b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715209806 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executab
le.2715209806
Directory /workspace/16.sram_ctrl_executable/latest

Test location /workspace/coverage/default/16.sram_ctrl_lc_escalation.1617698630
Short name T746
Test name
Test status
Simulation time 1898910930 ps
CPU time 3.32 seconds
Started Apr 23 12:24:23 PM PDT 24
Finished Apr 23 12:24:27 PM PDT 24
Peak memory 201872 kb
Host smart-323f4109-d69b-45c6-9709-2acdb4d8ed82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617698630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_es
calation.1617698630
Directory /workspace/16.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/16.sram_ctrl_max_throughput.1825911423
Short name T449
Test name
Test status
Simulation time 176753786 ps
CPU time 110.73 seconds
Started Apr 23 12:24:41 PM PDT 24
Finished Apr 23 12:26:33 PM PDT 24
Peak memory 368092 kb
Host smart-00bb88a7-50da-4835-b40f-6a73a9d3d814
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825911423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.sram_ctrl_max_throughput.1825911423
Directory /workspace/16.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_partial_access.3166660322
Short name T431
Test name
Test status
Simulation time 356471281 ps
CPU time 3.93 seconds
Started Apr 23 12:24:36 PM PDT 24
Finished Apr 23 12:24:42 PM PDT 24
Peak memory 209964 kb
Host smart-bcda3986-2022-415d-b1b3-326d128fd72b
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166660322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.sram_ctrl_mem_partial_access.3166660322
Directory /workspace/16.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_walk.618493468
Short name T626
Test name
Test status
Simulation time 687424069 ps
CPU time 9.65 seconds
Started Apr 23 12:24:42 PM PDT 24
Finished Apr 23 12:24:52 PM PDT 24
Peak memory 201760 kb
Host smart-2c4c143a-0c93-48ea-b488-6144c47310c1
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618493468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl
_mem_walk.618493468
Directory /workspace/16.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/16.sram_ctrl_multiple_keys.570258100
Short name T585
Test name
Test status
Simulation time 20096957335 ps
CPU time 1635.69 seconds
Started Apr 23 12:24:26 PM PDT 24
Finished Apr 23 12:51:42 PM PDT 24
Peak memory 368676 kb
Host smart-ba9b7b87-36d9-4da2-b2e4-a80e482fcc2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570258100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multip
le_keys.570258100
Directory /workspace/16.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access.2973962913
Short name T222
Test name
Test status
Simulation time 10649847655 ps
CPU time 12.75 seconds
Started Apr 23 12:24:31 PM PDT 24
Finished Apr 23 12:24:45 PM PDT 24
Peak memory 201892 kb
Host smart-a1bae666-381b-492c-bf87-97e9ec38b631
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973962913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
sram_ctrl_partial_access.2973962913
Directory /workspace/16.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.11532696
Short name T395
Test name
Test status
Simulation time 16763051761 ps
CPU time 315.58 seconds
Started Apr 23 12:24:26 PM PDT 24
Finished Apr 23 12:29:42 PM PDT 24
Peak memory 201912 kb
Host smart-b0e4a236-2025-4fa6-9188-591cd904c56f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11532696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.sram_ctrl_partial_access_b2b.11532696
Directory /workspace/16.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/16.sram_ctrl_ram_cfg.2945613060
Short name T382
Test name
Test status
Simulation time 43421299 ps
CPU time 0.77 seconds
Started Apr 23 12:24:15 PM PDT 24
Finished Apr 23 12:24:18 PM PDT 24
Peak memory 201916 kb
Host smart-5045ec3d-4b9f-4e85-a7c0-5954a7632719
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945613060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.2945613060
Directory /workspace/16.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/16.sram_ctrl_regwen.3644262125
Short name T250
Test name
Test status
Simulation time 67102304506 ps
CPU time 1045.07 seconds
Started Apr 23 12:24:09 PM PDT 24
Finished Apr 23 12:41:37 PM PDT 24
Peak memory 371068 kb
Host smart-af198ec3-7926-454c-a407-9d11d648a6f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644262125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.3644262125
Directory /workspace/16.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/16.sram_ctrl_smoke.2500257536
Short name T352
Test name
Test status
Simulation time 306038296 ps
CPU time 24.31 seconds
Started Apr 23 12:24:16 PM PDT 24
Finished Apr 23 12:24:41 PM PDT 24
Peak memory 286108 kb
Host smart-6547466e-156e-46d9-8bf1-12b2e553cca0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500257536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.2500257536
Directory /workspace/16.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_all.174567297
Short name T510
Test name
Test status
Simulation time 60431874021 ps
CPU time 931.75 seconds
Started Apr 23 12:24:23 PM PDT 24
Finished Apr 23 12:39:55 PM PDT 24
Peak memory 372556 kb
Host smart-7bcc3423-9bf2-4867-829a-7d66e594cfe9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174567297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 16.sram_ctrl_stress_all.174567297
Directory /workspace/16.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.3907552956
Short name T224
Test name
Test status
Simulation time 3204772387 ps
CPU time 145.58 seconds
Started Apr 23 12:24:23 PM PDT 24
Finished Apr 23 12:26:49 PM PDT 24
Peak memory 318112 kb
Host smart-594946ac-77c4-4768-9a2c-98adefd382c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3907552956 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.3907552956
Directory /workspace/16.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_pipeline.3536693927
Short name T587
Test name
Test status
Simulation time 28217619864 ps
CPU time 232.72 seconds
Started Apr 23 12:24:15 PM PDT 24
Finished Apr 23 12:28:09 PM PDT 24
Peak memory 201944 kb
Host smart-efee6e59-7743-42dd-aa91-aa6888aeb036
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536693927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.sram_ctrl_stress_pipeline.3536693927
Directory /workspace/16.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.60865226
Short name T296
Test name
Test status
Simulation time 127396277 ps
CPU time 44.97 seconds
Started Apr 23 12:24:12 PM PDT 24
Finished Apr 23 12:24:59 PM PDT 24
Peak memory 315124 kb
Host smart-93a5295b-b104-43c3-84f3-ebe841a102a8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60865226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.sram_ctrl_throughput_w_partial_write.60865226
Directory /workspace/16.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/17.sram_ctrl_access_during_key_req.1663805357
Short name T242
Test name
Test status
Simulation time 5044393525 ps
CPU time 777.57 seconds
Started Apr 23 12:24:21 PM PDT 24
Finished Apr 23 12:37:20 PM PDT 24
Peak memory 353308 kb
Host smart-6ddc8c6f-0fad-43a2-92c5-08058b812b02
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663805357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.sram_ctrl_access_during_key_req.1663805357
Directory /workspace/17.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/17.sram_ctrl_alert_test.2937279077
Short name T864
Test name
Test status
Simulation time 13607000 ps
CPU time 0.6 seconds
Started Apr 23 12:24:33 PM PDT 24
Finished Apr 23 12:24:34 PM PDT 24
Peak memory 201684 kb
Host smart-859b860a-8fb4-4d5a-b58e-5996aa4936ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937279077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.sram_ctrl_alert_test.2937279077
Directory /workspace/17.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sram_ctrl_bijection.1302173825
Short name T665
Test name
Test status
Simulation time 6057882897 ps
CPU time 46.37 seconds
Started Apr 23 12:24:11 PM PDT 24
Finished Apr 23 12:25:04 PM PDT 24
Peak memory 201944 kb
Host smart-11d36a4b-0a6d-471a-b16e-b1cb2a0bdc75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302173825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection
.1302173825
Directory /workspace/17.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/17.sram_ctrl_executable.2362662023
Short name T787
Test name
Test status
Simulation time 29805892499 ps
CPU time 1467.66 seconds
Started Apr 23 12:24:24 PM PDT 24
Finished Apr 23 12:48:53 PM PDT 24
Peak memory 372264 kb
Host smart-8badd48d-8760-4dce-aa2c-f3dc7b979c44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362662023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executab
le.2362662023
Directory /workspace/17.sram_ctrl_executable/latest

Test location /workspace/coverage/default/17.sram_ctrl_lc_escalation.750798969
Short name T885
Test name
Test status
Simulation time 929503979 ps
CPU time 5.29 seconds
Started Apr 23 12:24:35 PM PDT 24
Finished Apr 23 12:24:42 PM PDT 24
Peak memory 201932 kb
Host smart-ceb2a6e9-61a0-43a6-8f69-2cdcebb1e803
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750798969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_esc
alation.750798969
Directory /workspace/17.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/17.sram_ctrl_max_throughput.3900297343
Short name T263
Test name
Test status
Simulation time 155150928 ps
CPU time 82.42 seconds
Started Apr 23 12:24:29 PM PDT 24
Finished Apr 23 12:25:52 PM PDT 24
Peak memory 368412 kb
Host smart-eaf3aa39-18da-48c3-8056-8ccd710ea5af
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900297343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.sram_ctrl_max_throughput.3900297343
Directory /workspace/17.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_partial_access.1968813412
Short name T181
Test name
Test status
Simulation time 120496435 ps
CPU time 2.66 seconds
Started Apr 23 12:24:48 PM PDT 24
Finished Apr 23 12:24:51 PM PDT 24
Peak memory 210020 kb
Host smart-56f597f6-5310-4658-ae9b-337442e685c2
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968813412 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.sram_ctrl_mem_partial_access.1968813412
Directory /workspace/17.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_walk.2808270286
Short name T860
Test name
Test status
Simulation time 873200286 ps
CPU time 8.84 seconds
Started Apr 23 12:24:38 PM PDT 24
Finished Apr 23 12:24:49 PM PDT 24
Peak memory 201784 kb
Host smart-1dfb8bef-025d-4e58-a667-d3440b04270f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808270286 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctr
l_mem_walk.2808270286
Directory /workspace/17.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/17.sram_ctrl_multiple_keys.898119757
Short name T704
Test name
Test status
Simulation time 4297980130 ps
CPU time 899.39 seconds
Started Apr 23 12:24:10 PM PDT 24
Finished Apr 23 12:39:12 PM PDT 24
Peak memory 371672 kb
Host smart-88edc9e8-a3de-4ca8-8f40-5442f1cd6dd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898119757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multip
le_keys.898119757
Directory /workspace/17.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access.71463203
Short name T135
Test name
Test status
Simulation time 225925851 ps
CPU time 148.56 seconds
Started Apr 23 12:24:18 PM PDT 24
Finished Apr 23 12:26:48 PM PDT 24
Peak memory 368096 kb
Host smart-bb6e819c-ce3e-4145-8b4b-599146b360e0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71463203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sr
am_ctrl_partial_access.71463203
Directory /workspace/17.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.2664281472
Short name T829
Test name
Test status
Simulation time 20859403995 ps
CPU time 391.28 seconds
Started Apr 23 12:24:27 PM PDT 24
Finished Apr 23 12:30:59 PM PDT 24
Peak memory 201884 kb
Host smart-0dff5429-3645-4650-b923-f0f95b5d8898
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664281472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 17.sram_ctrl_partial_access_b2b.2664281472
Directory /workspace/17.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/17.sram_ctrl_ram_cfg.769058489
Short name T583
Test name
Test status
Simulation time 29867897 ps
CPU time 0.77 seconds
Started Apr 23 12:24:10 PM PDT 24
Finished Apr 23 12:24:13 PM PDT 24
Peak memory 202148 kb
Host smart-b2ebe525-1eee-4c30-944f-6b477bcbda97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769058489 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.769058489
Directory /workspace/17.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/17.sram_ctrl_regwen.4277153932
Short name T565
Test name
Test status
Simulation time 78642461217 ps
CPU time 1634.19 seconds
Started Apr 23 12:24:33 PM PDT 24
Finished Apr 23 12:51:48 PM PDT 24
Peak memory 374092 kb
Host smart-baaaf531-e3a8-473e-9e24-7992a2e169c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277153932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.4277153932
Directory /workspace/17.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/17.sram_ctrl_smoke.1871309962
Short name T466
Test name
Test status
Simulation time 73392316 ps
CPU time 1.66 seconds
Started Apr 23 12:24:28 PM PDT 24
Finished Apr 23 12:24:30 PM PDT 24
Peak memory 201884 kb
Host smart-05543a4c-d4c1-428f-a9e9-0724b30af0b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871309962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.1871309962
Directory /workspace/17.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_all.567858925
Short name T372
Test name
Test status
Simulation time 12675303574 ps
CPU time 1973.29 seconds
Started Apr 23 12:24:35 PM PDT 24
Finished Apr 23 12:57:30 PM PDT 24
Peak memory 374736 kb
Host smart-35152a4c-04d9-464c-bc41-3223b4aa72d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567858925 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 17.sram_ctrl_stress_all.567858925
Directory /workspace/17.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.4000480753
Short name T359
Test name
Test status
Simulation time 1432134440 ps
CPU time 391.99 seconds
Started Apr 23 12:24:33 PM PDT 24
Finished Apr 23 12:31:07 PM PDT 24
Peak memory 377292 kb
Host smart-5f44687c-545b-4d1c-a9be-d35a1c3a70c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4000480753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.4000480753
Directory /workspace/17.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_pipeline.2355499255
Short name T658
Test name
Test status
Simulation time 11625106819 ps
CPU time 269.51 seconds
Started Apr 23 12:24:52 PM PDT 24
Finished Apr 23 12:29:23 PM PDT 24
Peak memory 201916 kb
Host smart-63609da4-7ae8-482d-9851-218fb37515c6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355499255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.sram_ctrl_stress_pipeline.2355499255
Directory /workspace/17.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.915409917
Short name T839
Test name
Test status
Simulation time 345372598 ps
CPU time 21.52 seconds
Started Apr 23 12:24:35 PM PDT 24
Finished Apr 23 12:24:58 PM PDT 24
Peak memory 273612 kb
Host smart-4c036b5d-b149-4e19-87c2-481c57f4250c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915409917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.sram_ctrl_throughput_w_partial_write.915409917
Directory /workspace/17.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/18.sram_ctrl_alert_test.1628614855
Short name T609
Test name
Test status
Simulation time 42117411 ps
CPU time 0.63 seconds
Started Apr 23 12:24:35 PM PDT 24
Finished Apr 23 12:24:38 PM PDT 24
Peak memory 201072 kb
Host smart-1a4622c6-92ca-4f94-a5f9-fc4e331dce82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628614855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.sram_ctrl_alert_test.1628614855
Directory /workspace/18.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sram_ctrl_bijection.1014560208
Short name T901
Test name
Test status
Simulation time 4074708153 ps
CPU time 64.47 seconds
Started Apr 23 12:24:35 PM PDT 24
Finished Apr 23 12:25:41 PM PDT 24
Peak memory 201892 kb
Host smart-f4b10cd8-d3a9-4848-8b8e-3e39ef81aee0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014560208 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection
.1014560208
Directory /workspace/18.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/18.sram_ctrl_executable.3198822258
Short name T687
Test name
Test status
Simulation time 19927438706 ps
CPU time 929.5 seconds
Started Apr 23 12:24:35 PM PDT 24
Finished Apr 23 12:40:06 PM PDT 24
Peak memory 365520 kb
Host smart-4d82eaf6-c318-4ac5-bb1c-fcbe644418c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198822258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executab
le.3198822258
Directory /workspace/18.sram_ctrl_executable/latest

Test location /workspace/coverage/default/18.sram_ctrl_lc_escalation.469363152
Short name T31
Test name
Test status
Simulation time 3235616380 ps
CPU time 8.17 seconds
Started Apr 23 12:24:26 PM PDT 24
Finished Apr 23 12:24:35 PM PDT 24
Peak memory 213588 kb
Host smart-6316e965-7da5-4945-a746-8190944f44a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469363152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_esc
alation.469363152
Directory /workspace/18.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/18.sram_ctrl_max_throughput.3264496523
Short name T300
Test name
Test status
Simulation time 106022738 ps
CPU time 2.79 seconds
Started Apr 23 12:24:32 PM PDT 24
Finished Apr 23 12:24:36 PM PDT 24
Peak memory 218332 kb
Host smart-fd93ba65-07cd-4db9-abfc-2e2a70f898cf
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264496523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 18.sram_ctrl_max_throughput.3264496523
Directory /workspace/18.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_partial_access.2499502863
Short name T661
Test name
Test status
Simulation time 181101247 ps
CPU time 4.88 seconds
Started Apr 23 12:24:32 PM PDT 24
Finished Apr 23 12:24:38 PM PDT 24
Peak memory 210104 kb
Host smart-37d54852-9a4c-44e7-8e94-aa2ff2f08baa
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499502863 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.sram_ctrl_mem_partial_access.2499502863
Directory /workspace/18.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_walk.172024836
Short name T582
Test name
Test status
Simulation time 878730462 ps
CPU time 8.81 seconds
Started Apr 23 12:24:31 PM PDT 24
Finished Apr 23 12:24:41 PM PDT 24
Peak memory 201800 kb
Host smart-a0a139ea-bf58-44e3-a526-f72eeb7ac57b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172024836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl
_mem_walk.172024836
Directory /workspace/18.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/18.sram_ctrl_multiple_keys.3935711334
Short name T275
Test name
Test status
Simulation time 15539288813 ps
CPU time 1646.87 seconds
Started Apr 23 12:24:34 PM PDT 24
Finished Apr 23 12:52:02 PM PDT 24
Peak memory 374804 kb
Host smart-fe4d67ac-846a-419e-b5c1-a88f44774bc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935711334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multi
ple_keys.3935711334
Directory /workspace/18.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access.2070985569
Short name T156
Test name
Test status
Simulation time 313450860 ps
CPU time 14.84 seconds
Started Apr 23 12:24:48 PM PDT 24
Finished Apr 23 12:25:04 PM PDT 24
Peak memory 201772 kb
Host smart-c41147d1-6aeb-4306-9866-906a295831e2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070985569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
sram_ctrl_partial_access.2070985569
Directory /workspace/18.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.2635741204
Short name T467
Test name
Test status
Simulation time 39387083415 ps
CPU time 232.78 seconds
Started Apr 23 12:24:51 PM PDT 24
Finished Apr 23 12:28:46 PM PDT 24
Peak memory 201828 kb
Host smart-8c6fad1a-735f-4609-bd1d-10b0fc9807da
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635741204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 18.sram_ctrl_partial_access_b2b.2635741204
Directory /workspace/18.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/18.sram_ctrl_ram_cfg.1186027449
Short name T428
Test name
Test status
Simulation time 86598197 ps
CPU time 0.73 seconds
Started Apr 23 12:24:34 PM PDT 24
Finished Apr 23 12:24:37 PM PDT 24
Peak memory 201928 kb
Host smart-e6c352b3-9110-470a-84cb-6868bfe6da65
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186027449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.1186027449
Directory /workspace/18.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/18.sram_ctrl_regwen.2332171431
Short name T916
Test name
Test status
Simulation time 20718963920 ps
CPU time 509.19 seconds
Started Apr 23 12:24:37 PM PDT 24
Finished Apr 23 12:33:08 PM PDT 24
Peak memory 370980 kb
Host smart-ff3197da-2d21-41d1-9c3e-bc0009abcfe0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332171431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.2332171431
Directory /workspace/18.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/18.sram_ctrl_smoke.2009121215
Short name T569
Test name
Test status
Simulation time 1081696145 ps
CPU time 126.06 seconds
Started Apr 23 12:24:45 PM PDT 24
Finished Apr 23 12:26:52 PM PDT 24
Peak memory 366084 kb
Host smart-43125c89-3c29-40fd-829d-bee3332faeb2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009121215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.2009121215
Directory /workspace/18.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_all.2079468808
Short name T679
Test name
Test status
Simulation time 55530557061 ps
CPU time 2504.16 seconds
Started Apr 23 12:24:29 PM PDT 24
Finished Apr 23 01:06:15 PM PDT 24
Peak memory 373716 kb
Host smart-50150893-bbe2-4017-bdc2-2042356e30db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079468808 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 18.sram_ctrl_stress_all.2079468808
Directory /workspace/18.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.3422143976
Short name T101
Test name
Test status
Simulation time 902249251 ps
CPU time 11.74 seconds
Started Apr 23 12:24:35 PM PDT 24
Finished Apr 23 12:24:49 PM PDT 24
Peak memory 210184 kb
Host smart-bc7ec46f-712f-41c3-820a-cc261cf48549
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3422143976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.3422143976
Directory /workspace/18.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_pipeline.3785939038
Short name T366
Test name
Test status
Simulation time 8302112995 ps
CPU time 199.22 seconds
Started Apr 23 12:24:34 PM PDT 24
Finished Apr 23 12:27:56 PM PDT 24
Peak memory 201884 kb
Host smart-e269a98d-90ef-4df6-89d8-22f7ff5fac4b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785939038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.sram_ctrl_stress_pipeline.3785939038
Directory /workspace/18.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.1021745739
Short name T559
Test name
Test status
Simulation time 288984979 ps
CPU time 6.42 seconds
Started Apr 23 12:24:21 PM PDT 24
Finished Apr 23 12:24:28 PM PDT 24
Peak memory 234664 kb
Host smart-1056f440-1c81-4b57-8965-ea4f733eb5d0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021745739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.sram_ctrl_throughput_w_partial_write.1021745739
Directory /workspace/18.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/19.sram_ctrl_access_during_key_req.3780103422
Short name T635
Test name
Test status
Simulation time 6247752111 ps
CPU time 458.26 seconds
Started Apr 23 12:24:34 PM PDT 24
Finished Apr 23 12:32:15 PM PDT 24
Peak memory 363588 kb
Host smart-3e9f0a6d-8445-49fc-9e1f-c1ebb01c3a1b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780103422 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.sram_ctrl_access_during_key_req.3780103422
Directory /workspace/19.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/19.sram_ctrl_alert_test.816413591
Short name T925
Test name
Test status
Simulation time 12656890 ps
CPU time 0.62 seconds
Started Apr 23 12:24:51 PM PDT 24
Finished Apr 23 12:24:53 PM PDT 24
Peak memory 200800 kb
Host smart-e5b762bc-a8a1-4dad-8108-705c608cabfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816413591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.sram_ctrl_alert_test.816413591
Directory /workspace/19.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sram_ctrl_bijection.717758695
Short name T396
Test name
Test status
Simulation time 2248813507 ps
CPU time 55.72 seconds
Started Apr 23 12:24:24 PM PDT 24
Finished Apr 23 12:25:20 PM PDT 24
Peak memory 201996 kb
Host smart-eb9a3cf1-b44b-4b87-92f0-881bb5e40698
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717758695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection.
717758695
Directory /workspace/19.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/19.sram_ctrl_executable.2479915453
Short name T503
Test name
Test status
Simulation time 3296288220 ps
CPU time 168.07 seconds
Started Apr 23 12:24:27 PM PDT 24
Finished Apr 23 12:27:16 PM PDT 24
Peak memory 327836 kb
Host smart-c3c12dff-d838-472d-a60a-3cb120b2d2e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479915453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executab
le.2479915453
Directory /workspace/19.sram_ctrl_executable/latest

Test location /workspace/coverage/default/19.sram_ctrl_lc_escalation.2085968688
Short name T459
Test name
Test status
Simulation time 455038426 ps
CPU time 6.43 seconds
Started Apr 23 12:24:23 PM PDT 24
Finished Apr 23 12:24:30 PM PDT 24
Peak memory 201912 kb
Host smart-a652ac33-794b-447d-b6e3-ab4ff731887b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085968688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_es
calation.2085968688
Directory /workspace/19.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/19.sram_ctrl_max_throughput.3449298989
Short name T202
Test name
Test status
Simulation time 94053957 ps
CPU time 21.54 seconds
Started Apr 23 12:24:40 PM PDT 24
Finished Apr 23 12:25:03 PM PDT 24
Peak memory 287748 kb
Host smart-aa856314-6ca4-474f-a893-4791063d60fd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449298989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.sram_ctrl_max_throughput.3449298989
Directory /workspace/19.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_partial_access.4235815302
Short name T549
Test name
Test status
Simulation time 87666103 ps
CPU time 2.75 seconds
Started Apr 23 12:24:34 PM PDT 24
Finished Apr 23 12:24:38 PM PDT 24
Peak memory 210040 kb
Host smart-c4c40f67-2d5d-40ed-8b7e-cc4df6f471f7
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235815302 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.sram_ctrl_mem_partial_access.4235815302
Directory /workspace/19.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_walk.2782367294
Short name T425
Test name
Test status
Simulation time 125533227 ps
CPU time 4.14 seconds
Started Apr 23 12:24:33 PM PDT 24
Finished Apr 23 12:24:38 PM PDT 24
Peak memory 201840 kb
Host smart-422fb2ef-80f5-4c85-bd8d-0ea5790ed69b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782367294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctr
l_mem_walk.2782367294
Directory /workspace/19.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/19.sram_ctrl_multiple_keys.2947272184
Short name T558
Test name
Test status
Simulation time 2969849438 ps
CPU time 1187.78 seconds
Started Apr 23 12:24:52 PM PDT 24
Finished Apr 23 12:44:41 PM PDT 24
Peak memory 372752 kb
Host smart-11aedef5-d2d2-4258-9c70-9e8436d02c2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947272184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multi
ple_keys.2947272184
Directory /workspace/19.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access.45123094
Short name T815
Test name
Test status
Simulation time 4787638839 ps
CPU time 17.47 seconds
Started Apr 23 12:24:25 PM PDT 24
Finished Apr 23 12:24:43 PM PDT 24
Peak memory 262260 kb
Host smart-86fa425a-8498-4d44-b860-49a9f2510a7b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45123094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sr
am_ctrl_partial_access.45123094
Directory /workspace/19.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.3469434368
Short name T732
Test name
Test status
Simulation time 11941308860 ps
CPU time 245.68 seconds
Started Apr 23 12:24:36 PM PDT 24
Finished Apr 23 12:28:44 PM PDT 24
Peak memory 201900 kb
Host smart-fd47915f-ef1e-492d-a99c-725464c545b9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469434368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 19.sram_ctrl_partial_access_b2b.3469434368
Directory /workspace/19.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/19.sram_ctrl_ram_cfg.2621969321
Short name T504
Test name
Test status
Simulation time 78989935 ps
CPU time 0.74 seconds
Started Apr 23 12:24:36 PM PDT 24
Finished Apr 23 12:24:39 PM PDT 24
Peak memory 201904 kb
Host smart-9ca37a52-7f86-4ddd-b337-137dcc026236
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621969321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.2621969321
Directory /workspace/19.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/19.sram_ctrl_regwen.4197001545
Short name T875
Test name
Test status
Simulation time 12258863348 ps
CPU time 256.45 seconds
Started Apr 23 12:24:52 PM PDT 24
Finished Apr 23 12:29:11 PM PDT 24
Peak memory 365932 kb
Host smart-2677ffef-1bb8-46cb-9762-a9bb228a2f97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197001545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.4197001545
Directory /workspace/19.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/19.sram_ctrl_smoke.2840005437
Short name T915
Test name
Test status
Simulation time 5512361451 ps
CPU time 80.11 seconds
Started Apr 23 12:24:48 PM PDT 24
Finished Apr 23 12:26:10 PM PDT 24
Peak memory 336652 kb
Host smart-b933042c-e933-4fa2-b05d-30432d946947
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840005437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.2840005437
Directory /workspace/19.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_all.226181772
Short name T603
Test name
Test status
Simulation time 7374617687 ps
CPU time 1341.84 seconds
Started Apr 23 12:24:34 PM PDT 24
Finished Apr 23 12:46:58 PM PDT 24
Peak memory 373616 kb
Host smart-4bd33a87-2537-40b2-a059-06dc8ced4d29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226181772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 19.sram_ctrl_stress_all.226181772
Directory /workspace/19.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3794782910
Short name T387
Test name
Test status
Simulation time 2035597506 ps
CPU time 248.34 seconds
Started Apr 23 12:24:53 PM PDT 24
Finished Apr 23 12:29:04 PM PDT 24
Peak memory 348172 kb
Host smart-5af6b0b5-6646-4b56-b78b-ccbd30ccf02b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3794782910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.3794782910
Directory /workspace/19.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_pipeline.2416185340
Short name T327
Test name
Test status
Simulation time 30133477546 ps
CPU time 328.43 seconds
Started Apr 23 12:24:47 PM PDT 24
Finished Apr 23 12:30:17 PM PDT 24
Peak memory 201904 kb
Host smart-3a5288ca-9e4c-4d34-b2db-36f47941ecbd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416185340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.sram_ctrl_stress_pipeline.2416185340
Directory /workspace/19.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.196006785
Short name T608
Test name
Test status
Simulation time 101279428 ps
CPU time 23.87 seconds
Started Apr 23 12:24:31 PM PDT 24
Finished Apr 23 12:24:56 PM PDT 24
Peak memory 283672 kb
Host smart-2dc2e197-e086-42c5-982b-220aa4153c3b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196006785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.sram_ctrl_throughput_w_partial_write.196006785
Directory /workspace/19.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/2.sram_ctrl_access_during_key_req.1330930499
Short name T762
Test name
Test status
Simulation time 321493782 ps
CPU time 21.78 seconds
Started Apr 23 12:23:29 PM PDT 24
Finished Apr 23 12:23:53 PM PDT 24
Peak memory 270512 kb
Host smart-a404f585-4f46-45b7-babf-70cdb6fcd4f9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330930499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.sram_ctrl_access_during_key_req.1330930499
Directory /workspace/2.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/2.sram_ctrl_alert_test.1699614403
Short name T636
Test name
Test status
Simulation time 91014559 ps
CPU time 0.63 seconds
Started Apr 23 12:23:55 PM PDT 24
Finished Apr 23 12:23:57 PM PDT 24
Peak memory 201456 kb
Host smart-2f501fcd-3fac-44dc-b792-9827f2a406a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699614403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_alert_test.1699614403
Directory /workspace/2.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sram_ctrl_bijection.3852277991
Short name T401
Test name
Test status
Simulation time 4458899529 ps
CPU time 43.95 seconds
Started Apr 23 12:23:57 PM PDT 24
Finished Apr 23 12:24:43 PM PDT 24
Peak memory 201236 kb
Host smart-43fdef34-1fb4-4529-be19-4e27aab250fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852277991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.
3852277991
Directory /workspace/2.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/2.sram_ctrl_lc_escalation.841930811
Short name T708
Test name
Test status
Simulation time 1287713374 ps
CPU time 7.21 seconds
Started Apr 23 12:23:31 PM PDT 24
Finished Apr 23 12:23:39 PM PDT 24
Peak memory 201700 kb
Host smart-3611e6d1-f7d5-4b22-a88c-8d05575603ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841930811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_esca
lation.841930811
Directory /workspace/2.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/2.sram_ctrl_max_throughput.4236032472
Short name T500
Test name
Test status
Simulation time 127895373 ps
CPU time 10.05 seconds
Started Apr 23 12:21:38 PM PDT 24
Finished Apr 23 12:21:48 PM PDT 24
Peak memory 250956 kb
Host smart-90374a1b-72a8-4681-b328-6c4ec3b8bb96
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236032472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.sram_ctrl_max_throughput.4236032472
Directory /workspace/2.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_partial_access.516360374
Short name T564
Test name
Test status
Simulation time 249729895 ps
CPU time 4.48 seconds
Started Apr 23 12:23:31 PM PDT 24
Finished Apr 23 12:23:37 PM PDT 24
Peak memory 209380 kb
Host smart-2106e086-62b2-460c-add5-f867dac2b333
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516360374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
sram_ctrl_mem_partial_access.516360374
Directory /workspace/2.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_walk.2146127604
Short name T550
Test name
Test status
Simulation time 335580968 ps
CPU time 4.53 seconds
Started Apr 23 12:21:57 PM PDT 24
Finished Apr 23 12:22:02 PM PDT 24
Peak memory 201760 kb
Host smart-116b8f10-0548-47b0-9b8f-3499ba6a8726
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146127604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl
_mem_walk.2146127604
Directory /workspace/2.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/2.sram_ctrl_multiple_keys.1271744471
Short name T879
Test name
Test status
Simulation time 12329474974 ps
CPU time 911.52 seconds
Started Apr 23 12:24:11 PM PDT 24
Finished Apr 23 12:39:25 PM PDT 24
Peak memory 373708 kb
Host smart-68a141df-5292-4eed-8065-9a2e5d14c4bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271744471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multip
le_keys.1271744471
Directory /workspace/2.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access.3743243745
Short name T522
Test name
Test status
Simulation time 354391210 ps
CPU time 7.83 seconds
Started Apr 23 12:23:19 PM PDT 24
Finished Apr 23 12:23:28 PM PDT 24
Peak memory 234844 kb
Host smart-f45556b7-d23c-4f95-ad38-249ae85f06f7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743243745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.s
ram_ctrl_partial_access.3743243745
Directory /workspace/2.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.999205302
Short name T580
Test name
Test status
Simulation time 140007167362 ps
CPU time 308.96 seconds
Started Apr 23 12:23:18 PM PDT 24
Finished Apr 23 12:28:28 PM PDT 24
Peak memory 200476 kb
Host smart-ab32e83b-d285-4f24-9a1a-05932966cfed
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999205302 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.sram_ctrl_partial_access_b2b.999205302
Directory /workspace/2.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/2.sram_ctrl_ram_cfg.1047958031
Short name T532
Test name
Test status
Simulation time 49810540 ps
CPU time 0.87 seconds
Started Apr 23 12:22:06 PM PDT 24
Finished Apr 23 12:22:07 PM PDT 24
Peak memory 201940 kb
Host smart-d77b24d1-f18d-4a38-a4ca-1017e42497fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047958031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.1047958031
Directory /workspace/2.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/2.sram_ctrl_regwen.4066866668
Short name T540
Test name
Test status
Simulation time 31369516917 ps
CPU time 748.12 seconds
Started Apr 23 12:23:57 PM PDT 24
Finished Apr 23 12:36:27 PM PDT 24
Peak memory 371868 kb
Host smart-9c77d264-dcbf-4ff5-8606-255918ab48a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066866668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.4066866668
Directory /workspace/2.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/2.sram_ctrl_sec_cm.4067500452
Short name T28
Test name
Test status
Simulation time 138602758 ps
CPU time 1.94 seconds
Started Apr 23 12:24:29 PM PDT 24
Finished Apr 23 12:24:32 PM PDT 24
Peak memory 220636 kb
Host smart-527c48b3-0110-4681-b429-9a466b0a4230
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067500452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_sec_cm.4067500452
Directory /workspace/2.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sram_ctrl_smoke.1364278251
Short name T543
Test name
Test status
Simulation time 3900926680 ps
CPU time 99.22 seconds
Started Apr 23 12:24:11 PM PDT 24
Finished Apr 23 12:25:53 PM PDT 24
Peak memory 367220 kb
Host smart-1b902d5f-b2a5-4d1f-83ef-fe36fe81e344
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364278251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.1364278251
Directory /workspace/2.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_all.2410443268
Short name T253
Test name
Test status
Simulation time 7297043398 ps
CPU time 2211.02 seconds
Started Apr 23 12:23:45 PM PDT 24
Finished Apr 23 01:00:38 PM PDT 24
Peak memory 372044 kb
Host smart-82feb49f-f8d3-4edb-b724-b1ed9c070dd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410443268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 2.sram_ctrl_stress_all.2410443268
Directory /workspace/2.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.4192363150
Short name T34
Test name
Test status
Simulation time 1178263588 ps
CPU time 26.63 seconds
Started Apr 23 12:23:30 PM PDT 24
Finished Apr 23 12:23:58 PM PDT 24
Peak memory 209972 kb
Host smart-6af23348-42b9-4c39-af5c-988dc1574b7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4192363150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.4192363150
Directory /workspace/2.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_pipeline.1935233306
Short name T644
Test name
Test status
Simulation time 20833059215 ps
CPU time 302.58 seconds
Started Apr 23 12:23:20 PM PDT 24
Finished Apr 23 12:28:23 PM PDT 24
Peak memory 201812 kb
Host smart-7bd5ac03-8dc2-423c-af09-bebe7a12cd9f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935233306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.sram_ctrl_stress_pipeline.1935233306
Directory /workspace/2.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.1607862661
Short name T861
Test name
Test status
Simulation time 86587014 ps
CPU time 8.46 seconds
Started Apr 23 12:23:29 PM PDT 24
Finished Apr 23 12:23:39 PM PDT 24
Peak memory 238352 kb
Host smart-8e4933c1-7312-4a10-a147-59d47dbf619b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607862661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.sram_ctrl_throughput_w_partial_write.1607862661
Directory /workspace/2.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/20.sram_ctrl_access_during_key_req.762883982
Short name T637
Test name
Test status
Simulation time 88383891438 ps
CPU time 1026.21 seconds
Started Apr 23 12:24:37 PM PDT 24
Finished Apr 23 12:41:45 PM PDT 24
Peak memory 372204 kb
Host smart-e47cd451-caf1-4e27-8308-8439b2ae6db7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762883982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 20.sram_ctrl_access_during_key_req.762883982
Directory /workspace/20.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/20.sram_ctrl_alert_test.1130738891
Short name T776
Test name
Test status
Simulation time 28714581 ps
CPU time 0.73 seconds
Started Apr 23 12:24:32 PM PDT 24
Finished Apr 23 12:24:34 PM PDT 24
Peak memory 200932 kb
Host smart-c69b3b10-aec9-40ac-b648-6153fe5a84ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130738891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.sram_ctrl_alert_test.1130738891
Directory /workspace/20.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sram_ctrl_bijection.3727551320
Short name T719
Test name
Test status
Simulation time 12710445813 ps
CPU time 60.61 seconds
Started Apr 23 12:24:40 PM PDT 24
Finished Apr 23 12:25:42 PM PDT 24
Peak memory 201908 kb
Host smart-19e6aba4-76e4-4264-ba3f-45e93fe1725d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727551320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection
.3727551320
Directory /workspace/20.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/20.sram_ctrl_executable.225335197
Short name T876
Test name
Test status
Simulation time 12466494600 ps
CPU time 1183.55 seconds
Started Apr 23 12:24:32 PM PDT 24
Finished Apr 23 12:44:17 PM PDT 24
Peak memory 371720 kb
Host smart-a8bafd21-3a69-4967-98d7-bf63aab117e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225335197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executabl
e.225335197
Directory /workspace/20.sram_ctrl_executable/latest

Test location /workspace/coverage/default/20.sram_ctrl_lc_escalation.3425103822
Short name T594
Test name
Test status
Simulation time 1858196611 ps
CPU time 9.56 seconds
Started Apr 23 12:24:27 PM PDT 24
Finished Apr 23 12:24:37 PM PDT 24
Peak memory 201900 kb
Host smart-d0006923-d249-41fd-ba6e-8cb146242ab8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425103822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_es
calation.3425103822
Directory /workspace/20.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/20.sram_ctrl_max_throughput.2314492671
Short name T646
Test name
Test status
Simulation time 140314318 ps
CPU time 11.34 seconds
Started Apr 23 12:24:40 PM PDT 24
Finished Apr 23 12:24:53 PM PDT 24
Peak memory 256652 kb
Host smart-407dd55b-80ab-45c5-bc25-ff0a82b67a7c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314492671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.sram_ctrl_max_throughput.2314492671
Directory /workspace/20.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_partial_access.1839300889
Short name T720
Test name
Test status
Simulation time 47608284 ps
CPU time 2.41 seconds
Started Apr 23 12:24:39 PM PDT 24
Finished Apr 23 12:24:43 PM PDT 24
Peak memory 210036 kb
Host smart-bc9d4afb-16b2-4c3f-8c19-e8b82ca4bb6c
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839300889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.sram_ctrl_mem_partial_access.1839300889
Directory /workspace/20.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_walk.3858172108
Short name T228
Test name
Test status
Simulation time 269013959 ps
CPU time 4.73 seconds
Started Apr 23 12:24:41 PM PDT 24
Finished Apr 23 12:24:47 PM PDT 24
Peak memory 201696 kb
Host smart-55af10e5-6a1a-4220-a741-ff91d0593a08
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858172108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctr
l_mem_walk.3858172108
Directory /workspace/20.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/20.sram_ctrl_multiple_keys.247030825
Short name T809
Test name
Test status
Simulation time 4172879890 ps
CPU time 194.89 seconds
Started Apr 23 12:24:34 PM PDT 24
Finished Apr 23 12:27:51 PM PDT 24
Peak memory 320592 kb
Host smart-e95a810f-b726-46e5-afde-bacbdc374f77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247030825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multip
le_keys.247030825
Directory /workspace/20.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access.856870693
Short name T628
Test name
Test status
Simulation time 219764545 ps
CPU time 3.63 seconds
Started Apr 23 12:24:32 PM PDT 24
Finished Apr 23 12:24:43 PM PDT 24
Peak memory 215792 kb
Host smart-ffa7c992-18f3-44fe-adc7-8ef58bad330d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856870693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.s
ram_ctrl_partial_access.856870693
Directory /workspace/20.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.3488305884
Short name T299
Test name
Test status
Simulation time 54305985148 ps
CPU time 329.1 seconds
Started Apr 23 12:24:35 PM PDT 24
Finished Apr 23 12:30:07 PM PDT 24
Peak memory 201860 kb
Host smart-0b20d533-0a41-4bd0-9e30-879448755167
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488305884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 20.sram_ctrl_partial_access_b2b.3488305884
Directory /workspace/20.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/20.sram_ctrl_ram_cfg.3684202966
Short name T718
Test name
Test status
Simulation time 76333644 ps
CPU time 0.75 seconds
Started Apr 23 12:24:34 PM PDT 24
Finished Apr 23 12:24:36 PM PDT 24
Peak memory 201996 kb
Host smart-325d3fab-996d-4b6e-989b-fbb518c79249
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684202966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.3684202966
Directory /workspace/20.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/20.sram_ctrl_regwen.4091345783
Short name T634
Test name
Test status
Simulation time 14492046403 ps
CPU time 942.95 seconds
Started Apr 23 12:24:41 PM PDT 24
Finished Apr 23 12:40:25 PM PDT 24
Peak memory 368644 kb
Host smart-5a8c0fae-d42a-428d-a3e3-84bddf986dcb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091345783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.4091345783
Directory /workspace/20.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/20.sram_ctrl_smoke.626279653
Short name T896
Test name
Test status
Simulation time 304466177 ps
CPU time 5.9 seconds
Started Apr 23 12:24:38 PM PDT 24
Finished Apr 23 12:24:46 PM PDT 24
Peak memory 227424 kb
Host smart-2e855d45-7bd9-45e2-be71-f63047ff277c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626279653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.626279653
Directory /workspace/20.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_all.3690598336
Short name T771
Test name
Test status
Simulation time 30342659097 ps
CPU time 5742.87 seconds
Started Apr 23 12:24:37 PM PDT 24
Finished Apr 23 02:00:22 PM PDT 24
Peak memory 381868 kb
Host smart-3d172fb8-3c68-40bf-b932-4e7aa97b1b5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690598336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 20.sram_ctrl_stress_all.3690598336
Directory /workspace/20.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.1751472799
Short name T44
Test name
Test status
Simulation time 6653461272 ps
CPU time 31.47 seconds
Started Apr 23 12:24:40 PM PDT 24
Finished Apr 23 12:25:13 PM PDT 24
Peak memory 210188 kb
Host smart-a6b6b7e6-82f5-47e1-997a-cba9c60cbcd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1751472799 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.1751472799
Directory /workspace/20.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_pipeline.769685107
Short name T414
Test name
Test status
Simulation time 3086899292 ps
CPU time 286.99 seconds
Started Apr 23 12:24:34 PM PDT 24
Finished Apr 23 12:29:23 PM PDT 24
Peak memory 201964 kb
Host smart-c354a5da-c34a-4992-8fb3-47ae7f03db6a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769685107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.sram_ctrl_stress_pipeline.769685107
Directory /workspace/20.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.798023144
Short name T272
Test name
Test status
Simulation time 125822637 ps
CPU time 18.23 seconds
Started Apr 23 12:24:33 PM PDT 24
Finished Apr 23 12:24:52 PM PDT 24
Peak memory 272680 kb
Host smart-9c614d11-03cf-45bb-93bf-93f83e72b44d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798023144 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.sram_ctrl_throughput_w_partial_write.798023144
Directory /workspace/20.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/21.sram_ctrl_access_during_key_req.1465464551
Short name T40
Test name
Test status
Simulation time 4187969893 ps
CPU time 1669.59 seconds
Started Apr 23 12:24:30 PM PDT 24
Finished Apr 23 12:52:20 PM PDT 24
Peak memory 373716 kb
Host smart-8fc3db36-4225-4146-ac7f-c32ceb94804b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465464551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.sram_ctrl_access_during_key_req.1465464551
Directory /workspace/21.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/21.sram_ctrl_alert_test.1761329145
Short name T640
Test name
Test status
Simulation time 40509852 ps
CPU time 0.62 seconds
Started Apr 23 12:24:36 PM PDT 24
Finished Apr 23 12:24:39 PM PDT 24
Peak memory 201060 kb
Host smart-8240c6e6-d0ac-45ee-b0ff-90c934711432
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761329145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.sram_ctrl_alert_test.1761329145
Directory /workspace/21.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sram_ctrl_bijection.1597692406
Short name T940
Test name
Test status
Simulation time 1955750198 ps
CPU time 26.79 seconds
Started Apr 23 12:24:27 PM PDT 24
Finished Apr 23 12:24:54 PM PDT 24
Peak memory 201908 kb
Host smart-b3493941-bdce-423a-88bb-79ad699033bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597692406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection
.1597692406
Directory /workspace/21.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/21.sram_ctrl_executable.3819439195
Short name T893
Test name
Test status
Simulation time 1365796015 ps
CPU time 330.28 seconds
Started Apr 23 12:24:40 PM PDT 24
Finished Apr 23 12:30:12 PM PDT 24
Peak memory 363028 kb
Host smart-68e809f6-17bb-4c1b-809b-e24c4909389c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819439195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executab
le.3819439195
Directory /workspace/21.sram_ctrl_executable/latest

Test location /workspace/coverage/default/21.sram_ctrl_lc_escalation.1386983041
Short name T509
Test name
Test status
Simulation time 292887003 ps
CPU time 2.53 seconds
Started Apr 23 12:24:36 PM PDT 24
Finished Apr 23 12:24:41 PM PDT 24
Peak memory 201932 kb
Host smart-f8ffc1c9-9b08-4f2c-8af1-520f3d52ade4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386983041 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_es
calation.1386983041
Directory /workspace/21.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/21.sram_ctrl_max_throughput.852627122
Short name T476
Test name
Test status
Simulation time 201845276 ps
CPU time 47.93 seconds
Started Apr 23 12:24:33 PM PDT 24
Finished Apr 23 12:25:22 PM PDT 24
Peak memory 304512 kb
Host smart-f1c63b01-5e59-4909-ad40-55c2c54d41dc
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852627122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.sram_ctrl_max_throughput.852627122
Directory /workspace/21.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_partial_access.4264727734
Short name T13
Test name
Test status
Simulation time 183475034 ps
CPU time 2.8 seconds
Started Apr 23 12:24:37 PM PDT 24
Finished Apr 23 12:24:42 PM PDT 24
Peak memory 209996 kb
Host smart-41dc939e-1ec3-4833-89af-e03904011022
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264727734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.sram_ctrl_mem_partial_access.4264727734
Directory /workspace/21.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_walk.980180104
Short name T917
Test name
Test status
Simulation time 78076609 ps
CPU time 4.28 seconds
Started Apr 23 12:24:37 PM PDT 24
Finished Apr 23 12:24:43 PM PDT 24
Peak memory 201804 kb
Host smart-b0d4933e-8ad1-49e4-93a3-fe018f6bc700
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980180104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl
_mem_walk.980180104
Directory /workspace/21.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/21.sram_ctrl_multiple_keys.4281018241
Short name T692
Test name
Test status
Simulation time 58917822237 ps
CPU time 823.73 seconds
Started Apr 23 12:24:24 PM PDT 24
Finished Apr 23 12:38:08 PM PDT 24
Peak memory 372776 kb
Host smart-cd4662d6-6381-451c-beee-d47143ee1c73
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281018241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multi
ple_keys.4281018241
Directory /workspace/21.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access.3657481171
Short name T524
Test name
Test status
Simulation time 1095144316 ps
CPU time 18.75 seconds
Started Apr 23 12:24:33 PM PDT 24
Finished Apr 23 12:24:53 PM PDT 24
Peak memory 201812 kb
Host smart-f58943a2-7cc9-4732-8f42-36f58ff8aac0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657481171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
sram_ctrl_partial_access.3657481171
Directory /workspace/21.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.1058228566
Short name T87
Test name
Test status
Simulation time 14219167039 ps
CPU time 242.82 seconds
Started Apr 23 12:24:38 PM PDT 24
Finished Apr 23 12:28:42 PM PDT 24
Peak memory 201856 kb
Host smart-f46d12af-5bb4-4862-94a1-88d0c590fdde
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058228566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 21.sram_ctrl_partial_access_b2b.1058228566
Directory /workspace/21.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/21.sram_ctrl_ram_cfg.3394964625
Short name T538
Test name
Test status
Simulation time 71867940 ps
CPU time 0.73 seconds
Started Apr 23 12:24:54 PM PDT 24
Finished Apr 23 12:24:57 PM PDT 24
Peak memory 201592 kb
Host smart-13061d68-5cb2-4806-b5d7-865fd67927f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394964625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.3394964625
Directory /workspace/21.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/21.sram_ctrl_regwen.122397059
Short name T537
Test name
Test status
Simulation time 53356202970 ps
CPU time 1580.25 seconds
Started Apr 23 12:24:39 PM PDT 24
Finished Apr 23 12:51:01 PM PDT 24
Peak memory 373760 kb
Host smart-034e2557-7acf-4a3b-b986-493e6c7d9067
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122397059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.122397059
Directory /workspace/21.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/21.sram_ctrl_smoke.117051936
Short name T496
Test name
Test status
Simulation time 1396481315 ps
CPU time 27.31 seconds
Started Apr 23 12:24:56 PM PDT 24
Finished Apr 23 12:25:25 PM PDT 24
Peak memory 280360 kb
Host smart-b0765568-ba1c-40e7-95be-9d405f4aa7b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117051936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.117051936
Directory /workspace/21.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_all.2052642478
Short name T399
Test name
Test status
Simulation time 32706305939 ps
CPU time 3020.65 seconds
Started Apr 23 12:24:33 PM PDT 24
Finished Apr 23 01:14:55 PM PDT 24
Peak memory 374448 kb
Host smart-57ee30aa-959a-4148-9a5b-a26944a6d3f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052642478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 21.sram_ctrl_stress_all.2052642478
Directory /workspace/21.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.3694076978
Short name T488
Test name
Test status
Simulation time 11685341759 ps
CPU time 210.02 seconds
Started Apr 23 12:24:35 PM PDT 24
Finished Apr 23 12:28:07 PM PDT 24
Peak memory 314500 kb
Host smart-394ced7b-ad66-4f6f-8777-0cf6783b924f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3694076978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.3694076978
Directory /workspace/21.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_pipeline.1575562663
Short name T781
Test name
Test status
Simulation time 3409278345 ps
CPU time 153.07 seconds
Started Apr 23 12:24:25 PM PDT 24
Finished Apr 23 12:26:59 PM PDT 24
Peak memory 201924 kb
Host smart-3e97df98-0a4f-45e9-96c3-89429ea1d62f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575562663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.sram_ctrl_stress_pipeline.1575562663
Directory /workspace/21.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.3136498460
Short name T797
Test name
Test status
Simulation time 139567421 ps
CPU time 14.03 seconds
Started Apr 23 12:24:33 PM PDT 24
Finished Apr 23 12:24:49 PM PDT 24
Peak memory 269356 kb
Host smart-480f5899-1ae2-4c11-ab83-ac5daea701c3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136498460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.sram_ctrl_throughput_w_partial_write.3136498460
Directory /workspace/21.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/22.sram_ctrl_access_during_key_req.685840090
Short name T277
Test name
Test status
Simulation time 11342110591 ps
CPU time 621.17 seconds
Started Apr 23 12:24:36 PM PDT 24
Finished Apr 23 12:35:00 PM PDT 24
Peak memory 372680 kb
Host smart-3ac85c83-de5a-4b4a-8fc0-940b92920133
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685840090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 22.sram_ctrl_access_during_key_req.685840090
Directory /workspace/22.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/22.sram_ctrl_alert_test.1749408849
Short name T600
Test name
Test status
Simulation time 24305158 ps
CPU time 0.69 seconds
Started Apr 23 12:24:30 PM PDT 24
Finished Apr 23 12:24:32 PM PDT 24
Peak memory 201084 kb
Host smart-09936260-9310-453b-ab70-52ffa4fe85fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749408849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.sram_ctrl_alert_test.1749408849
Directory /workspace/22.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sram_ctrl_bijection.4126174274
Short name T330
Test name
Test status
Simulation time 1229473213 ps
CPU time 19.51 seconds
Started Apr 23 12:24:48 PM PDT 24
Finished Apr 23 12:25:09 PM PDT 24
Peak memory 201928 kb
Host smart-7aeee6ca-05b2-4f37-8cc5-686b7e739477
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126174274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection
.4126174274
Directory /workspace/22.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/22.sram_ctrl_executable.791335718
Short name T420
Test name
Test status
Simulation time 2797074485 ps
CPU time 276.76 seconds
Started Apr 23 12:24:38 PM PDT 24
Finished Apr 23 12:29:17 PM PDT 24
Peak memory 369268 kb
Host smart-baae565e-5394-4e8a-b433-8d786495be9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791335718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executabl
e.791335718
Directory /workspace/22.sram_ctrl_executable/latest

Test location /workspace/coverage/default/22.sram_ctrl_lc_escalation.2254684892
Short name T706
Test name
Test status
Simulation time 774200099 ps
CPU time 4.37 seconds
Started Apr 23 12:24:36 PM PDT 24
Finished Apr 23 12:24:43 PM PDT 24
Peak memory 201892 kb
Host smart-b29e01ed-1602-4e74-8e66-a39f9ad2fe29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254684892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_es
calation.2254684892
Directory /workspace/22.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/22.sram_ctrl_max_throughput.2666284960
Short name T675
Test name
Test status
Simulation time 92713516 ps
CPU time 20.5 seconds
Started Apr 23 12:24:33 PM PDT 24
Finished Apr 23 12:24:55 PM PDT 24
Peak memory 283660 kb
Host smart-10db568a-f335-4aea-a5d5-a0dae6e05cac
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666284960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.sram_ctrl_max_throughput.2666284960
Directory /workspace/22.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_partial_access.2337060285
Short name T174
Test name
Test status
Simulation time 48016761 ps
CPU time 2.47 seconds
Started Apr 23 12:24:37 PM PDT 24
Finished Apr 23 12:24:42 PM PDT 24
Peak memory 210044 kb
Host smart-3fd2575b-b798-48b2-bb62-8135de6fc743
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337060285 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.sram_ctrl_mem_partial_access.2337060285
Directory /workspace/22.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_walk.1492887517
Short name T858
Test name
Test status
Simulation time 525066837 ps
CPU time 7.74 seconds
Started Apr 23 12:24:44 PM PDT 24
Finished Apr 23 12:24:53 PM PDT 24
Peak memory 201772 kb
Host smart-80fe8c90-1642-416d-8901-4fbf911a0f88
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492887517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctr
l_mem_walk.1492887517
Directory /workspace/22.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/22.sram_ctrl_multiple_keys.2995285512
Short name T690
Test name
Test status
Simulation time 9446254268 ps
CPU time 531.4 seconds
Started Apr 23 12:24:35 PM PDT 24
Finished Apr 23 12:33:29 PM PDT 24
Peak memory 365332 kb
Host smart-da8ade9e-5d09-41b1-b216-79a834611b59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995285512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multi
ple_keys.2995285512
Directory /workspace/22.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access.4191657709
Short name T731
Test name
Test status
Simulation time 3870474765 ps
CPU time 16.02 seconds
Started Apr 23 12:24:41 PM PDT 24
Finished Apr 23 12:24:58 PM PDT 24
Peak memory 201848 kb
Host smart-1d90b4b5-8a3a-46c6-8c01-c2f770ef9322
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191657709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
sram_ctrl_partial_access.4191657709
Directory /workspace/22.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.1344551164
Short name T542
Test name
Test status
Simulation time 71024525630 ps
CPU time 401.01 seconds
Started Apr 23 12:24:35 PM PDT 24
Finished Apr 23 12:31:18 PM PDT 24
Peak memory 201928 kb
Host smart-0f71dd8f-521d-44e7-b76d-db2f2a90c8a6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344551164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 22.sram_ctrl_partial_access_b2b.1344551164
Directory /workspace/22.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/22.sram_ctrl_ram_cfg.510025165
Short name T114
Test name
Test status
Simulation time 78283121 ps
CPU time 0.72 seconds
Started Apr 23 12:24:45 PM PDT 24
Finished Apr 23 12:24:47 PM PDT 24
Peak memory 201924 kb
Host smart-d7f613cf-e53a-442c-bb5d-9b6249ff0467
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510025165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.510025165
Directory /workspace/22.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/22.sram_ctrl_regwen.2509178273
Short name T716
Test name
Test status
Simulation time 5791346632 ps
CPU time 722.42 seconds
Started Apr 23 12:24:35 PM PDT 24
Finished Apr 23 12:36:39 PM PDT 24
Peak memory 372712 kb
Host smart-4dd34472-f26d-4954-b9cc-8c02932d545e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509178273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.2509178273
Directory /workspace/22.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/22.sram_ctrl_smoke.494332667
Short name T138
Test name
Test status
Simulation time 1162852741 ps
CPU time 8.99 seconds
Started Apr 23 12:24:35 PM PDT 24
Finished Apr 23 12:24:46 PM PDT 24
Peak memory 201892 kb
Host smart-62c42239-7641-4e30-a2da-6f47798c27eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494332667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.494332667
Directory /workspace/22.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_all.2787248636
Short name T164
Test name
Test status
Simulation time 2204956691 ps
CPU time 100.42 seconds
Started Apr 23 12:24:35 PM PDT 24
Finished Apr 23 12:26:18 PM PDT 24
Peak memory 258444 kb
Host smart-81d8ed11-7533-4c00-bd0a-cc549933f71e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787248636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 22.sram_ctrl_stress_all.2787248636
Directory /workspace/22.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.3076829837
Short name T104
Test name
Test status
Simulation time 4800066930 ps
CPU time 123.05 seconds
Started Apr 23 12:24:35 PM PDT 24
Finished Apr 23 12:26:40 PM PDT 24
Peak memory 353524 kb
Host smart-60162ff6-19c3-4d00-bf72-731233a96e06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3076829837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.3076829837
Directory /workspace/22.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_pipeline.383897785
Short name T779
Test name
Test status
Simulation time 7602053369 ps
CPU time 400.28 seconds
Started Apr 23 12:24:33 PM PDT 24
Finished Apr 23 12:31:15 PM PDT 24
Peak memory 201952 kb
Host smart-f46255c3-16a5-47ad-a531-0e51af9048fd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383897785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.sram_ctrl_stress_pipeline.383897785
Directory /workspace/22.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.86489732
Short name T110
Test name
Test status
Simulation time 350178047 ps
CPU time 21.91 seconds
Started Apr 23 12:24:51 PM PDT 24
Finished Apr 23 12:25:15 PM PDT 24
Peak memory 278220 kb
Host smart-00af774c-2c10-4866-b9fb-e147ef0a23cf
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86489732 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.sram_ctrl_throughput_w_partial_write.86489732
Directory /workspace/22.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/23.sram_ctrl_access_during_key_req.927838748
Short name T796
Test name
Test status
Simulation time 10688552848 ps
CPU time 958.44 seconds
Started Apr 23 12:24:34 PM PDT 24
Finished Apr 23 12:40:35 PM PDT 24
Peak memory 373640 kb
Host smart-5e1f132f-2fa2-421a-afb9-d2aab3d62a65
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927838748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 23.sram_ctrl_access_during_key_req.927838748
Directory /workspace/23.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/23.sram_ctrl_alert_test.449511120
Short name T19
Test name
Test status
Simulation time 28230076 ps
CPU time 0.6 seconds
Started Apr 23 12:24:41 PM PDT 24
Finished Apr 23 12:24:43 PM PDT 24
Peak memory 201056 kb
Host smart-db072c6f-a752-44b6-89bf-7117b2c68aaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449511120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.sram_ctrl_alert_test.449511120
Directory /workspace/23.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sram_ctrl_bijection.758802504
Short name T157
Test name
Test status
Simulation time 10297622898 ps
CPU time 64.67 seconds
Started Apr 23 12:24:53 PM PDT 24
Finished Apr 23 12:26:00 PM PDT 24
Peak memory 201936 kb
Host smart-f760c299-679c-4b46-a978-aae4ade6925d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758802504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection.
758802504
Directory /workspace/23.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/23.sram_ctrl_executable.3937859520
Short name T159
Test name
Test status
Simulation time 12853260071 ps
CPU time 102.78 seconds
Started Apr 23 12:24:33 PM PDT 24
Finished Apr 23 12:26:18 PM PDT 24
Peak memory 313100 kb
Host smart-ce5d6997-8809-46f2-ae0e-2ea656142eb7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937859520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executab
le.3937859520
Directory /workspace/23.sram_ctrl_executable/latest

Test location /workspace/coverage/default/23.sram_ctrl_lc_escalation.3181120401
Short name T577
Test name
Test status
Simulation time 654283611 ps
CPU time 2.25 seconds
Started Apr 23 12:24:40 PM PDT 24
Finished Apr 23 12:24:44 PM PDT 24
Peak memory 201912 kb
Host smart-43d965e2-19d7-4b36-8954-335858a10128
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181120401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_es
calation.3181120401
Directory /workspace/23.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/23.sram_ctrl_max_throughput.1219759538
Short name T570
Test name
Test status
Simulation time 65191415 ps
CPU time 3.76 seconds
Started Apr 23 12:24:36 PM PDT 24
Finished Apr 23 12:24:42 PM PDT 24
Peak memory 222916 kb
Host smart-c7b01d0a-f640-40ed-8337-1869cc9545f0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219759538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.sram_ctrl_max_throughput.1219759538
Directory /workspace/23.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_partial_access.2437276407
Short name T684
Test name
Test status
Simulation time 302608018 ps
CPU time 5.58 seconds
Started Apr 23 12:24:48 PM PDT 24
Finished Apr 23 12:24:55 PM PDT 24
Peak memory 210028 kb
Host smart-eea76a7f-eea7-4c94-ae44-98a4b137a758
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437276407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.sram_ctrl_mem_partial_access.2437276407
Directory /workspace/23.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_walk.2538545963
Short name T924
Test name
Test status
Simulation time 2233326200 ps
CPU time 10.01 seconds
Started Apr 23 12:24:35 PM PDT 24
Finished Apr 23 12:24:48 PM PDT 24
Peak memory 201108 kb
Host smart-a0170d61-9129-4379-8e70-bc3e89c54f25
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538545963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctr
l_mem_walk.2538545963
Directory /workspace/23.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/23.sram_ctrl_multiple_keys.1293318326
Short name T552
Test name
Test status
Simulation time 1123725919 ps
CPU time 260.25 seconds
Started Apr 23 12:24:39 PM PDT 24
Finished Apr 23 12:29:01 PM PDT 24
Peak memory 371896 kb
Host smart-bb21b6c2-43a8-4d5f-a074-dcd90eb21ec7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293318326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multi
ple_keys.1293318326
Directory /workspace/23.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access.3986104033
Short name T304
Test name
Test status
Simulation time 786796389 ps
CPU time 8.72 seconds
Started Apr 23 12:24:36 PM PDT 24
Finished Apr 23 12:24:47 PM PDT 24
Peak memory 201828 kb
Host smart-3f57280f-59cb-4a4e-9f55-893ddf4e9515
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986104033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
sram_ctrl_partial_access.3986104033
Directory /workspace/23.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.4063830729
Short name T688
Test name
Test status
Simulation time 29850092754 ps
CPU time 374.72 seconds
Started Apr 23 12:24:38 PM PDT 24
Finished Apr 23 12:30:55 PM PDT 24
Peak memory 201924 kb
Host smart-823a9ad4-096a-45c3-8807-052248021acd
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063830729 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 23.sram_ctrl_partial_access_b2b.4063830729
Directory /workspace/23.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/23.sram_ctrl_ram_cfg.44294478
Short name T219
Test name
Test status
Simulation time 29224931 ps
CPU time 0.79 seconds
Started Apr 23 12:24:52 PM PDT 24
Finished Apr 23 12:24:54 PM PDT 24
Peak memory 201920 kb
Host smart-39883883-e439-4ab6-b268-b35b51ef4eb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44294478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf
g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.44294478
Directory /workspace/23.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/23.sram_ctrl_regwen.3195432439
Short name T249
Test name
Test status
Simulation time 1147921986 ps
CPU time 297.18 seconds
Started Apr 23 12:24:53 PM PDT 24
Finished Apr 23 12:29:52 PM PDT 24
Peak memory 335840 kb
Host smart-74070ff7-7c41-427c-a6e6-d2d719350adf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195432439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.3195432439
Directory /workspace/23.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/23.sram_ctrl_smoke.3546832764
Short name T368
Test name
Test status
Simulation time 732791284 ps
CPU time 11.04 seconds
Started Apr 23 12:24:30 PM PDT 24
Finished Apr 23 12:24:42 PM PDT 24
Peak memory 201856 kb
Host smart-a58e1c52-e27c-4e7c-8835-f19fc0729ab8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546832764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.3546832764
Directory /workspace/23.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_all.1657155459
Short name T841
Test name
Test status
Simulation time 19349498153 ps
CPU time 3144.53 seconds
Started Apr 23 12:24:32 PM PDT 24
Finished Apr 23 01:16:58 PM PDT 24
Peak memory 381984 kb
Host smart-4d4c99e8-ca56-401e-9129-01fcb33d24d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657155459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 23.sram_ctrl_stress_all.1657155459
Directory /workspace/23.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.640624547
Short name T605
Test name
Test status
Simulation time 335797130 ps
CPU time 104.91 seconds
Started Apr 23 12:24:37 PM PDT 24
Finished Apr 23 12:26:24 PM PDT 24
Peak memory 343980 kb
Host smart-2c6d4981-7746-45f8-aea4-4ac34fdfda44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=640624547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.640624547
Directory /workspace/23.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_pipeline.1961286446
Short name T227
Test name
Test status
Simulation time 9498585649 ps
CPU time 109.56 seconds
Started Apr 23 12:24:36 PM PDT 24
Finished Apr 23 12:26:28 PM PDT 24
Peak memory 201896 kb
Host smart-81e10a40-2009-4160-9445-012e8295a2a0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961286446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.sram_ctrl_stress_pipeline.1961286446
Directory /workspace/23.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.1137648074
Short name T208
Test name
Test status
Simulation time 321171969 ps
CPU time 14.29 seconds
Started Apr 23 12:24:53 PM PDT 24
Finished Apr 23 12:25:09 PM PDT 24
Peak memory 266704 kb
Host smart-fdd24469-4d49-4d78-b550-3202189076f2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137648074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.sram_ctrl_throughput_w_partial_write.1137648074
Directory /workspace/23.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/24.sram_ctrl_access_during_key_req.3365085235
Short name T451
Test name
Test status
Simulation time 6768768670 ps
CPU time 947.5 seconds
Started Apr 23 12:24:36 PM PDT 24
Finished Apr 23 12:40:26 PM PDT 24
Peak memory 373608 kb
Host smart-a16f49b7-f34b-4a35-bf58-471272710813
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365085235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.sram_ctrl_access_during_key_req.3365085235
Directory /workspace/24.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/24.sram_ctrl_alert_test.1927680751
Short name T578
Test name
Test status
Simulation time 42585516 ps
CPU time 0.67 seconds
Started Apr 23 12:24:45 PM PDT 24
Finished Apr 23 12:24:46 PM PDT 24
Peak memory 201076 kb
Host smart-6ffa6261-3fb4-4825-a177-6fe5626d03df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927680751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.sram_ctrl_alert_test.1927680751
Directory /workspace/24.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sram_ctrl_bijection.2555811129
Short name T702
Test name
Test status
Simulation time 7031697121 ps
CPU time 56.8 seconds
Started Apr 23 12:24:43 PM PDT 24
Finished Apr 23 12:25:40 PM PDT 24
Peak memory 201940 kb
Host smart-365a8a53-28f9-4fd2-a1a4-9361edb3d39a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555811129 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection
.2555811129
Directory /workspace/24.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/24.sram_ctrl_executable.3527547982
Short name T252
Test name
Test status
Simulation time 7700186512 ps
CPU time 219.43 seconds
Started Apr 23 12:24:22 PM PDT 24
Finished Apr 23 12:28:02 PM PDT 24
Peak memory 328088 kb
Host smart-5000fb4e-2378-473f-adce-d10f66064f7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527547982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executab
le.3527547982
Directory /workspace/24.sram_ctrl_executable/latest

Test location /workspace/coverage/default/24.sram_ctrl_lc_escalation.1670856619
Short name T463
Test name
Test status
Simulation time 611166306 ps
CPU time 7.9 seconds
Started Apr 23 12:24:38 PM PDT 24
Finished Apr 23 12:24:48 PM PDT 24
Peak memory 201964 kb
Host smart-c32c719e-4b96-408e-8b4e-7b62366e4436
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670856619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_es
calation.1670856619
Directory /workspace/24.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/24.sram_ctrl_max_throughput.3887674619
Short name T225
Test name
Test status
Simulation time 531301138 ps
CPU time 102.01 seconds
Started Apr 23 12:24:37 PM PDT 24
Finished Apr 23 12:26:21 PM PDT 24
Peak memory 364304 kb
Host smart-ed4ed9e6-97c0-482f-819f-8ef039ecfc20
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887674619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.sram_ctrl_max_throughput.3887674619
Directory /workspace/24.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_partial_access.388022291
Short name T887
Test name
Test status
Simulation time 341626780 ps
CPU time 2.83 seconds
Started Apr 23 12:24:36 PM PDT 24
Finished Apr 23 12:24:41 PM PDT 24
Peak memory 209992 kb
Host smart-03e7a1e2-6ae0-4a9f-a504-91bae179d119
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388022291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.sram_ctrl_mem_partial_access.388022291
Directory /workspace/24.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_walk.419013165
Short name T282
Test name
Test status
Simulation time 174309312 ps
CPU time 8.8 seconds
Started Apr 23 12:24:58 PM PDT 24
Finished Apr 23 12:25:07 PM PDT 24
Peak memory 201924 kb
Host smart-30e815b8-8b67-4dbf-a3c5-b4abca7ef7b7
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419013165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl
_mem_walk.419013165
Directory /workspace/24.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/24.sram_ctrl_multiple_keys.2984576669
Short name T446
Test name
Test status
Simulation time 17840799757 ps
CPU time 875.82 seconds
Started Apr 23 12:24:53 PM PDT 24
Finished Apr 23 12:39:31 PM PDT 24
Peak memory 373804 kb
Host smart-69e5ecb0-6d90-4386-889f-9d35f8fbc205
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984576669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multi
ple_keys.2984576669
Directory /workspace/24.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access.321349005
Short name T700
Test name
Test status
Simulation time 1153998138 ps
CPU time 15.97 seconds
Started Apr 23 12:24:43 PM PDT 24
Finished Apr 23 12:25:00 PM PDT 24
Peak memory 201836 kb
Host smart-964c6ec0-4306-41f5-a7e3-38da99901fc5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321349005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.s
ram_ctrl_partial_access.321349005
Directory /workspace/24.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.1514392134
Short name T638
Test name
Test status
Simulation time 4409217780 ps
CPU time 290.54 seconds
Started Apr 23 12:24:45 PM PDT 24
Finished Apr 23 12:29:37 PM PDT 24
Peak memory 201944 kb
Host smart-1161397c-71f1-4b1b-b789-8edeaa8a39db
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514392134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 24.sram_ctrl_partial_access_b2b.1514392134
Directory /workspace/24.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/24.sram_ctrl_ram_cfg.118147266
Short name T161
Test name
Test status
Simulation time 41536460 ps
CPU time 0.77 seconds
Started Apr 23 12:24:50 PM PDT 24
Finished Apr 23 12:24:52 PM PDT 24
Peak memory 201936 kb
Host smart-a892b86a-abba-401c-898b-1af564e80c4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118147266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.118147266
Directory /workspace/24.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/24.sram_ctrl_regwen.3010516145
Short name T462
Test name
Test status
Simulation time 10067535587 ps
CPU time 666.52 seconds
Started Apr 23 12:24:35 PM PDT 24
Finished Apr 23 12:35:44 PM PDT 24
Peak memory 369684 kb
Host smart-9e5141cc-52eb-4d27-9ffd-3873377547cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010516145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.3010516145
Directory /workspace/24.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/24.sram_ctrl_smoke.3018219677
Short name T324
Test name
Test status
Simulation time 847576742 ps
CPU time 13.07 seconds
Started Apr 23 12:24:31 PM PDT 24
Finished Apr 23 12:24:45 PM PDT 24
Peak memory 201892 kb
Host smart-32d1ded6-911e-49e3-aa46-1db3e3f24c11
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018219677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.3018219677
Directory /workspace/24.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_all.1464569582
Short name T671
Test name
Test status
Simulation time 32413003206 ps
CPU time 1265.72 seconds
Started Apr 23 12:24:51 PM PDT 24
Finished Apr 23 12:45:58 PM PDT 24
Peak memory 370632 kb
Host smart-021ee25a-5a12-4623-9417-6db9521f6222
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464569582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 24.sram_ctrl_stress_all.1464569582
Directory /workspace/24.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_pipeline.676221678
Short name T346
Test name
Test status
Simulation time 3595356795 ps
CPU time 311.83 seconds
Started Apr 23 12:24:49 PM PDT 24
Finished Apr 23 12:30:02 PM PDT 24
Peak memory 201928 kb
Host smart-1cbec21e-a702-42a1-b178-507435644f24
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676221678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.sram_ctrl_stress_pipeline.676221678
Directory /workspace/24.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.3400246548
Short name T721
Test name
Test status
Simulation time 40609867 ps
CPU time 1.73 seconds
Started Apr 23 12:24:33 PM PDT 24
Finished Apr 23 12:24:36 PM PDT 24
Peak memory 210296 kb
Host smart-c752b2e5-84d9-4b2e-b4cb-516dfa650180
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400246548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.sram_ctrl_throughput_w_partial_write.3400246548
Directory /workspace/24.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/25.sram_ctrl_access_during_key_req.2130593027
Short name T427
Test name
Test status
Simulation time 597663155 ps
CPU time 248.81 seconds
Started Apr 23 12:24:54 PM PDT 24
Finished Apr 23 12:29:05 PM PDT 24
Peak memory 372628 kb
Host smart-523377f9-f8d8-40ed-8705-2c5edf0c27d3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130593027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.sram_ctrl_access_during_key_req.2130593027
Directory /workspace/25.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/25.sram_ctrl_alert_test.921591616
Short name T35
Test name
Test status
Simulation time 19833224 ps
CPU time 0.61 seconds
Started Apr 23 12:24:45 PM PDT 24
Finished Apr 23 12:24:47 PM PDT 24
Peak memory 201652 kb
Host smart-03106ffe-4562-4e4c-9f84-ed3c94450a8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921591616 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.sram_ctrl_alert_test.921591616
Directory /workspace/25.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sram_ctrl_bijection.404426224
Short name T210
Test name
Test status
Simulation time 2619364766 ps
CPU time 28.31 seconds
Started Apr 23 12:24:38 PM PDT 24
Finished Apr 23 12:25:08 PM PDT 24
Peak memory 201992 kb
Host smart-462af4f9-b5ea-4f2b-bcb2-ce6a461f50a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404426224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection.
404426224
Directory /workspace/25.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/25.sram_ctrl_executable.2214902764
Short name T745
Test name
Test status
Simulation time 15395348514 ps
CPU time 755.99 seconds
Started Apr 23 12:24:34 PM PDT 24
Finished Apr 23 12:37:12 PM PDT 24
Peak memory 367248 kb
Host smart-f2de463e-9d85-49e0-a18c-454b4db87133
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214902764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executab
le.2214902764
Directory /workspace/25.sram_ctrl_executable/latest

Test location /workspace/coverage/default/25.sram_ctrl_lc_escalation.3597873161
Short name T878
Test name
Test status
Simulation time 380519587 ps
CPU time 2.29 seconds
Started Apr 23 12:24:36 PM PDT 24
Finished Apr 23 12:24:41 PM PDT 24
Peak memory 201900 kb
Host smart-628fb9ee-2d7e-4932-84ac-def9f27553c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597873161 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_es
calation.3597873161
Directory /workspace/25.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/25.sram_ctrl_max_throughput.3491999213
Short name T429
Test name
Test status
Simulation time 161317533 ps
CPU time 21.71 seconds
Started Apr 23 12:24:53 PM PDT 24
Finished Apr 23 12:25:17 PM PDT 24
Peak memory 267320 kb
Host smart-5f86fe66-812c-4551-814c-a64ad1ac40fc
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491999213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 25.sram_ctrl_max_throughput.3491999213
Directory /workspace/25.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_partial_access.2891518317
Short name T803
Test name
Test status
Simulation time 64949306 ps
CPU time 4.43 seconds
Started Apr 23 12:24:53 PM PDT 24
Finished Apr 23 12:25:00 PM PDT 24
Peak memory 209988 kb
Host smart-9c2cab3f-c2d7-40b5-a421-695973d6d97e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891518317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.sram_ctrl_mem_partial_access.2891518317
Directory /workspace/25.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_walk.196984044
Short name T693
Test name
Test status
Simulation time 960366191 ps
CPU time 5.5 seconds
Started Apr 23 12:24:53 PM PDT 24
Finished Apr 23 12:25:01 PM PDT 24
Peak memory 201752 kb
Host smart-653cdf16-0736-4517-81b9-01de7703d846
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196984044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl
_mem_walk.196984044
Directory /workspace/25.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/25.sram_ctrl_multiple_keys.2041801541
Short name T337
Test name
Test status
Simulation time 76050767021 ps
CPU time 1131.73 seconds
Started Apr 23 12:24:37 PM PDT 24
Finished Apr 23 12:43:31 PM PDT 24
Peak memory 373760 kb
Host smart-b8b625f2-b09b-41ca-a358-c8ebcf164230
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041801541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multi
ple_keys.2041801541
Directory /workspace/25.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access.393857207
Short name T217
Test name
Test status
Simulation time 3862162064 ps
CPU time 17.09 seconds
Started Apr 23 12:24:35 PM PDT 24
Finished Apr 23 12:24:55 PM PDT 24
Peak memory 263124 kb
Host smart-6416d343-d195-4fd2-abbc-7ef2b36a6f0f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393857207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.s
ram_ctrl_partial_access.393857207
Directory /workspace/25.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.3981643470
Short name T464
Test name
Test status
Simulation time 2724539902 ps
CPU time 179.28 seconds
Started Apr 23 12:24:34 PM PDT 24
Finished Apr 23 12:27:34 PM PDT 24
Peak memory 201928 kb
Host smart-4b75f33b-2ef9-4762-901c-8df5c42aa373
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981643470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 25.sram_ctrl_partial_access_b2b.3981643470
Directory /workspace/25.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/25.sram_ctrl_ram_cfg.1000036793
Short name T203
Test name
Test status
Simulation time 51464442 ps
CPU time 0.74 seconds
Started Apr 23 12:24:37 PM PDT 24
Finished Apr 23 12:24:40 PM PDT 24
Peak memory 201988 kb
Host smart-fb90aba2-60c4-4325-8716-b3f4a82bad4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000036793 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.1000036793
Directory /workspace/25.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/25.sram_ctrl_regwen.1978491421
Short name T648
Test name
Test status
Simulation time 39412786969 ps
CPU time 1144.89 seconds
Started Apr 23 12:24:53 PM PDT 24
Finished Apr 23 12:44:00 PM PDT 24
Peak memory 373700 kb
Host smart-7fb5c224-9c4b-4179-b141-f3fb57f32d93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978491421 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.1978491421
Directory /workspace/25.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/25.sram_ctrl_smoke.362923356
Short name T381
Test name
Test status
Simulation time 2048337391 ps
CPU time 10.87 seconds
Started Apr 23 12:24:54 PM PDT 24
Finished Apr 23 12:25:07 PM PDT 24
Peak memory 201880 kb
Host smart-27906800-83fe-4c42-95d2-8a1ef03d9a1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362923356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.362923356
Directory /workspace/25.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_all.1153925088
Short name T712
Test name
Test status
Simulation time 17430336432 ps
CPU time 2774.39 seconds
Started Apr 23 12:24:48 PM PDT 24
Finished Apr 23 01:11:04 PM PDT 24
Peak memory 381888 kb
Host smart-e4a27ed7-c61c-4780-a97d-a953de136fc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153925088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 25.sram_ctrl_stress_all.1153925088
Directory /workspace/25.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_pipeline.3277029686
Short name T928
Test name
Test status
Simulation time 11757195562 ps
CPU time 262.76 seconds
Started Apr 23 12:24:37 PM PDT 24
Finished Apr 23 12:29:02 PM PDT 24
Peak memory 201916 kb
Host smart-457e9b3f-09b3-478b-ac46-cfc2ecb8373f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277029686 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.sram_ctrl_stress_pipeline.3277029686
Directory /workspace/25.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.1488960905
Short name T335
Test name
Test status
Simulation time 113150651 ps
CPU time 30.92 seconds
Started Apr 23 12:24:52 PM PDT 24
Finished Apr 23 12:25:26 PM PDT 24
Peak memory 300060 kb
Host smart-ed70717e-648c-4249-ba48-ad033867662a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488960905 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.sram_ctrl_throughput_w_partial_write.1488960905
Directory /workspace/25.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/26.sram_ctrl_access_during_key_req.3319031644
Short name T67
Test name
Test status
Simulation time 8095833138 ps
CPU time 1126.5 seconds
Started Apr 23 12:24:54 PM PDT 24
Finished Apr 23 12:43:43 PM PDT 24
Peak memory 373744 kb
Host smart-82e842ff-0981-4586-90fb-db07ec8b8da4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319031644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.sram_ctrl_access_during_key_req.3319031644
Directory /workspace/26.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/26.sram_ctrl_alert_test.763153660
Short name T602
Test name
Test status
Simulation time 47623726 ps
CPU time 0.63 seconds
Started Apr 23 12:24:47 PM PDT 24
Finished Apr 23 12:24:49 PM PDT 24
Peak memory 201692 kb
Host smart-df6807a3-2483-440e-ae28-f46a32c2b783
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763153660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.sram_ctrl_alert_test.763153660
Directory /workspace/26.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sram_ctrl_bijection.3382910531
Short name T474
Test name
Test status
Simulation time 22638132226 ps
CPU time 81.09 seconds
Started Apr 23 12:24:53 PM PDT 24
Finished Apr 23 12:26:17 PM PDT 24
Peak memory 201972 kb
Host smart-81a78c91-f65c-4c98-89ee-4f4a40d8f8f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382910531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection
.3382910531
Directory /workspace/26.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/26.sram_ctrl_executable.3185470657
Short name T544
Test name
Test status
Simulation time 7033376495 ps
CPU time 865.4 seconds
Started Apr 23 12:24:41 PM PDT 24
Finished Apr 23 12:39:08 PM PDT 24
Peak memory 374000 kb
Host smart-3feab9a7-baa6-45ed-8e1e-d403640e6adc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185470657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executab
le.3185470657
Directory /workspace/26.sram_ctrl_executable/latest

Test location /workspace/coverage/default/26.sram_ctrl_lc_escalation.45593210
Short name T468
Test name
Test status
Simulation time 694130827 ps
CPU time 5.95 seconds
Started Apr 23 12:25:07 PM PDT 24
Finished Apr 23 12:25:17 PM PDT 24
Peak memory 201880 kb
Host smart-616de356-3fc5-4615-bef0-21cacd8996ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45593210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc
alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_esca
lation.45593210
Directory /workspace/26.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/26.sram_ctrl_max_throughput.3040524190
Short name T148
Test name
Test status
Simulation time 63150648 ps
CPU time 8.06 seconds
Started Apr 23 12:24:53 PM PDT 24
Finished Apr 23 12:25:03 PM PDT 24
Peak memory 244008 kb
Host smart-5244960f-f181-4d17-bb18-ad04743afc0d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040524190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.sram_ctrl_max_throughput.3040524190
Directory /workspace/26.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_partial_access.2184323420
Short name T185
Test name
Test status
Simulation time 118547727 ps
CPU time 4.13 seconds
Started Apr 23 12:24:54 PM PDT 24
Finished Apr 23 12:25:01 PM PDT 24
Peak memory 210072 kb
Host smart-2dc5f6b3-05a7-49d7-a3e9-28166d9f4620
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184323420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.sram_ctrl_mem_partial_access.2184323420
Directory /workspace/26.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_walk.975172900
Short name T394
Test name
Test status
Simulation time 143210876 ps
CPU time 4.53 seconds
Started Apr 23 12:24:48 PM PDT 24
Finished Apr 23 12:24:54 PM PDT 24
Peak memory 201028 kb
Host smart-8f61a0ea-4b57-4210-9625-15be26f33818
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975172900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl
_mem_walk.975172900
Directory /workspace/26.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/26.sram_ctrl_multiple_keys.107747769
Short name T942
Test name
Test status
Simulation time 29604876887 ps
CPU time 610.13 seconds
Started Apr 23 12:24:54 PM PDT 24
Finished Apr 23 12:35:07 PM PDT 24
Peak memory 355368 kb
Host smart-f9bbbc65-d20c-4f6e-b91a-04c05404c9f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107747769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multip
le_keys.107747769
Directory /workspace/26.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access.919058210
Short name T256
Test name
Test status
Simulation time 933706587 ps
CPU time 16.14 seconds
Started Apr 23 12:24:51 PM PDT 24
Finished Apr 23 12:25:09 PM PDT 24
Peak memory 201832 kb
Host smart-b1e11682-ab13-4e19-819d-0a688c0e6002
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919058210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.s
ram_ctrl_partial_access.919058210
Directory /workspace/26.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.1579886430
Short name T596
Test name
Test status
Simulation time 18356232819 ps
CPU time 216.46 seconds
Started Apr 23 12:24:41 PM PDT 24
Finished Apr 23 12:28:18 PM PDT 24
Peak memory 201940 kb
Host smart-a5941272-027c-41b6-83a1-41cc21eccad4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579886430 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 26.sram_ctrl_partial_access_b2b.1579886430
Directory /workspace/26.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/26.sram_ctrl_ram_cfg.2002417369
Short name T293
Test name
Test status
Simulation time 85444687 ps
CPU time 0.75 seconds
Started Apr 23 12:24:54 PM PDT 24
Finished Apr 23 12:24:57 PM PDT 24
Peak memory 201760 kb
Host smart-8207e3fe-962b-4390-acea-7fd8f0d4adb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002417369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.2002417369
Directory /workspace/26.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/26.sram_ctrl_regwen.966049764
Short name T909
Test name
Test status
Simulation time 9022411645 ps
CPU time 382.58 seconds
Started Apr 23 12:24:37 PM PDT 24
Finished Apr 23 12:31:02 PM PDT 24
Peak memory 363032 kb
Host smart-181b42e1-d934-4266-9e5a-723f96f69b5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966049764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.966049764
Directory /workspace/26.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/26.sram_ctrl_smoke.3604977045
Short name T598
Test name
Test status
Simulation time 1734489302 ps
CPU time 36.12 seconds
Started Apr 23 12:24:51 PM PDT 24
Finished Apr 23 12:25:29 PM PDT 24
Peak memory 289044 kb
Host smart-e87fee3d-dd82-47f4-8c6f-6276141cabb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604977045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.3604977045
Directory /workspace/26.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_all.3385246400
Short name T694
Test name
Test status
Simulation time 48915182008 ps
CPU time 2595.2 seconds
Started Apr 23 12:24:53 PM PDT 24
Finished Apr 23 01:08:11 PM PDT 24
Peak memory 373040 kb
Host smart-a4c1aeac-1a99-4997-8637-836a3b16c4f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385246400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 26.sram_ctrl_stress_all.3385246400
Directory /workspace/26.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.3129888397
Short name T24
Test name
Test status
Simulation time 2983733168 ps
CPU time 1117.33 seconds
Started Apr 23 12:24:36 PM PDT 24
Finished Apr 23 12:43:16 PM PDT 24
Peak memory 377932 kb
Host smart-4757b99d-a8c5-48fe-ae72-cba064795179
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3129888397 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.3129888397
Directory /workspace/26.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_pipeline.2215894451
Short name T454
Test name
Test status
Simulation time 25469814078 ps
CPU time 331.64 seconds
Started Apr 23 12:24:44 PM PDT 24
Finished Apr 23 12:30:17 PM PDT 24
Peak memory 201932 kb
Host smart-cae1c4d7-12a8-4175-936c-16d103c3995f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215894451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.sram_ctrl_stress_pipeline.2215894451
Directory /workspace/26.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.752902975
Short name T593
Test name
Test status
Simulation time 173374556 ps
CPU time 97.99 seconds
Started Apr 23 12:24:36 PM PDT 24
Finished Apr 23 12:26:16 PM PDT 24
Peak memory 365196 kb
Host smart-9261aad8-2385-4630-8416-7ef317eb8a33
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752902975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.sram_ctrl_throughput_w_partial_write.752902975
Directory /workspace/26.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/27.sram_ctrl_access_during_key_req.3175228651
Short name T363
Test name
Test status
Simulation time 385310876 ps
CPU time 25.6 seconds
Started Apr 23 12:24:54 PM PDT 24
Finished Apr 23 12:25:22 PM PDT 24
Peak memory 237528 kb
Host smart-d44bdb1e-7fa5-42eb-8fb4-160ee240b0f8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175228651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.sram_ctrl_access_during_key_req.3175228651
Directory /workspace/27.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/27.sram_ctrl_alert_test.380354968
Short name T444
Test name
Test status
Simulation time 41362885 ps
CPU time 0.65 seconds
Started Apr 23 12:24:57 PM PDT 24
Finished Apr 23 12:24:58 PM PDT 24
Peak memory 200940 kb
Host smart-0e158661-5806-404e-9a2e-0512b5a8088d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380354968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.sram_ctrl_alert_test.380354968
Directory /workspace/27.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sram_ctrl_bijection.1328183989
Short name T485
Test name
Test status
Simulation time 2117846557 ps
CPU time 43.46 seconds
Started Apr 23 12:24:55 PM PDT 24
Finished Apr 23 12:25:40 PM PDT 24
Peak memory 201920 kb
Host smart-d35c3412-a9ff-47cc-aecb-cc5b9a263eee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328183989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection
.1328183989
Directory /workspace/27.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/27.sram_ctrl_executable.4054172693
Short name T874
Test name
Test status
Simulation time 3586387107 ps
CPU time 1092.31 seconds
Started Apr 23 12:24:59 PM PDT 24
Finished Apr 23 12:43:13 PM PDT 24
Peak memory 370768 kb
Host smart-2619f764-4109-4550-a70b-76412a5e06a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054172693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executab
le.4054172693
Directory /workspace/27.sram_ctrl_executable/latest

Test location /workspace/coverage/default/27.sram_ctrl_lc_escalation.3758262412
Short name T892
Test name
Test status
Simulation time 1922355665 ps
CPU time 7.18 seconds
Started Apr 23 12:24:46 PM PDT 24
Finished Apr 23 12:24:54 PM PDT 24
Peak memory 201924 kb
Host smart-f1b7748a-17eb-4bd4-8eb0-40565c122268
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758262412 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_es
calation.3758262412
Directory /workspace/27.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/27.sram_ctrl_max_throughput.2512750123
Short name T908
Test name
Test status
Simulation time 152142304 ps
CPU time 17.85 seconds
Started Apr 23 12:24:55 PM PDT 24
Finished Apr 23 12:25:15 PM PDT 24
Peak memory 272492 kb
Host smart-f16b41fc-7777-44f8-92e4-5d14447c0005
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512750123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 27.sram_ctrl_max_throughput.2512750123
Directory /workspace/27.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_partial_access.2515645733
Short name T68
Test name
Test status
Simulation time 87192427 ps
CPU time 2.72 seconds
Started Apr 23 12:25:07 PM PDT 24
Finished Apr 23 12:25:15 PM PDT 24
Peak memory 210132 kb
Host smart-b7fcb9fd-fb57-4504-8e72-054913c4694d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515645733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.sram_ctrl_mem_partial_access.2515645733
Directory /workspace/27.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_walk.2389036657
Short name T167
Test name
Test status
Simulation time 291474244 ps
CPU time 4.95 seconds
Started Apr 23 12:24:59 PM PDT 24
Finished Apr 23 12:25:04 PM PDT 24
Peak memory 201760 kb
Host smart-ce6bc1fd-ffd2-4dfa-b799-97001fdc3c7a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389036657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctr
l_mem_walk.2389036657
Directory /workspace/27.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/27.sram_ctrl_multiple_keys.1511386267
Short name T501
Test name
Test status
Simulation time 2442302577 ps
CPU time 400.22 seconds
Started Apr 23 12:24:45 PM PDT 24
Finished Apr 23 12:31:26 PM PDT 24
Peak memory 371748 kb
Host smart-ab5b79f0-c53a-4cd8-b2b7-ba15bb8ccd86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511386267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multi
ple_keys.1511386267
Directory /workspace/27.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access.785160475
Short name T695
Test name
Test status
Simulation time 193741298 ps
CPU time 4.6 seconds
Started Apr 23 12:24:45 PM PDT 24
Finished Apr 23 12:24:51 PM PDT 24
Peak memory 221760 kb
Host smart-e1da53dd-bd3c-48ea-9457-7385ffd89538
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785160475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.s
ram_ctrl_partial_access.785160475
Directory /workspace/27.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.1010529520
Short name T633
Test name
Test status
Simulation time 62726354259 ps
CPU time 373.29 seconds
Started Apr 23 12:24:41 PM PDT 24
Finished Apr 23 12:30:55 PM PDT 24
Peak memory 201940 kb
Host smart-dd0fb09b-35e6-41cf-bacc-7d2cb503e700
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010529520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 27.sram_ctrl_partial_access_b2b.1010529520
Directory /workspace/27.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/27.sram_ctrl_ram_cfg.3879352242
Short name T325
Test name
Test status
Simulation time 306735310 ps
CPU time 0.81 seconds
Started Apr 23 12:24:53 PM PDT 24
Finished Apr 23 12:24:56 PM PDT 24
Peak memory 201864 kb
Host smart-7ca02d8d-87db-46bb-8b0b-59ba069670f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879352242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.3879352242
Directory /workspace/27.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/27.sram_ctrl_regwen.818674670
Short name T759
Test name
Test status
Simulation time 4186646762 ps
CPU time 654.38 seconds
Started Apr 23 12:25:05 PM PDT 24
Finished Apr 23 12:36:03 PM PDT 24
Peak memory 372708 kb
Host smart-6c272ce6-6bf9-4c9f-b724-a2f2d9f97c9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818674670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.818674670
Directory /workspace/27.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/27.sram_ctrl_smoke.3789323781
Short name T264
Test name
Test status
Simulation time 409363741 ps
CPU time 12.19 seconds
Started Apr 23 12:25:03 PM PDT 24
Finished Apr 23 12:25:16 PM PDT 24
Peak memory 201920 kb
Host smart-2734d808-0a15-44c1-bc4d-2683c195c34f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789323781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.3789323781
Directory /workspace/27.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_all.2386316127
Short name T357
Test name
Test status
Simulation time 87022543131 ps
CPU time 3666.47 seconds
Started Apr 23 12:24:37 PM PDT 24
Finished Apr 23 01:25:46 PM PDT 24
Peak memory 374724 kb
Host smart-24fc61ec-54ee-46fd-9c20-6d2a97b312ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386316127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 27.sram_ctrl_stress_all.2386316127
Directory /workspace/27.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.4248749060
Short name T450
Test name
Test status
Simulation time 5087794015 ps
CPU time 474.62 seconds
Started Apr 23 12:24:39 PM PDT 24
Finished Apr 23 12:32:35 PM PDT 24
Peak memory 371952 kb
Host smart-01f1d1cf-4784-4587-8754-15e149d48b46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4248749060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.4248749060
Directory /workspace/27.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_pipeline.3380706898
Short name T168
Test name
Test status
Simulation time 3793635061 ps
CPU time 353.62 seconds
Started Apr 23 12:24:42 PM PDT 24
Finished Apr 23 12:30:37 PM PDT 24
Peak memory 201976 kb
Host smart-00bc0e80-de1f-4011-a36c-b1cb3daa9596
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380706898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.sram_ctrl_stress_pipeline.3380706898
Directory /workspace/27.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.3038510792
Short name T214
Test name
Test status
Simulation time 86509577 ps
CPU time 9.86 seconds
Started Apr 23 12:24:54 PM PDT 24
Finished Apr 23 12:25:06 PM PDT 24
Peak memory 250992 kb
Host smart-e1e4e9d8-bd56-4ed5-8efa-142fdf7b9fd6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038510792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.sram_ctrl_throughput_w_partial_write.3038510792
Directory /workspace/27.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/28.sram_ctrl_access_during_key_req.3490392410
Short name T778
Test name
Test status
Simulation time 3327938141 ps
CPU time 949.12 seconds
Started Apr 23 12:24:51 PM PDT 24
Finished Apr 23 12:40:42 PM PDT 24
Peak memory 372700 kb
Host smart-48cca7d7-6244-43a0-8f3c-3c9332af5913
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490392410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.sram_ctrl_access_during_key_req.3490392410
Directory /workspace/28.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/28.sram_ctrl_alert_test.1114687186
Short name T197
Test name
Test status
Simulation time 40552555 ps
CPU time 0.6 seconds
Started Apr 23 12:24:48 PM PDT 24
Finished Apr 23 12:24:50 PM PDT 24
Peak memory 201096 kb
Host smart-db9987a6-118c-4dcc-8c2e-2501dc9228e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114687186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.sram_ctrl_alert_test.1114687186
Directory /workspace/28.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sram_ctrl_bijection.936722810
Short name T286
Test name
Test status
Simulation time 18554428995 ps
CPU time 68.22 seconds
Started Apr 23 12:24:53 PM PDT 24
Finished Apr 23 12:26:03 PM PDT 24
Peak memory 201960 kb
Host smart-a143cb08-31dc-493c-898b-19215b66f3d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936722810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection.
936722810
Directory /workspace/28.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/28.sram_ctrl_executable.2419118158
Short name T142
Test name
Test status
Simulation time 23182131342 ps
CPU time 1019.85 seconds
Started Apr 23 12:25:01 PM PDT 24
Finished Apr 23 12:42:02 PM PDT 24
Peak memory 355360 kb
Host smart-977684ab-d9db-4520-80f0-8a5a5259389a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419118158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executab
le.2419118158
Directory /workspace/28.sram_ctrl_executable/latest

Test location /workspace/coverage/default/28.sram_ctrl_lc_escalation.4104249939
Short name T518
Test name
Test status
Simulation time 637654945 ps
CPU time 6.43 seconds
Started Apr 23 12:25:05 PM PDT 24
Finished Apr 23 12:25:14 PM PDT 24
Peak memory 201956 kb
Host smart-2b1eb4da-ff85-4f2f-82bc-d6c805404fed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104249939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_es
calation.4104249939
Directory /workspace/28.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/28.sram_ctrl_max_throughput.229938970
Short name T328
Test name
Test status
Simulation time 183949292 ps
CPU time 30.32 seconds
Started Apr 23 12:24:59 PM PDT 24
Finished Apr 23 12:25:30 PM PDT 24
Peak memory 293144 kb
Host smart-7729290c-2bd4-49c5-bfe9-84fec4e55e45
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229938970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.sram_ctrl_max_throughput.229938970
Directory /workspace/28.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_partial_access.319722902
Short name T69
Test name
Test status
Simulation time 170693715 ps
CPU time 3 seconds
Started Apr 23 12:24:57 PM PDT 24
Finished Apr 23 12:25:01 PM PDT 24
Peak memory 210116 kb
Host smart-b3a55db3-da41-4438-90c6-ce489829c9b4
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319722902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.sram_ctrl_mem_partial_access.319722902
Directory /workspace/28.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_walk.4005087309
Short name T520
Test name
Test status
Simulation time 138714698 ps
CPU time 8.25 seconds
Started Apr 23 12:25:07 PM PDT 24
Finished Apr 23 12:25:20 PM PDT 24
Peak memory 201796 kb
Host smart-6c6d67c4-7e10-4cd8-b6a0-4e70519eb61b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005087309 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctr
l_mem_walk.4005087309
Directory /workspace/28.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/28.sram_ctrl_multiple_keys.2762076621
Short name T889
Test name
Test status
Simulation time 84905529899 ps
CPU time 612.51 seconds
Started Apr 23 12:24:57 PM PDT 24
Finished Apr 23 12:35:11 PM PDT 24
Peak memory 370720 kb
Host smart-b8f1d0b1-11e1-4bbb-9f20-f6e401635f90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762076621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multi
ple_keys.2762076621
Directory /workspace/28.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access.2935209656
Short name T615
Test name
Test status
Simulation time 216943798 ps
CPU time 10.23 seconds
Started Apr 23 12:24:54 PM PDT 24
Finished Apr 23 12:25:06 PM PDT 24
Peak memory 201848 kb
Host smart-53b6af63-5e6c-4451-8c81-f9bd836655a7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935209656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
sram_ctrl_partial_access.2935209656
Directory /workspace/28.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.3179075051
Short name T597
Test name
Test status
Simulation time 90152743226 ps
CPU time 443.68 seconds
Started Apr 23 12:25:00 PM PDT 24
Finished Apr 23 12:32:25 PM PDT 24
Peak memory 201908 kb
Host smart-4c756229-8111-49ac-ab6d-ca97655d2424
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179075051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 28.sram_ctrl_partial_access_b2b.3179075051
Directory /workspace/28.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/28.sram_ctrl_ram_cfg.198143921
Short name T945
Test name
Test status
Simulation time 43319203 ps
CPU time 0.77 seconds
Started Apr 23 12:25:01 PM PDT 24
Finished Apr 23 12:25:03 PM PDT 24
Peak memory 201944 kb
Host smart-fe16bead-dc68-49a3-8368-35306410d628
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198143921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.198143921
Directory /workspace/28.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/28.sram_ctrl_regwen.1521900033
Short name T724
Test name
Test status
Simulation time 1019292943 ps
CPU time 645.31 seconds
Started Apr 23 12:25:04 PM PDT 24
Finished Apr 23 12:35:51 PM PDT 24
Peak memory 373688 kb
Host smart-ebdb3e21-3018-42fa-b5f8-2f762de7acb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521900033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.1521900033
Directory /workspace/28.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/28.sram_ctrl_smoke.3696859029
Short name T482
Test name
Test status
Simulation time 378091728 ps
CPU time 6.14 seconds
Started Apr 23 12:24:38 PM PDT 24
Finished Apr 23 12:24:46 PM PDT 24
Peak memory 201896 kb
Host smart-a692e0fb-31be-461c-b775-37e1dbcc8dae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696859029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.3696859029
Directory /workspace/28.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_all.2483810230
Short name T612
Test name
Test status
Simulation time 43446578108 ps
CPU time 823.26 seconds
Started Apr 23 12:25:08 PM PDT 24
Finished Apr 23 12:38:56 PM PDT 24
Peak memory 367924 kb
Host smart-37772a38-4e0f-43d3-abc5-892467ea94ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483810230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 28.sram_ctrl_stress_all.2483810230
Directory /workspace/28.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.271026066
Short name T229
Test name
Test status
Simulation time 603432699 ps
CPU time 254.82 seconds
Started Apr 23 12:25:05 PM PDT 24
Finished Apr 23 12:29:27 PM PDT 24
Peak memory 376936 kb
Host smart-9ea509f3-6fd0-4a71-943a-b67f93b0e6a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=271026066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.271026066
Directory /workspace/28.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_pipeline.3722786532
Short name T172
Test name
Test status
Simulation time 51925079663 ps
CPU time 332.14 seconds
Started Apr 23 12:24:56 PM PDT 24
Finished Apr 23 12:30:30 PM PDT 24
Peak memory 201880 kb
Host smart-15db1e2a-bf04-4ef0-9aae-220489398ac6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722786532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.sram_ctrl_stress_pipeline.3722786532
Directory /workspace/28.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.2328686561
Short name T378
Test name
Test status
Simulation time 150258206 ps
CPU time 111.37 seconds
Started Apr 23 12:24:45 PM PDT 24
Finished Apr 23 12:26:38 PM PDT 24
Peak memory 368212 kb
Host smart-fee5e8ea-255b-413c-9c48-43a5d1e89cff
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328686561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.sram_ctrl_throughput_w_partial_write.2328686561
Directory /workspace/28.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/29.sram_ctrl_access_during_key_req.661966892
Short name T404
Test name
Test status
Simulation time 1494767315 ps
CPU time 385.04 seconds
Started Apr 23 12:25:06 PM PDT 24
Finished Apr 23 12:31:35 PM PDT 24
Peak memory 366752 kb
Host smart-3dc7b1f1-8a0e-4731-9a61-9e935a727b8d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661966892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 29.sram_ctrl_access_during_key_req.661966892
Directory /workspace/29.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/29.sram_ctrl_alert_test.2998946005
Short name T794
Test name
Test status
Simulation time 19937116 ps
CPU time 0.6 seconds
Started Apr 23 12:25:00 PM PDT 24
Finished Apr 23 12:25:02 PM PDT 24
Peak memory 201684 kb
Host smart-c292a976-c833-4d52-8e62-1621217a6d1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998946005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.sram_ctrl_alert_test.2998946005
Directory /workspace/29.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sram_ctrl_bijection.631614773
Short name T923
Test name
Test status
Simulation time 3313927493 ps
CPU time 26.55 seconds
Started Apr 23 12:24:44 PM PDT 24
Finished Apr 23 12:25:12 PM PDT 24
Peak memory 201940 kb
Host smart-e9105665-b988-4878-9b69-affa1c0bb2da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631614773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection.
631614773
Directory /workspace/29.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/29.sram_ctrl_executable.1409951478
Short name T397
Test name
Test status
Simulation time 2187066887 ps
CPU time 39.7 seconds
Started Apr 23 12:25:01 PM PDT 24
Finished Apr 23 12:25:41 PM PDT 24
Peak memory 201952 kb
Host smart-39406f1c-4fbb-42e1-a6d3-4d9831656dbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409951478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executab
le.1409951478
Directory /workspace/29.sram_ctrl_executable/latest

Test location /workspace/coverage/default/29.sram_ctrl_lc_escalation.3217398895
Short name T298
Test name
Test status
Simulation time 432780305 ps
CPU time 4.75 seconds
Started Apr 23 12:25:07 PM PDT 24
Finished Apr 23 12:25:16 PM PDT 24
Peak memory 201924 kb
Host smart-e2e99b24-52d7-46ed-b717-55e4759c2506
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217398895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_es
calation.3217398895
Directory /workspace/29.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/29.sram_ctrl_max_throughput.1448341579
Short name T292
Test name
Test status
Simulation time 82679441 ps
CPU time 22.2 seconds
Started Apr 23 12:24:46 PM PDT 24
Finished Apr 23 12:25:09 PM PDT 24
Peak memory 283612 kb
Host smart-431f2934-c31e-4ae5-b6c8-86f2ca2057fa
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448341579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 29.sram_ctrl_max_throughput.1448341579
Directory /workspace/29.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_partial_access.1993543977
Short name T742
Test name
Test status
Simulation time 64962478 ps
CPU time 4.15 seconds
Started Apr 23 12:24:47 PM PDT 24
Finished Apr 23 12:24:53 PM PDT 24
Peak memory 210012 kb
Host smart-d6b8ca1f-de15-4965-9ba3-473720226793
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993543977 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.sram_ctrl_mem_partial_access.1993543977
Directory /workspace/29.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_walk.2645365531
Short name T912
Test name
Test status
Simulation time 2630837017 ps
CPU time 9.99 seconds
Started Apr 23 12:25:06 PM PDT 24
Finished Apr 23 12:25:18 PM PDT 24
Peak memory 201852 kb
Host smart-53352fc4-0434-4753-8cc8-b3b9cf9e4127
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645365531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctr
l_mem_walk.2645365531
Directory /workspace/29.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/29.sram_ctrl_multiple_keys.78532842
Short name T209
Test name
Test status
Simulation time 8751075668 ps
CPU time 823.02 seconds
Started Apr 23 12:25:00 PM PDT 24
Finished Apr 23 12:38:44 PM PDT 24
Peak memory 372768 kb
Host smart-7df2858f-8049-4ae4-935f-d8a1041329ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78532842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip
le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multipl
e_keys.78532842
Directory /workspace/29.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access.1777151704
Short name T810
Test name
Test status
Simulation time 265105919 ps
CPU time 11.99 seconds
Started Apr 23 12:24:56 PM PDT 24
Finished Apr 23 12:25:09 PM PDT 24
Peak memory 248680 kb
Host smart-2bed2f9c-4322-42b0-a3a3-6929a636dac9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777151704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
sram_ctrl_partial_access.1777151704
Directory /workspace/29.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.2199330898
Short name T344
Test name
Test status
Simulation time 36293690017 ps
CPU time 346.77 seconds
Started Apr 23 12:25:02 PM PDT 24
Finished Apr 23 12:30:50 PM PDT 24
Peak memory 201936 kb
Host smart-2fb5429b-bf90-467f-beaf-6ea0a0206d31
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199330898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 29.sram_ctrl_partial_access_b2b.2199330898
Directory /workspace/29.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/29.sram_ctrl_ram_cfg.878489671
Short name T873
Test name
Test status
Simulation time 59272310 ps
CPU time 0.72 seconds
Started Apr 23 12:24:45 PM PDT 24
Finished Apr 23 12:24:47 PM PDT 24
Peak memory 201932 kb
Host smart-4110c3a8-3712-4738-96cc-4c10d820391e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878489671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.878489671
Directory /workspace/29.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/29.sram_ctrl_regwen.2834334659
Short name T919
Test name
Test status
Simulation time 3197695137 ps
CPU time 944.85 seconds
Started Apr 23 12:24:43 PM PDT 24
Finished Apr 23 12:40:28 PM PDT 24
Peak memory 373576 kb
Host smart-9cb867c7-cfaf-4b9b-afbe-747bba081d80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834334659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.2834334659
Directory /workspace/29.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/29.sram_ctrl_smoke.3730442525
Short name T416
Test name
Test status
Simulation time 341253329 ps
CPU time 10.72 seconds
Started Apr 23 12:24:51 PM PDT 24
Finished Apr 23 12:25:04 PM PDT 24
Peak memory 201888 kb
Host smart-f416431e-3012-4a87-b4e6-7e807e4e97f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730442525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.3730442525
Directory /workspace/29.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_all.964670701
Short name T417
Test name
Test status
Simulation time 34262733810 ps
CPU time 3239.95 seconds
Started Apr 23 12:25:01 PM PDT 24
Finished Apr 23 01:19:11 PM PDT 24
Peak memory 374780 kb
Host smart-8d69228c-8ce2-4025-8d5c-1e0afd97b358
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964670701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 29.sram_ctrl_stress_all.964670701
Directory /workspace/29.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1658714978
Short name T102
Test name
Test status
Simulation time 4265379289 ps
CPU time 79.25 seconds
Started Apr 23 12:25:14 PM PDT 24
Finished Apr 23 12:26:36 PM PDT 24
Peak memory 338352 kb
Host smart-d06a3c45-1f5b-47ff-9d1e-ee08ead26eba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1658714978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.1658714978
Directory /workspace/29.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_pipeline.1181878711
Short name T536
Test name
Test status
Simulation time 13638433769 ps
CPU time 221.7 seconds
Started Apr 23 12:25:05 PM PDT 24
Finished Apr 23 12:28:49 PM PDT 24
Peak memory 201908 kb
Host smart-f5a0ee56-45ce-4dfa-a6c2-3dbba8dc0b36
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181878711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.sram_ctrl_stress_pipeline.1181878711
Directory /workspace/29.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.3748675159
Short name T306
Test name
Test status
Simulation time 88972921 ps
CPU time 19.45 seconds
Started Apr 23 12:25:00 PM PDT 24
Finished Apr 23 12:25:20 PM PDT 24
Peak memory 272444 kb
Host smart-21c2d7ce-30f6-428e-863d-69c69a3e951f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748675159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.sram_ctrl_throughput_w_partial_write.3748675159
Directory /workspace/29.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/3.sram_ctrl_access_during_key_req.778008632
Short name T402
Test name
Test status
Simulation time 4475930522 ps
CPU time 1099.85 seconds
Started Apr 23 12:23:12 PM PDT 24
Finished Apr 23 12:41:33 PM PDT 24
Peak memory 372624 kb
Host smart-5da64e54-6f48-49a2-9416-6907fd36f826
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778008632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 3.sram_ctrl_access_during_key_req.778008632
Directory /workspace/3.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/3.sram_ctrl_alert_test.4143665466
Short name T711
Test name
Test status
Simulation time 13352180 ps
CPU time 0.71 seconds
Started Apr 23 12:24:46 PM PDT 24
Finished Apr 23 12:24:48 PM PDT 24
Peak memory 201648 kb
Host smart-25f8a80f-6a24-4398-89e4-5ad3c6e9d86a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143665466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_alert_test.4143665466
Directory /workspace/3.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sram_ctrl_bijection.3316053966
Short name T37
Test name
Test status
Simulation time 4745733834 ps
CPU time 67.79 seconds
Started Apr 23 12:22:34 PM PDT 24
Finished Apr 23 12:23:43 PM PDT 24
Peak memory 201800 kb
Host smart-fc5a197f-c2c3-45bd-b038-e47a48fc71db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316053966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.
3316053966
Directory /workspace/3.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/3.sram_ctrl_executable.3828253419
Short name T223
Test name
Test status
Simulation time 10037513444 ps
CPU time 748.78 seconds
Started Apr 23 12:23:20 PM PDT 24
Finished Apr 23 12:35:49 PM PDT 24
Peak memory 346144 kb
Host smart-e787479b-906a-4668-a20d-7bdf9a64a631
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828253419 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executabl
e.3828253419
Directory /workspace/3.sram_ctrl_executable/latest

Test location /workspace/coverage/default/3.sram_ctrl_lc_escalation.3641968745
Short name T814
Test name
Test status
Simulation time 6323888319 ps
CPU time 5.24 seconds
Started Apr 23 12:24:34 PM PDT 24
Finished Apr 23 12:24:41 PM PDT 24
Peak memory 201948 kb
Host smart-240d3984-2a84-4c9f-8d6f-144cac013adc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641968745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esc
alation.3641968745
Directory /workspace/3.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/3.sram_ctrl_max_throughput.2583583651
Short name T581
Test name
Test status
Simulation time 71754814 ps
CPU time 13.47 seconds
Started Apr 23 12:23:22 PM PDT 24
Finished Apr 23 12:23:37 PM PDT 24
Peak memory 254628 kb
Host smart-43ee60bb-3236-48a5-85aa-9cf09474b1f4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583583651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.sram_ctrl_max_throughput.2583583651
Directory /workspace/3.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_partial_access.2529445880
Short name T534
Test name
Test status
Simulation time 297267018 ps
CPU time 2.81 seconds
Started Apr 23 12:24:28 PM PDT 24
Finished Apr 23 12:24:32 PM PDT 24
Peak memory 208656 kb
Host smart-b4be5ea7-7f4c-4a2c-9406-ba19c53956a7
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529445880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.sram_ctrl_mem_partial_access.2529445880
Directory /workspace/3.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_walk.3170750425
Short name T423
Test name
Test status
Simulation time 6204205341 ps
CPU time 10.52 seconds
Started Apr 23 12:24:29 PM PDT 24
Finished Apr 23 12:24:40 PM PDT 24
Peak memory 201572 kb
Host smart-36fca041-baae-4d8d-9bfd-a5ad6b312ab4
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170750425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl
_mem_walk.3170750425
Directory /workspace/3.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/3.sram_ctrl_multiple_keys.3247486510
Short name T342
Test name
Test status
Simulation time 13892831083 ps
CPU time 932.48 seconds
Started Apr 23 12:22:32 PM PDT 24
Finished Apr 23 12:38:05 PM PDT 24
Peak memory 373136 kb
Host smart-a8d2de8b-fde6-43d4-8bb6-448d726c68d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247486510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multip
le_keys.3247486510
Directory /workspace/3.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access.651751989
Short name T187
Test name
Test status
Simulation time 933115497 ps
CPU time 15.41 seconds
Started Apr 23 12:23:22 PM PDT 24
Finished Apr 23 12:23:39 PM PDT 24
Peak memory 255432 kb
Host smart-2ca958b1-456c-49e5-9469-107eee4269a7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651751989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sr
am_ctrl_partial_access.651751989
Directory /workspace/3.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.4018250688
Short name T89
Test name
Test status
Simulation time 5190564242 ps
CPU time 356.35 seconds
Started Apr 23 12:24:32 PM PDT 24
Finished Apr 23 12:30:29 PM PDT 24
Peak memory 201912 kb
Host smart-d5a35945-93f1-4ec5-a77b-c54c85fd907d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018250688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 3.sram_ctrl_partial_access_b2b.4018250688
Directory /workspace/3.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/3.sram_ctrl_ram_cfg.3895181817
Short name T154
Test name
Test status
Simulation time 86742695 ps
CPU time 0.83 seconds
Started Apr 23 12:24:44 PM PDT 24
Finished Apr 23 12:24:45 PM PDT 24
Peak memory 201900 kb
Host smart-ec3cdc5e-a9d0-4beb-9fce-f70f298085f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895181817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.3895181817
Directory /workspace/3.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/3.sram_ctrl_regwen.2839638254
Short name T676
Test name
Test status
Simulation time 17154365722 ps
CPU time 909.86 seconds
Started Apr 23 12:24:31 PM PDT 24
Finished Apr 23 12:39:41 PM PDT 24
Peak memory 372764 kb
Host smart-9bc1f7d7-f5d9-4bd9-b9bb-956454ec59aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839638254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.2839638254
Directory /workspace/3.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/3.sram_ctrl_smoke.3499381463
Short name T371
Test name
Test status
Simulation time 139490333 ps
CPU time 11.26 seconds
Started Apr 23 12:21:38 PM PDT 24
Finished Apr 23 12:21:50 PM PDT 24
Peak memory 255076 kb
Host smart-4042afde-6513-4e79-a23f-8e6b5e117ed9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499381463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.3499381463
Directory /workspace/3.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_all.2731947121
Short name T515
Test name
Test status
Simulation time 170166533269 ps
CPU time 2999.05 seconds
Started Apr 23 12:23:12 PM PDT 24
Finished Apr 23 01:13:12 PM PDT 24
Peak memory 374368 kb
Host smart-8b9adcae-1cb6-488e-a205-5f9b85344cab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731947121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 3.sram_ctrl_stress_all.2731947121
Directory /workspace/3.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.1972727739
Short name T276
Test name
Test status
Simulation time 1142122880 ps
CPU time 35.52 seconds
Started Apr 23 12:23:15 PM PDT 24
Finished Apr 23 12:23:51 PM PDT 24
Peak memory 252236 kb
Host smart-93603f32-6cc7-4278-97dd-afa656ca652a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1972727739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.1972727739
Directory /workspace/3.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_pipeline.2174190254
Short name T869
Test name
Test status
Simulation time 4247911128 ps
CPU time 165.51 seconds
Started Apr 23 12:24:28 PM PDT 24
Finished Apr 23 12:27:15 PM PDT 24
Peak memory 200712 kb
Host smart-5ae42934-c261-4715-81f0-e140ab900218
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174190254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.sram_ctrl_stress_pipeline.2174190254
Directory /workspace/3.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.883433080
Short name T849
Test name
Test status
Simulation time 485236553 ps
CPU time 47.79 seconds
Started Apr 23 12:24:49 PM PDT 24
Finished Apr 23 12:25:38 PM PDT 24
Peak memory 322532 kb
Host smart-ebe84ac2-7015-40d1-a345-de50c48977c4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883433080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.sram_ctrl_throughput_w_partial_write.883433080
Directory /workspace/3.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/30.sram_ctrl_access_during_key_req.1272645384
Short name T938
Test name
Test status
Simulation time 12311038111 ps
CPU time 1270.93 seconds
Started Apr 23 12:24:54 PM PDT 24
Finished Apr 23 12:46:07 PM PDT 24
Peak memory 372904 kb
Host smart-d3ba54d6-a264-406a-82d8-ea9206eee0dd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272645384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.sram_ctrl_access_during_key_req.1272645384
Directory /workspace/30.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/30.sram_ctrl_alert_test.2926505537
Short name T530
Test name
Test status
Simulation time 16730771 ps
CPU time 0.66 seconds
Started Apr 23 12:24:44 PM PDT 24
Finished Apr 23 12:24:46 PM PDT 24
Peak memory 201728 kb
Host smart-c09c8066-4bd2-4709-bb4a-7baa526a7755
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926505537 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.sram_ctrl_alert_test.2926505537
Directory /workspace/30.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sram_ctrl_bijection.3893363858
Short name T906
Test name
Test status
Simulation time 2923803155 ps
CPU time 43.32 seconds
Started Apr 23 12:24:44 PM PDT 24
Finished Apr 23 12:25:28 PM PDT 24
Peak memory 202012 kb
Host smart-004e1ff9-5653-4f00-b9dd-182660127c3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893363858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection
.3893363858
Directory /workspace/30.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/30.sram_ctrl_executable.806989448
Short name T801
Test name
Test status
Simulation time 2972326784 ps
CPU time 509.03 seconds
Started Apr 23 12:25:06 PM PDT 24
Finished Apr 23 12:33:39 PM PDT 24
Peak memory 351128 kb
Host smart-09999b62-d5cf-4ff5-9a31-515ff55d6174
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806989448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executabl
e.806989448
Directory /workspace/30.sram_ctrl_executable/latest

Test location /workspace/coverage/default/30.sram_ctrl_lc_escalation.2277555343
Short name T752
Test name
Test status
Simulation time 500158696 ps
CPU time 7.29 seconds
Started Apr 23 12:24:45 PM PDT 24
Finished Apr 23 12:24:53 PM PDT 24
Peak memory 201884 kb
Host smart-377c0dca-2466-4fa9-a4fe-78155e28f614
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277555343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_es
calation.2277555343
Directory /workspace/30.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/30.sram_ctrl_max_throughput.3121984302
Short name T802
Test name
Test status
Simulation time 96226750 ps
CPU time 2.02 seconds
Started Apr 23 12:24:58 PM PDT 24
Finished Apr 23 12:25:00 PM PDT 24
Peak memory 214872 kb
Host smart-9c2fd042-5c70-4b52-a56e-b1c5ce239bcd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121984302 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.sram_ctrl_max_throughput.3121984302
Directory /workspace/30.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_partial_access.3050928474
Short name T72
Test name
Test status
Simulation time 526165954 ps
CPU time 4.16 seconds
Started Apr 23 12:24:45 PM PDT 24
Finished Apr 23 12:24:50 PM PDT 24
Peak memory 210032 kb
Host smart-59127214-22be-4460-8f6b-7e060e75eddd
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050928474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.sram_ctrl_mem_partial_access.3050928474
Directory /workspace/30.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_walk.3141657167
Short name T747
Test name
Test status
Simulation time 1819019233 ps
CPU time 9.19 seconds
Started Apr 23 12:25:07 PM PDT 24
Finished Apr 23 12:25:22 PM PDT 24
Peak memory 201800 kb
Host smart-7e976c61-e4df-452c-8ddc-2d6a03f7c699
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141657167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctr
l_mem_walk.3141657167
Directory /workspace/30.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/30.sram_ctrl_multiple_keys.1202603275
Short name T576
Test name
Test status
Simulation time 31307605747 ps
CPU time 465.5 seconds
Started Apr 23 12:24:53 PM PDT 24
Finished Apr 23 12:32:41 PM PDT 24
Peak memory 371992 kb
Host smart-e5fb9ea1-16f9-424a-826e-a0a2372b836e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202603275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multi
ple_keys.1202603275
Directory /workspace/30.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access.2770245895
Short name T155
Test name
Test status
Simulation time 344008134 ps
CPU time 6.5 seconds
Started Apr 23 12:24:47 PM PDT 24
Finished Apr 23 12:24:54 PM PDT 24
Peak memory 229108 kb
Host smart-a534a220-147e-418e-9533-437274a516ad
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770245895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
sram_ctrl_partial_access.2770245895
Directory /workspace/30.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.2740732383
Short name T507
Test name
Test status
Simulation time 20992097116 ps
CPU time 395.3 seconds
Started Apr 23 12:25:07 PM PDT 24
Finished Apr 23 12:31:48 PM PDT 24
Peak memory 201872 kb
Host smart-2acc4f3c-353f-46c8-b52e-c62097dfca80
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740732383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 30.sram_ctrl_partial_access_b2b.2740732383
Directory /workspace/30.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/30.sram_ctrl_ram_cfg.606664838
Short name T842
Test name
Test status
Simulation time 38810397 ps
CPU time 0.74 seconds
Started Apr 23 12:25:06 PM PDT 24
Finished Apr 23 12:25:11 PM PDT 24
Peak memory 202004 kb
Host smart-1ba5900a-50e6-46c7-9e7c-74846b080496
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606664838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.606664838
Directory /workspace/30.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/30.sram_ctrl_regwen.338897289
Short name T410
Test name
Test status
Simulation time 12425454317 ps
CPU time 873.66 seconds
Started Apr 23 12:24:46 PM PDT 24
Finished Apr 23 12:39:21 PM PDT 24
Peak memory 371768 kb
Host smart-d2cf3d34-912d-4d33-8ade-48049932deaf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338897289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.338897289
Directory /workspace/30.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/30.sram_ctrl_smoke.2915729581
Short name T489
Test name
Test status
Simulation time 600594359 ps
CPU time 111.72 seconds
Started Apr 23 12:24:47 PM PDT 24
Finished Apr 23 12:26:40 PM PDT 24
Peak memory 365020 kb
Host smart-55c104bb-5fb4-4bfb-976f-55a64354f6ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915729581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.2915729581
Directory /workspace/30.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_all.3461732349
Short name T112
Test name
Test status
Simulation time 23061936616 ps
CPU time 5210.01 seconds
Started Apr 23 12:24:49 PM PDT 24
Finished Apr 23 01:51:41 PM PDT 24
Peak memory 374764 kb
Host smart-5fec42fc-cedc-45d3-9d44-a9d5f8db2d0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461732349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 30.sram_ctrl_stress_all.3461732349
Directory /workspace/30.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.3047276599
Short name T497
Test name
Test status
Simulation time 6895373999 ps
CPU time 135.98 seconds
Started Apr 23 12:25:05 PM PDT 24
Finished Apr 23 12:27:22 PM PDT 24
Peak memory 345992 kb
Host smart-83173d1a-9843-43ab-86f8-c173637ed038
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3047276599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.3047276599
Directory /workspace/30.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_pipeline.3887489952
Short name T691
Test name
Test status
Simulation time 55716866217 ps
CPU time 273.26 seconds
Started Apr 23 12:25:05 PM PDT 24
Finished Apr 23 12:29:41 PM PDT 24
Peak memory 201928 kb
Host smart-2b171c69-0bf6-4380-a7fb-7df416597ded
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887489952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.sram_ctrl_stress_pipeline.3887489952
Directory /workspace/30.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.767993532
Short name T792
Test name
Test status
Simulation time 547550552 ps
CPU time 44.59 seconds
Started Apr 23 12:25:11 PM PDT 24
Finished Apr 23 12:26:00 PM PDT 24
Peak memory 319260 kb
Host smart-fc345e92-4d46-4f56-a78d-e727ea162cd3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767993532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.sram_ctrl_throughput_w_partial_write.767993532
Directory /workspace/30.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/31.sram_ctrl_access_during_key_req.1858382266
Short name T553
Test name
Test status
Simulation time 17112420449 ps
CPU time 497.21 seconds
Started Apr 23 12:25:06 PM PDT 24
Finished Apr 23 12:33:27 PM PDT 24
Peak memory 370628 kb
Host smart-b6328ce6-5cf9-4b04-a718-c574206845e0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858382266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.sram_ctrl_access_during_key_req.1858382266
Directory /workspace/31.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/31.sram_ctrl_alert_test.3053272184
Short name T322
Test name
Test status
Simulation time 37774223 ps
CPU time 0.65 seconds
Started Apr 23 12:25:07 PM PDT 24
Finished Apr 23 12:25:12 PM PDT 24
Peak memory 201692 kb
Host smart-0818ff78-4ffe-420f-8613-45578d17e59d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053272184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.sram_ctrl_alert_test.3053272184
Directory /workspace/31.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sram_ctrl_bijection.4186671485
Short name T705
Test name
Test status
Simulation time 6480709408 ps
CPU time 52.22 seconds
Started Apr 23 12:24:42 PM PDT 24
Finished Apr 23 12:25:36 PM PDT 24
Peak memory 201948 kb
Host smart-3f05bbac-b290-4501-84b2-b49ab4019032
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186671485 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection
.4186671485
Directory /workspace/31.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/31.sram_ctrl_executable.2143429290
Short name T403
Test name
Test status
Simulation time 9286417740 ps
CPU time 699.35 seconds
Started Apr 23 12:24:44 PM PDT 24
Finished Apr 23 12:36:25 PM PDT 24
Peak memory 368532 kb
Host smart-328c61b4-9d28-407f-8964-85a9b0e5c290
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143429290 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executab
le.2143429290
Directory /workspace/31.sram_ctrl_executable/latest

Test location /workspace/coverage/default/31.sram_ctrl_lc_escalation.2271300603
Short name T393
Test name
Test status
Simulation time 4003164657 ps
CPU time 3.23 seconds
Started Apr 23 12:25:05 PM PDT 24
Finished Apr 23 12:25:10 PM PDT 24
Peak memory 202036 kb
Host smart-d2ded4c0-df0a-498d-a9b8-89ddd1c4c812
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271300603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_es
calation.2271300603
Directory /workspace/31.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/31.sram_ctrl_max_throughput.2704221121
Short name T763
Test name
Test status
Simulation time 122952298 ps
CPU time 16.31 seconds
Started Apr 23 12:24:56 PM PDT 24
Finished Apr 23 12:25:13 PM PDT 24
Peak memory 271416 kb
Host smart-dd68fb90-b79c-45c4-b267-b2367e2a86ff
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704221121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.sram_ctrl_max_throughput.2704221121
Directory /workspace/31.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_partial_access.2831146321
Short name T234
Test name
Test status
Simulation time 153326541 ps
CPU time 2.81 seconds
Started Apr 23 12:24:44 PM PDT 24
Finished Apr 23 12:24:47 PM PDT 24
Peak memory 210096 kb
Host smart-a07779ef-5e58-4fe9-b9a1-522c68743a95
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831146321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.sram_ctrl_mem_partial_access.2831146321
Directory /workspace/31.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_walk.1371809829
Short name T772
Test name
Test status
Simulation time 2723618648 ps
CPU time 10.29 seconds
Started Apr 23 12:25:05 PM PDT 24
Finished Apr 23 12:25:17 PM PDT 24
Peak memory 201808 kb
Host smart-980a6162-032f-4834-b405-874b10703bd4
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371809829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctr
l_mem_walk.1371809829
Directory /workspace/31.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/31.sram_ctrl_multiple_keys.2046054172
Short name T358
Test name
Test status
Simulation time 4250739739 ps
CPU time 441.45 seconds
Started Apr 23 12:25:02 PM PDT 24
Finished Apr 23 12:32:25 PM PDT 24
Peak memory 373772 kb
Host smart-5471cd8e-d535-4bea-abb4-d3841e36362b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046054172 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multi
ple_keys.2046054172
Directory /workspace/31.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access.2510745528
Short name T460
Test name
Test status
Simulation time 4485536345 ps
CPU time 15.52 seconds
Started Apr 23 12:25:05 PM PDT 24
Finished Apr 23 12:25:23 PM PDT 24
Peak memory 201916 kb
Host smart-69c639aa-a5e1-43f3-b4ae-7d15d1545ee6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510745528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
sram_ctrl_partial_access.2510745528
Directory /workspace/31.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.3484725922
Short name T271
Test name
Test status
Simulation time 68091477686 ps
CPU time 444.22 seconds
Started Apr 23 12:25:07 PM PDT 24
Finished Apr 23 12:32:37 PM PDT 24
Peak memory 201784 kb
Host smart-60b7e05f-0f78-4118-b10b-f621fe74d90b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484725922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 31.sram_ctrl_partial_access_b2b.3484725922
Directory /workspace/31.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/31.sram_ctrl_ram_cfg.2831713962
Short name T834
Test name
Test status
Simulation time 94685248 ps
CPU time 0.78 seconds
Started Apr 23 12:25:06 PM PDT 24
Finished Apr 23 12:25:10 PM PDT 24
Peak memory 201972 kb
Host smart-da1707c9-9598-4daf-bea9-ddda37a14c28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831713962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.2831713962
Directory /workspace/31.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/31.sram_ctrl_regwen.2278703062
Short name T50
Test name
Test status
Simulation time 34379968602 ps
CPU time 700.92 seconds
Started Apr 23 12:24:53 PM PDT 24
Finished Apr 23 12:36:36 PM PDT 24
Peak memory 374492 kb
Host smart-eb12116e-bfc2-4ef8-b8e5-c8b6e15b752f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278703062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.2278703062
Directory /workspace/31.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/31.sram_ctrl_smoke.1674961893
Short name T146
Test name
Test status
Simulation time 253497776 ps
CPU time 2.38 seconds
Started Apr 23 12:24:53 PM PDT 24
Finished Apr 23 12:24:58 PM PDT 24
Peak memory 201856 kb
Host smart-e8957a65-f2d6-4bf1-a47b-c7d5ab4dbcf1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674961893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.1674961893
Directory /workspace/31.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_all.3019078029
Short name T108
Test name
Test status
Simulation time 65725194485 ps
CPU time 3502.99 seconds
Started Apr 23 12:25:06 PM PDT 24
Finished Apr 23 01:23:34 PM PDT 24
Peak memory 373236 kb
Host smart-31759261-80e4-475e-ab9f-abf82a61946d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019078029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 31.sram_ctrl_stress_all.3019078029
Directory /workspace/31.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.3082355558
Short name T22
Test name
Test status
Simulation time 24048187948 ps
CPU time 790.62 seconds
Started Apr 23 12:25:01 PM PDT 24
Finished Apr 23 12:38:13 PM PDT 24
Peak memory 375888 kb
Host smart-62586cea-cafe-4639-a48f-ca60a741b308
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3082355558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.3082355558
Directory /workspace/31.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_pipeline.224958787
Short name T574
Test name
Test status
Simulation time 4936953186 ps
CPU time 415.96 seconds
Started Apr 23 12:24:56 PM PDT 24
Finished Apr 23 12:31:53 PM PDT 24
Peak memory 201892 kb
Host smart-d2f3097a-09e7-46ed-ade7-030e4ac21389
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224958787 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.sram_ctrl_stress_pipeline.224958787
Directory /workspace/31.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.2585860721
Short name T589
Test name
Test status
Simulation time 115841032 ps
CPU time 50.12 seconds
Started Apr 23 12:25:05 PM PDT 24
Finished Apr 23 12:25:58 PM PDT 24
Peak memory 316380 kb
Host smart-622bffc5-032b-4e90-96b9-ceff79de90c0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585860721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.sram_ctrl_throughput_w_partial_write.2585860721
Directory /workspace/31.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/32.sram_ctrl_access_during_key_req.1130133787
Short name T927
Test name
Test status
Simulation time 18382180787 ps
CPU time 1210.35 seconds
Started Apr 23 12:24:59 PM PDT 24
Finished Apr 23 12:45:10 PM PDT 24
Peak memory 372620 kb
Host smart-223770e1-6fb2-4c6f-8ce0-76bfbf1887ea
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130133787 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.sram_ctrl_access_during_key_req.1130133787
Directory /workspace/32.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/32.sram_ctrl_alert_test.4035299660
Short name T472
Test name
Test status
Simulation time 14739644 ps
CPU time 0.7 seconds
Started Apr 23 12:25:12 PM PDT 24
Finished Apr 23 12:25:16 PM PDT 24
Peak memory 200876 kb
Host smart-771695a2-2c26-4a87-8b93-fdb9b9210792
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035299660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.sram_ctrl_alert_test.4035299660
Directory /workspace/32.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sram_ctrl_bijection.1709271042
Short name T862
Test name
Test status
Simulation time 2730177359 ps
CPU time 32.72 seconds
Started Apr 23 12:25:06 PM PDT 24
Finished Apr 23 12:25:43 PM PDT 24
Peak memory 201964 kb
Host smart-5a826010-ea8e-43f0-860a-0786f7756885
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709271042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection
.1709271042
Directory /workspace/32.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/32.sram_ctrl_executable.3828403
Short name T905
Test name
Test status
Simulation time 15557757769 ps
CPU time 940.66 seconds
Started Apr 23 12:24:55 PM PDT 24
Finished Apr 23 12:40:38 PM PDT 24
Peak memory 372760 kb
Host smart-888e64a5-74c9-42df-930f-a38469a31400
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executa
ble_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executable.3828403
Directory /workspace/32.sram_ctrl_executable/latest

Test location /workspace/coverage/default/32.sram_ctrl_lc_escalation.2294080046
Short name T307
Test name
Test status
Simulation time 276347889 ps
CPU time 1.3 seconds
Started Apr 23 12:24:53 PM PDT 24
Finished Apr 23 12:24:57 PM PDT 24
Peak memory 201928 kb
Host smart-32015843-145b-4a6c-a4f6-a3e555da47a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294080046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_es
calation.2294080046
Directory /workspace/32.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/32.sram_ctrl_max_throughput.1684036974
Short name T374
Test name
Test status
Simulation time 131394518 ps
CPU time 86.66 seconds
Started Apr 23 12:24:47 PM PDT 24
Finished Apr 23 12:26:15 PM PDT 24
Peak memory 345956 kb
Host smart-ea5d7da9-1ecf-431e-901e-1c75362dee70
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684036974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 32.sram_ctrl_max_throughput.1684036974
Directory /workspace/32.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_partial_access.3972695373
Short name T753
Test name
Test status
Simulation time 180642977 ps
CPU time 2.39 seconds
Started Apr 23 12:25:13 PM PDT 24
Finished Apr 23 12:25:19 PM PDT 24
Peak memory 210056 kb
Host smart-498316de-1d2b-4a87-9a21-85e1968bc4b4
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972695373 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.sram_ctrl_mem_partial_access.3972695373
Directory /workspace/32.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_walk.3856021220
Short name T430
Test name
Test status
Simulation time 571727808 ps
CPU time 8.79 seconds
Started Apr 23 12:25:05 PM PDT 24
Finished Apr 23 12:25:16 PM PDT 24
Peak memory 201780 kb
Host smart-b7c63ba6-a38a-4ee8-964f-c9716cb98c79
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856021220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctr
l_mem_walk.3856021220
Directory /workspace/32.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/32.sram_ctrl_multiple_keys.2136316220
Short name T356
Test name
Test status
Simulation time 21164327731 ps
CPU time 457.19 seconds
Started Apr 23 12:25:06 PM PDT 24
Finished Apr 23 12:32:47 PM PDT 24
Peak memory 368584 kb
Host smart-3e62e298-44ca-4738-ac29-a2490ed40f2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136316220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multi
ple_keys.2136316220
Directory /workspace/32.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access.1813613634
Short name T934
Test name
Test status
Simulation time 42682168 ps
CPU time 1.06 seconds
Started Apr 23 12:24:50 PM PDT 24
Finished Apr 23 12:24:53 PM PDT 24
Peak memory 201664 kb
Host smart-6c0c81c4-1534-4085-9172-7d977ed61d6b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813613634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
sram_ctrl_partial_access.1813613634
Directory /workspace/32.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.3199858313
Short name T758
Test name
Test status
Simulation time 3249539071 ps
CPU time 235.96 seconds
Started Apr 23 12:24:54 PM PDT 24
Finished Apr 23 12:28:52 PM PDT 24
Peak memory 202068 kb
Host smart-2fe6964a-5359-495d-89cb-bb82ca94f273
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199858313 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 32.sram_ctrl_partial_access_b2b.3199858313
Directory /workspace/32.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/32.sram_ctrl_ram_cfg.2992094492
Short name T369
Test name
Test status
Simulation time 44573441 ps
CPU time 0.74 seconds
Started Apr 23 12:24:49 PM PDT 24
Finished Apr 23 12:24:51 PM PDT 24
Peak memory 201972 kb
Host smart-bf9f68f1-8a46-4813-a886-8659475e7204
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992094492 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.2992094492
Directory /workspace/32.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/32.sram_ctrl_regwen.1460048513
Short name T567
Test name
Test status
Simulation time 5489404794 ps
CPU time 740.45 seconds
Started Apr 23 12:25:02 PM PDT 24
Finished Apr 23 12:37:24 PM PDT 24
Peak memory 373576 kb
Host smart-90f22e8e-37a9-46ed-90fc-3740c317fb41
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460048513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.1460048513
Directory /workspace/32.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/32.sram_ctrl_smoke.1357824238
Short name T812
Test name
Test status
Simulation time 369754680 ps
CPU time 87.85 seconds
Started Apr 23 12:25:00 PM PDT 24
Finished Apr 23 12:26:29 PM PDT 24
Peak memory 342076 kb
Host smart-61aa2e8e-2ec8-4dd7-9685-474b40a651e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357824238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.1357824238
Directory /workspace/32.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_all.22865454
Short name T816
Test name
Test status
Simulation time 161418602894 ps
CPU time 5159.13 seconds
Started Apr 23 12:25:07 PM PDT 24
Finished Apr 23 01:51:12 PM PDT 24
Peak memory 381836 kb
Host smart-3c132600-44e7-4284-bd4e-96d43826a514
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22865454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +
UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.sram_ctrl_stress_all.22865454
Directory /workspace/32.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.1226066377
Short name T738
Test name
Test status
Simulation time 611048553 ps
CPU time 77.9 seconds
Started Apr 23 12:24:57 PM PDT 24
Finished Apr 23 12:26:16 PM PDT 24
Peak memory 315416 kb
Host smart-50f264b0-3a20-494f-af3c-2e13958d8269
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1226066377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.1226066377
Directory /workspace/32.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_pipeline.1036778148
Short name T405
Test name
Test status
Simulation time 4263727428 ps
CPU time 102.24 seconds
Started Apr 23 12:24:55 PM PDT 24
Finished Apr 23 12:26:39 PM PDT 24
Peak memory 201944 kb
Host smart-07b665e5-6f5e-4956-bc57-8f4bf5807e9a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036778148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.sram_ctrl_stress_pipeline.1036778148
Directory /workspace/32.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.1993357683
Short name T904
Test name
Test status
Simulation time 154353229 ps
CPU time 9.52 seconds
Started Apr 23 12:24:48 PM PDT 24
Finished Apr 23 12:24:58 PM PDT 24
Peak memory 250992 kb
Host smart-9749db1d-d85c-4656-b5c6-abf7c0aefa43
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993357683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.sram_ctrl_throughput_w_partial_write.1993357683
Directory /workspace/32.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/33.sram_ctrl_access_during_key_req.59786111
Short name T175
Test name
Test status
Simulation time 12183735193 ps
CPU time 1650.15 seconds
Started Apr 23 12:24:48 PM PDT 24
Finished Apr 23 12:52:19 PM PDT 24
Peak memory 372780 kb
Host smart-fbb73ef3-0d4b-4138-af8e-efac904f0211
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59786111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.sram_ctrl_access_during_key_req.59786111
Directory /workspace/33.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/33.sram_ctrl_alert_test.2758180936
Short name T525
Test name
Test status
Simulation time 28242900 ps
CPU time 0.63 seconds
Started Apr 23 12:25:17 PM PDT 24
Finished Apr 23 12:25:20 PM PDT 24
Peak memory 201692 kb
Host smart-1f5568fc-1031-4ea4-9fab-53d71ce4571b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758180936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.sram_ctrl_alert_test.2758180936
Directory /workspace/33.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sram_ctrl_bijection.601022983
Short name T699
Test name
Test status
Simulation time 3265397164 ps
CPU time 56.86 seconds
Started Apr 23 12:25:15 PM PDT 24
Finished Apr 23 12:26:15 PM PDT 24
Peak memory 201968 kb
Host smart-c94a765f-b590-4c32-9379-ad6fa5c55b7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601022983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection.
601022983
Directory /workspace/33.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/33.sram_ctrl_executable.1817101584
Short name T723
Test name
Test status
Simulation time 3720961734 ps
CPU time 726.23 seconds
Started Apr 23 12:25:06 PM PDT 24
Finished Apr 23 12:37:14 PM PDT 24
Peak memory 373180 kb
Host smart-3dd7208b-90a1-462c-b46d-8eea767bc4f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817101584 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executab
le.1817101584
Directory /workspace/33.sram_ctrl_executable/latest

Test location /workspace/coverage/default/33.sram_ctrl_lc_escalation.555705893
Short name T799
Test name
Test status
Simulation time 1007398371 ps
CPU time 5.36 seconds
Started Apr 23 12:25:06 PM PDT 24
Finished Apr 23 12:25:14 PM PDT 24
Peak memory 201948 kb
Host smart-cff211cd-8f85-4e23-88f1-28e2e4e8d6d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555705893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_esc
alation.555705893
Directory /workspace/33.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/33.sram_ctrl_max_throughput.1187722486
Short name T317
Test name
Test status
Simulation time 88684105 ps
CPU time 27.11 seconds
Started Apr 23 12:25:08 PM PDT 24
Finished Apr 23 12:25:40 PM PDT 24
Peak memory 283512 kb
Host smart-eba428b7-10be-467b-b8ec-a23bfdd1dad1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187722486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.sram_ctrl_max_throughput.1187722486
Directory /workspace/33.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_partial_access.3549512388
Short name T437
Test name
Test status
Simulation time 128576715 ps
CPU time 4.55 seconds
Started Apr 23 12:25:09 PM PDT 24
Finished Apr 23 12:25:18 PM PDT 24
Peak memory 210016 kb
Host smart-e41d8663-63e3-48bb-a891-3d5273566f3e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549512388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.sram_ctrl_mem_partial_access.3549512388
Directory /workspace/33.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_walk.1860483509
Short name T260
Test name
Test status
Simulation time 224934550 ps
CPU time 4.71 seconds
Started Apr 23 12:25:07 PM PDT 24
Finished Apr 23 12:25:17 PM PDT 24
Peak memory 201568 kb
Host smart-90ee1c62-ddd5-4735-8a51-551b8b25c1e1
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860483509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctr
l_mem_walk.1860483509
Directory /workspace/33.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/33.sram_ctrl_multiple_keys.1329496386
Short name T151
Test name
Test status
Simulation time 64434885825 ps
CPU time 1194.79 seconds
Started Apr 23 12:25:07 PM PDT 24
Finished Apr 23 12:45:07 PM PDT 24
Peak memory 374608 kb
Host smart-e758613e-dffe-4c16-9687-184b5e4bfe14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329496386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multi
ple_keys.1329496386
Directory /workspace/33.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access.2073199933
Short name T153
Test name
Test status
Simulation time 203697530 ps
CPU time 117.82 seconds
Started Apr 23 12:25:05 PM PDT 24
Finished Apr 23 12:27:04 PM PDT 24
Peak memory 359928 kb
Host smart-58e760cd-185c-492f-b7ec-49b5e6c66ea7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073199933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
sram_ctrl_partial_access.2073199933
Directory /workspace/33.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.1627798434
Short name T92
Test name
Test status
Simulation time 12065303639 ps
CPU time 282.22 seconds
Started Apr 23 12:24:57 PM PDT 24
Finished Apr 23 12:29:40 PM PDT 24
Peak memory 201924 kb
Host smart-15710bba-446c-4aae-9396-a36b0e7d1b5c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627798434 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 33.sram_ctrl_partial_access_b2b.1627798434
Directory /workspace/33.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/33.sram_ctrl_ram_cfg.576549008
Short name T305
Test name
Test status
Simulation time 88348590 ps
CPU time 0.73 seconds
Started Apr 23 12:25:03 PM PDT 24
Finished Apr 23 12:25:05 PM PDT 24
Peak memory 201972 kb
Host smart-d7f4563e-24d6-4d5a-8d2a-19c54daca39b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576549008 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.576549008
Directory /workspace/33.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/33.sram_ctrl_regwen.2152135799
Short name T226
Test name
Test status
Simulation time 54290315743 ps
CPU time 452.22 seconds
Started Apr 23 12:25:05 PM PDT 24
Finished Apr 23 12:32:40 PM PDT 24
Peak memory 363912 kb
Host smart-7a1ae469-4a7f-4d85-8fb6-c4725ff65d11
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152135799 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.2152135799
Directory /workspace/33.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/33.sram_ctrl_smoke.2836232558
Short name T899
Test name
Test status
Simulation time 453323905 ps
CPU time 6.81 seconds
Started Apr 23 12:25:08 PM PDT 24
Finished Apr 23 12:25:20 PM PDT 24
Peak memory 201904 kb
Host smart-3a5301c8-21ca-4be5-84fd-287ca05de9dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836232558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.2836232558
Directory /workspace/33.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_all.1577190661
Short name T884
Test name
Test status
Simulation time 34910686388 ps
CPU time 2180.74 seconds
Started Apr 23 12:25:03 PM PDT 24
Finished Apr 23 01:01:25 PM PDT 24
Peak memory 374708 kb
Host smart-5ebd7988-2918-4ecb-b4f1-757eafb73c97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577190661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 33.sram_ctrl_stress_all.1577190661
Directory /workspace/33.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_pipeline.4216208186
Short name T445
Test name
Test status
Simulation time 2276734873 ps
CPU time 195.42 seconds
Started Apr 23 12:25:05 PM PDT 24
Finished Apr 23 12:28:21 PM PDT 24
Peak memory 201880 kb
Host smart-9f6ab235-bfc5-4b45-8163-12d4e3284c53
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216208186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.sram_ctrl_stress_pipeline.4216208186
Directory /workspace/33.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.2620805374
Short name T149
Test name
Test status
Simulation time 156339226 ps
CPU time 124.01 seconds
Started Apr 23 12:25:13 PM PDT 24
Finished Apr 23 12:27:21 PM PDT 24
Peak memory 361444 kb
Host smart-a8c69d80-92db-412c-b731-bf33cae8b526
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620805374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.sram_ctrl_throughput_w_partial_write.2620805374
Directory /workspace/33.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/34.sram_ctrl_access_during_key_req.2358670154
Short name T471
Test name
Test status
Simulation time 3908164018 ps
CPU time 1344.54 seconds
Started Apr 23 12:25:12 PM PDT 24
Finished Apr 23 12:47:40 PM PDT 24
Peak memory 373704 kb
Host smart-85104df5-752b-4805-b62b-064d3edcee7b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358670154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.sram_ctrl_access_during_key_req.2358670154
Directory /workspace/34.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/34.sram_ctrl_alert_test.2305253950
Short name T18
Test name
Test status
Simulation time 68700696 ps
CPU time 0.66 seconds
Started Apr 23 12:25:08 PM PDT 24
Finished Apr 23 12:25:14 PM PDT 24
Peak memory 200920 kb
Host smart-11d2c1d3-5faa-4759-9c82-e737f5f6f277
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305253950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.sram_ctrl_alert_test.2305253950
Directory /workspace/34.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sram_ctrl_bijection.958032526
Short name T881
Test name
Test status
Simulation time 3644017959 ps
CPU time 25.95 seconds
Started Apr 23 12:25:03 PM PDT 24
Finished Apr 23 12:25:30 PM PDT 24
Peak memory 201936 kb
Host smart-3c644f29-af98-45dc-a27c-1ce1518ba6c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958032526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection.
958032526
Directory /workspace/34.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/34.sram_ctrl_executable.3491736054
Short name T294
Test name
Test status
Simulation time 22608420848 ps
CPU time 1184.49 seconds
Started Apr 23 12:25:07 PM PDT 24
Finished Apr 23 12:44:56 PM PDT 24
Peak memory 370660 kb
Host smart-e52a7292-6515-419d-a91e-ebf5f020b1b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491736054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executab
le.3491736054
Directory /workspace/34.sram_ctrl_executable/latest

Test location /workspace/coverage/default/34.sram_ctrl_lc_escalation.134307496
Short name T937
Test name
Test status
Simulation time 1172390860 ps
CPU time 4.65 seconds
Started Apr 23 12:25:08 PM PDT 24
Finished Apr 23 12:25:17 PM PDT 24
Peak memory 201840 kb
Host smart-c9579a4c-879a-4232-812f-97c42477a579
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134307496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_esc
alation.134307496
Directory /workspace/34.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/34.sram_ctrl_max_throughput.1215289823
Short name T257
Test name
Test status
Simulation time 83694929 ps
CPU time 1.81 seconds
Started Apr 23 12:25:13 PM PDT 24
Finished Apr 23 12:25:18 PM PDT 24
Peak memory 210120 kb
Host smart-647fc41a-1f00-4eaa-8e8f-2c2a106021a4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215289823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 34.sram_ctrl_max_throughput.1215289823
Directory /workspace/34.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_partial_access.902196463
Short name T265
Test name
Test status
Simulation time 101086583 ps
CPU time 2.82 seconds
Started Apr 23 12:25:19 PM PDT 24
Finished Apr 23 12:25:24 PM PDT 24
Peak memory 209996 kb
Host smart-df831cd1-feb5-4f80-ab80-5867893ffdd2
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902196463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.sram_ctrl_mem_partial_access.902196463
Directory /workspace/34.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_walk.1890272971
Short name T837
Test name
Test status
Simulation time 132192400 ps
CPU time 4.25 seconds
Started Apr 23 12:25:06 PM PDT 24
Finished Apr 23 12:25:14 PM PDT 24
Peak memory 201780 kb
Host smart-df695c51-6816-42c8-90c8-ed49563e209e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890272971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctr
l_mem_walk.1890272971
Directory /workspace/34.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/34.sram_ctrl_multiple_keys.1008279910
Short name T811
Test name
Test status
Simulation time 22613282427 ps
CPU time 2145.07 seconds
Started Apr 23 12:24:56 PM PDT 24
Finished Apr 23 01:00:42 PM PDT 24
Peak memory 374724 kb
Host smart-06ddc930-6732-4933-9f8e-609cef49b9d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008279910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multi
ple_keys.1008279910
Directory /workspace/34.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access.1615574871
Short name T373
Test name
Test status
Simulation time 1779043487 ps
CPU time 63.88 seconds
Started Apr 23 12:25:03 PM PDT 24
Finished Apr 23 12:26:07 PM PDT 24
Peak memory 322528 kb
Host smart-43f88091-4afb-4d84-8c7b-f95777a08c12
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615574871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
sram_ctrl_partial_access.1615574871
Directory /workspace/34.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.3042345674
Short name T737
Test name
Test status
Simulation time 17477504281 ps
CPU time 440.16 seconds
Started Apr 23 12:24:45 PM PDT 24
Finished Apr 23 12:32:06 PM PDT 24
Peak memory 201888 kb
Host smart-80b1fbbd-ff1d-4e76-8da8-e99c084c04f8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042345674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 34.sram_ctrl_partial_access_b2b.3042345674
Directory /workspace/34.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/34.sram_ctrl_ram_cfg.3269795261
Short name T269
Test name
Test status
Simulation time 150724889 ps
CPU time 0.72 seconds
Started Apr 23 12:25:09 PM PDT 24
Finished Apr 23 12:25:15 PM PDT 24
Peak memory 201988 kb
Host smart-4a9f978c-f835-4c49-b3bf-2a59333831fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269795261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.3269795261
Directory /workspace/34.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/34.sram_ctrl_regwen.117533703
Short name T259
Test name
Test status
Simulation time 48973892032 ps
CPU time 344.1 seconds
Started Apr 23 12:25:12 PM PDT 24
Finished Apr 23 12:31:00 PM PDT 24
Peak memory 332760 kb
Host smart-2513299f-1d49-4aec-aff8-b6a4de3219f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117533703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.117533703
Directory /workspace/34.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/34.sram_ctrl_smoke.218754949
Short name T160
Test name
Test status
Simulation time 2611033558 ps
CPU time 10.56 seconds
Started Apr 23 12:25:08 PM PDT 24
Finished Apr 23 12:25:24 PM PDT 24
Peak memory 201948 kb
Host smart-64e5f5b0-0dd4-4414-853b-aa3de1fd96ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218754949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.218754949
Directory /workspace/34.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_all.1132704382
Short name T492
Test name
Test status
Simulation time 84419254454 ps
CPU time 6513.57 seconds
Started Apr 23 12:25:14 PM PDT 24
Finished Apr 23 02:13:52 PM PDT 24
Peak memory 374772 kb
Host smart-da8d7f62-3a54-4f2d-a4b3-ca75de19a94b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132704382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 34.sram_ctrl_stress_all.1132704382
Directory /workspace/34.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3385154650
Short name T932
Test name
Test status
Simulation time 3200779585 ps
CPU time 1085.33 seconds
Started Apr 23 12:25:04 PM PDT 24
Finished Apr 23 12:43:10 PM PDT 24
Peak memory 372828 kb
Host smart-b09aede8-cdce-45cf-8d7e-8e84bf5cd2d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3385154650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.3385154650
Directory /workspace/34.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_pipeline.1266855387
Short name T447
Test name
Test status
Simulation time 33741133866 ps
CPU time 284.17 seconds
Started Apr 23 12:25:08 PM PDT 24
Finished Apr 23 12:29:57 PM PDT 24
Peak memory 201892 kb
Host smart-9ab95a9d-dae9-468f-ab17-19c4aa019e8a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266855387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.sram_ctrl_stress_pipeline.1266855387
Directory /workspace/34.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.2834409536
Short name T621
Test name
Test status
Simulation time 912133822 ps
CPU time 49.42 seconds
Started Apr 23 12:25:11 PM PDT 24
Finished Apr 23 12:26:05 PM PDT 24
Peak memory 307780 kb
Host smart-5e42aebe-a4d1-432a-a6df-4b59f91a004d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834409536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.2834409536
Directory /workspace/34.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/35.sram_ctrl_access_during_key_req.2303407442
Short name T682
Test name
Test status
Simulation time 6371568410 ps
CPU time 521.04 seconds
Started Apr 23 12:25:03 PM PDT 24
Finished Apr 23 12:33:46 PM PDT 24
Peak memory 350356 kb
Host smart-6b1f0bd9-a3b1-4925-be63-015998546ed8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303407442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.sram_ctrl_access_during_key_req.2303407442
Directory /workspace/35.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/35.sram_ctrl_alert_test.2312185119
Short name T407
Test name
Test status
Simulation time 18630800 ps
CPU time 0.64 seconds
Started Apr 23 12:25:16 PM PDT 24
Finished Apr 23 12:25:20 PM PDT 24
Peak memory 201616 kb
Host smart-afd38a41-faea-4eb4-88f0-e12571e90ac8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312185119 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.sram_ctrl_alert_test.2312185119
Directory /workspace/35.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sram_ctrl_bijection.1127979858
Short name T586
Test name
Test status
Simulation time 2653888030 ps
CPU time 47.58 seconds
Started Apr 23 12:25:00 PM PDT 24
Finished Apr 23 12:25:48 PM PDT 24
Peak memory 201916 kb
Host smart-8676ff55-ea5c-43d6-af23-4395233a8cf3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127979858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection
.1127979858
Directory /workspace/35.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/35.sram_ctrl_executable.2162770609
Short name T273
Test name
Test status
Simulation time 60522722306 ps
CPU time 535.42 seconds
Started Apr 23 12:25:00 PM PDT 24
Finished Apr 23 12:33:56 PM PDT 24
Peak memory 362840 kb
Host smart-4a6bb6e4-e875-4eed-9b93-2530bbf71e96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162770609 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executab
le.2162770609
Directory /workspace/35.sram_ctrl_executable/latest

Test location /workspace/coverage/default/35.sram_ctrl_lc_escalation.3980636708
Short name T872
Test name
Test status
Simulation time 135963826 ps
CPU time 1.34 seconds
Started Apr 23 12:25:12 PM PDT 24
Finished Apr 23 12:25:17 PM PDT 24
Peak memory 201924 kb
Host smart-7ecac4db-0bc8-411e-b288-6dfcb8cae06b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980636708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_es
calation.3980636708
Directory /workspace/35.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/35.sram_ctrl_max_throughput.2528675283
Short name T562
Test name
Test status
Simulation time 49719318 ps
CPU time 3.13 seconds
Started Apr 23 12:25:15 PM PDT 24
Finished Apr 23 12:25:21 PM PDT 24
Peak memory 218244 kb
Host smart-124ff94f-742a-4711-89ef-c68a126ad59f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528675283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 35.sram_ctrl_max_throughput.2528675283
Directory /workspace/35.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_partial_access.2576704146
Short name T173
Test name
Test status
Simulation time 347376405 ps
CPU time 2.97 seconds
Started Apr 23 12:25:02 PM PDT 24
Finished Apr 23 12:25:06 PM PDT 24
Peak memory 210052 kb
Host smart-6567856c-9969-4f7a-a3d3-e0e749d10773
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576704146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.sram_ctrl_mem_partial_access.2576704146
Directory /workspace/35.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_walk.208824927
Short name T782
Test name
Test status
Simulation time 141761317 ps
CPU time 7.9 seconds
Started Apr 23 12:25:19 PM PDT 24
Finished Apr 23 12:25:29 PM PDT 24
Peak memory 201760 kb
Host smart-565785a1-ffde-412b-a0c7-3a812ebfcd79
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208824927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl
_mem_walk.208824927
Directory /workspace/35.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/35.sram_ctrl_multiple_keys.2696124662
Short name T30
Test name
Test status
Simulation time 4755805070 ps
CPU time 493.43 seconds
Started Apr 23 12:25:14 PM PDT 24
Finished Apr 23 12:33:30 PM PDT 24
Peak memory 371652 kb
Host smart-3ccbfda4-c9f1-4251-81b0-6885abad747c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696124662 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multi
ple_keys.2696124662
Directory /workspace/35.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access.3237644885
Short name T247
Test name
Test status
Simulation time 2246836951 ps
CPU time 21.58 seconds
Started Apr 23 12:24:56 PM PDT 24
Finished Apr 23 12:25:19 PM PDT 24
Peak memory 273276 kb
Host smart-8fe216cf-8354-43e1-9465-5f0016093645
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237644885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
sram_ctrl_partial_access.3237644885
Directory /workspace/35.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.540857010
Short name T554
Test name
Test status
Simulation time 16230840426 ps
CPU time 285.58 seconds
Started Apr 23 12:25:15 PM PDT 24
Finished Apr 23 12:30:04 PM PDT 24
Peak memory 202008 kb
Host smart-abe46883-3fcb-490d-bf22-2f7d5aa82378
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540857010 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.sram_ctrl_partial_access_b2b.540857010
Directory /workspace/35.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/35.sram_ctrl_ram_cfg.2273279459
Short name T166
Test name
Test status
Simulation time 28856658 ps
CPU time 0.79 seconds
Started Apr 23 12:25:11 PM PDT 24
Finished Apr 23 12:25:16 PM PDT 24
Peak memory 202052 kb
Host smart-41400de3-c4b0-4fcf-8c20-49298d234c60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273279459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.2273279459
Directory /workspace/35.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/35.sram_ctrl_regwen.274379285
Short name T51
Test name
Test status
Simulation time 50940940185 ps
CPU time 1056 seconds
Started Apr 23 12:25:07 PM PDT 24
Finished Apr 23 12:42:47 PM PDT 24
Peak memory 373552 kb
Host smart-e63db283-282e-4703-907c-28f2ad3209a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274379285 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.274379285
Directory /workspace/35.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/35.sram_ctrl_smoke.419484764
Short name T788
Test name
Test status
Simulation time 329266908 ps
CPU time 26.43 seconds
Started Apr 23 12:25:02 PM PDT 24
Finished Apr 23 12:25:29 PM PDT 24
Peak memory 274320 kb
Host smart-06848a73-9fd4-4f10-b978-d7f3bee01ede
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419484764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.419484764
Directory /workspace/35.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_all.2518455957
Short name T866
Test name
Test status
Simulation time 5488986335 ps
CPU time 1758.73 seconds
Started Apr 23 12:25:11 PM PDT 24
Finished Apr 23 12:54:34 PM PDT 24
Peak memory 374024 kb
Host smart-6f85fc69-6c28-4283-a51a-40dc97e5f471
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518455957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 35.sram_ctrl_stress_all.2518455957
Directory /workspace/35.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.2119533410
Short name T103
Test name
Test status
Simulation time 3149042004 ps
CPU time 21.44 seconds
Started Apr 23 12:25:11 PM PDT 24
Finished Apr 23 12:25:37 PM PDT 24
Peak memory 210252 kb
Host smart-3944ad68-7c43-41a9-b137-1ca3d5bf21a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2119533410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.2119533410
Directory /workspace/35.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_pipeline.2417650785
Short name T1
Test name
Test status
Simulation time 7344644008 ps
CPU time 158.64 seconds
Started Apr 23 12:25:07 PM PDT 24
Finished Apr 23 12:27:50 PM PDT 24
Peak memory 201908 kb
Host smart-3945b8c8-a350-4d26-b0c5-8331cf0eddb7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417650785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.sram_ctrl_stress_pipeline.2417650785
Directory /workspace/35.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.587650366
Short name T475
Test name
Test status
Simulation time 548159655 ps
CPU time 48.78 seconds
Started Apr 23 12:25:03 PM PDT 24
Finished Apr 23 12:25:53 PM PDT 24
Peak memory 311920 kb
Host smart-8dd868d5-b6d0-4b08-8e04-64ce7bc7631f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587650366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 35.sram_ctrl_throughput_w_partial_write.587650366
Directory /workspace/35.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/36.sram_ctrl_access_during_key_req.1368170903
Short name T750
Test name
Test status
Simulation time 11557804808 ps
CPU time 432.49 seconds
Started Apr 23 12:25:23 PM PDT 24
Finished Apr 23 12:32:37 PM PDT 24
Peak memory 373588 kb
Host smart-68f494fe-ffcc-4740-9e95-6631ab2f2613
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368170903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.sram_ctrl_access_during_key_req.1368170903
Directory /workspace/36.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/36.sram_ctrl_alert_test.3023006415
Short name T703
Test name
Test status
Simulation time 12647274 ps
CPU time 0.64 seconds
Started Apr 23 12:25:13 PM PDT 24
Finished Apr 23 12:25:17 PM PDT 24
Peak memory 201468 kb
Host smart-c03fa993-60e0-49f9-95c1-2ee720950f11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023006415 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.sram_ctrl_alert_test.3023006415
Directory /workspace/36.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sram_ctrl_bijection.164723342
Short name T230
Test name
Test status
Simulation time 13377279436 ps
CPU time 60.35 seconds
Started Apr 23 12:25:05 PM PDT 24
Finished Apr 23 12:26:07 PM PDT 24
Peak memory 201964 kb
Host smart-5fc8c8be-7fd2-48b9-a07c-d26b1ec392f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164723342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection.
164723342
Directory /workspace/36.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/36.sram_ctrl_executable.2285567057
Short name T341
Test name
Test status
Simulation time 5997963721 ps
CPU time 403.09 seconds
Started Apr 23 12:24:56 PM PDT 24
Finished Apr 23 12:31:41 PM PDT 24
Peak memory 367608 kb
Host smart-d80bfc78-57c1-4e7d-bda0-e74ed7f4cd65
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285567057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executab
le.2285567057
Directory /workspace/36.sram_ctrl_executable/latest

Test location /workspace/coverage/default/36.sram_ctrl_lc_escalation.2704358788
Short name T4
Test name
Test status
Simulation time 1955912274 ps
CPU time 3.79 seconds
Started Apr 23 12:25:12 PM PDT 24
Finished Apr 23 12:25:20 PM PDT 24
Peak memory 201928 kb
Host smart-8a7681ce-436a-443d-a150-51a497fdcb7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704358788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_es
calation.2704358788
Directory /workspace/36.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/36.sram_ctrl_max_throughput.3978890778
Short name T285
Test name
Test status
Simulation time 375869844 ps
CPU time 33.77 seconds
Started Apr 23 12:25:14 PM PDT 24
Finished Apr 23 12:25:50 PM PDT 24
Peak memory 299080 kb
Host smart-73cdc494-1a56-4d2c-a209-bb11ead4e9eb
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978890778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.sram_ctrl_max_throughput.3978890778
Directory /workspace/36.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_partial_access.3057793527
Short name T392
Test name
Test status
Simulation time 604635349 ps
CPU time 5.08 seconds
Started Apr 23 12:25:09 PM PDT 24
Finished Apr 23 12:25:19 PM PDT 24
Peak memory 210048 kb
Host smart-312bfe38-5436-48b6-8843-75aac41ecc5e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057793527 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.sram_ctrl_mem_partial_access.3057793527
Directory /workspace/36.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_walk.1812906252
Short name T204
Test name
Test status
Simulation time 599661358 ps
CPU time 9.69 seconds
Started Apr 23 12:25:10 PM PDT 24
Finished Apr 23 12:25:24 PM PDT 24
Peak memory 201804 kb
Host smart-84329cf8-854c-41d9-96e8-67ba6c073757
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812906252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctr
l_mem_walk.1812906252
Directory /workspace/36.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/36.sram_ctrl_multiple_keys.1370856216
Short name T391
Test name
Test status
Simulation time 3097097327 ps
CPU time 738.62 seconds
Started Apr 23 12:25:03 PM PDT 24
Finished Apr 23 12:37:23 PM PDT 24
Peak memory 368852 kb
Host smart-e423139b-3f9e-492c-bab0-76c088f3660c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370856216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multi
ple_keys.1370856216
Directory /workspace/36.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access.3753579780
Short name T455
Test name
Test status
Simulation time 356273660 ps
CPU time 79.67 seconds
Started Apr 23 12:25:09 PM PDT 24
Finished Apr 23 12:26:34 PM PDT 24
Peak memory 334576 kb
Host smart-4ee4ea09-6c48-4fca-a74e-34cdbbd32609
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753579780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
sram_ctrl_partial_access.3753579780
Directory /workspace/36.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.4037426222
Short name T669
Test name
Test status
Simulation time 6805313703 ps
CPU time 234.72 seconds
Started Apr 23 12:25:08 PM PDT 24
Finished Apr 23 12:29:09 PM PDT 24
Peak memory 201988 kb
Host smart-d101c47f-2df8-4b69-8135-98c4959276d5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037426222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 36.sram_ctrl_partial_access_b2b.4037426222
Directory /workspace/36.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/36.sram_ctrl_ram_cfg.1227113126
Short name T871
Test name
Test status
Simulation time 232956642 ps
CPU time 0.82 seconds
Started Apr 23 12:25:03 PM PDT 24
Finished Apr 23 12:25:05 PM PDT 24
Peak memory 201920 kb
Host smart-25cf3bf6-2e55-48d2-af2a-80bb59002e90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227113126 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.1227113126
Directory /workspace/36.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/36.sram_ctrl_regwen.1249932914
Short name T483
Test name
Test status
Simulation time 865947272 ps
CPU time 16.99 seconds
Started Apr 23 12:25:03 PM PDT 24
Finished Apr 23 12:25:21 PM PDT 24
Peak memory 202044 kb
Host smart-2c56f8fb-c942-4e9f-a11f-9ae712fb9ca7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249932914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.1249932914
Directory /workspace/36.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/36.sram_ctrl_smoke.176065084
Short name T438
Test name
Test status
Simulation time 228924987 ps
CPU time 6.41 seconds
Started Apr 23 12:25:15 PM PDT 24
Finished Apr 23 12:25:24 PM PDT 24
Peak memory 201860 kb
Host smart-79db8b9a-41ac-4ec6-98be-380552530ee8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176065084 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.176065084
Directory /workspace/36.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_all.1225296758
Short name T465
Test name
Test status
Simulation time 143489220305 ps
CPU time 2503.1 seconds
Started Apr 23 12:25:07 PM PDT 24
Finished Apr 23 01:06:56 PM PDT 24
Peak memory 375440 kb
Host smart-51f047b1-780c-4622-a7cb-49487338a413
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225296758 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 36.sram_ctrl_stress_all.1225296758
Directory /workspace/36.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.1589853065
Short name T624
Test name
Test status
Simulation time 3173783385 ps
CPU time 164 seconds
Started Apr 23 12:25:03 PM PDT 24
Finished Apr 23 12:27:49 PM PDT 24
Peak memory 360012 kb
Host smart-6d5bc19f-233d-4c0d-9506-0303aa6d91a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1589853065 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.1589853065
Directory /workspace/36.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_pipeline.1365345708
Short name T793
Test name
Test status
Simulation time 3119369719 ps
CPU time 279.59 seconds
Started Apr 23 12:25:12 PM PDT 24
Finished Apr 23 12:29:55 PM PDT 24
Peak memory 201880 kb
Host smart-f8b1933c-dae5-4cbc-a2d2-e4e9fbdd2af3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365345708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.sram_ctrl_stress_pipeline.1365345708
Directory /workspace/36.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.828738073
Short name T150
Test name
Test status
Simulation time 168184727 ps
CPU time 19.02 seconds
Started Apr 23 12:25:09 PM PDT 24
Finished Apr 23 12:25:33 PM PDT 24
Peak memory 273480 kb
Host smart-cafaf5eb-1203-45b2-9d90-5998b140eb5e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828738073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.sram_ctrl_throughput_w_partial_write.828738073
Directory /workspace/36.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/37.sram_ctrl_access_during_key_req.2521787112
Short name T376
Test name
Test status
Simulation time 3909814373 ps
CPU time 1023.81 seconds
Started Apr 23 12:25:09 PM PDT 24
Finished Apr 23 12:42:18 PM PDT 24
Peak memory 373696 kb
Host smart-dd171816-3ed7-4f3c-86e4-6d14d5f408fc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521787112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.sram_ctrl_access_during_key_req.2521787112
Directory /workspace/37.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/37.sram_ctrl_alert_test.1544553722
Short name T20
Test name
Test status
Simulation time 50367324 ps
CPU time 0.65 seconds
Started Apr 23 12:25:07 PM PDT 24
Finished Apr 23 12:25:13 PM PDT 24
Peak memory 201084 kb
Host smart-b28ca0b2-2b39-4927-8a35-38d3897d4639
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544553722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.sram_ctrl_alert_test.1544553722
Directory /workspace/37.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sram_ctrl_bijection.1149739154
Short name T947
Test name
Test status
Simulation time 3645447661 ps
CPU time 79.49 seconds
Started Apr 23 12:25:07 PM PDT 24
Finished Apr 23 12:26:31 PM PDT 24
Peak memory 201980 kb
Host smart-ee28953b-5d52-45a6-b885-20d02c69fb8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149739154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection
.1149739154
Directory /workspace/37.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/37.sram_ctrl_executable.3950476679
Short name T655
Test name
Test status
Simulation time 4383962148 ps
CPU time 828.18 seconds
Started Apr 23 12:25:17 PM PDT 24
Finished Apr 23 12:39:08 PM PDT 24
Peak memory 371656 kb
Host smart-71a14ebc-a4cc-466a-a801-72afad1099eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950476679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executab
le.3950476679
Directory /workspace/37.sram_ctrl_executable/latest

Test location /workspace/coverage/default/37.sram_ctrl_lc_escalation.395923605
Short name T726
Test name
Test status
Simulation time 2607202977 ps
CPU time 7.08 seconds
Started Apr 23 12:25:08 PM PDT 24
Finished Apr 23 12:25:20 PM PDT 24
Peak memory 202068 kb
Host smart-75f7123b-7035-46de-9cc6-882843829ff0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395923605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_esc
alation.395923605
Directory /workspace/37.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/37.sram_ctrl_max_throughput.3861026748
Short name T385
Test name
Test status
Simulation time 65602721 ps
CPU time 7.81 seconds
Started Apr 23 12:25:15 PM PDT 24
Finished Apr 23 12:25:25 PM PDT 24
Peak memory 243636 kb
Host smart-ebccde37-07c8-4934-b837-2278b4a4ef7e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861026748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.sram_ctrl_max_throughput.3861026748
Directory /workspace/37.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_partial_access.860476328
Short name T529
Test name
Test status
Simulation time 292250899 ps
CPU time 4.98 seconds
Started Apr 23 12:25:04 PM PDT 24
Finished Apr 23 12:25:10 PM PDT 24
Peak memory 210040 kb
Host smart-08d4c253-8c6b-4242-9d78-cdbe7b8b035d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860476328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.sram_ctrl_mem_partial_access.860476328
Directory /workspace/37.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_walk.788370679
Short name T610
Test name
Test status
Simulation time 267189251 ps
CPU time 8.02 seconds
Started Apr 23 12:25:06 PM PDT 24
Finished Apr 23 12:25:19 PM PDT 24
Peak memory 201784 kb
Host smart-cbcefe66-379d-42de-a5bf-4c046aaf5b62
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788370679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl
_mem_walk.788370679
Directory /workspace/37.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/37.sram_ctrl_multiple_keys.3890126036
Short name T14
Test name
Test status
Simulation time 63420647319 ps
CPU time 716.16 seconds
Started Apr 23 12:25:19 PM PDT 24
Finished Apr 23 12:37:17 PM PDT 24
Peak memory 360520 kb
Host smart-95b2e312-6b8a-48b3-80c8-6d4ecbb2abcf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890126036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multi
ple_keys.3890126036
Directory /workspace/37.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access.276675670
Short name T280
Test name
Test status
Simulation time 1289423112 ps
CPU time 12.22 seconds
Started Apr 23 12:25:38 PM PDT 24
Finished Apr 23 12:25:52 PM PDT 24
Peak memory 201804 kb
Host smart-ddc172d0-3021-47f0-9291-22e4da15fac8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276675670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.s
ram_ctrl_partial_access.276675670
Directory /workspace/37.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.2266952656
Short name T90
Test name
Test status
Simulation time 21267955035 ps
CPU time 219.4 seconds
Started Apr 23 12:25:07 PM PDT 24
Finished Apr 23 12:28:51 PM PDT 24
Peak memory 201908 kb
Host smart-45a0ff00-0824-4525-a350-1c90579595fc
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266952656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 37.sram_ctrl_partial_access_b2b.2266952656
Directory /workspace/37.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/37.sram_ctrl_ram_cfg.284200292
Short name T935
Test name
Test status
Simulation time 36818539 ps
CPU time 0.75 seconds
Started Apr 23 12:25:06 PM PDT 24
Finished Apr 23 12:25:11 PM PDT 24
Peak memory 201940 kb
Host smart-51596dd5-f5cb-43b8-9494-b4674f06a7d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284200292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.284200292
Directory /workspace/37.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/37.sram_ctrl_regwen.4218231184
Short name T184
Test name
Test status
Simulation time 11894461330 ps
CPU time 1611.67 seconds
Started Apr 23 12:25:14 PM PDT 24
Finished Apr 23 12:52:09 PM PDT 24
Peak memory 374000 kb
Host smart-456fa1b3-c252-4ef4-8522-617d2439e6ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218231184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.4218231184
Directory /workspace/37.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/37.sram_ctrl_smoke.2243639247
Short name T789
Test name
Test status
Simulation time 2263136630 ps
CPU time 17.38 seconds
Started Apr 23 12:25:04 PM PDT 24
Finished Apr 23 12:25:23 PM PDT 24
Peak memory 201948 kb
Host smart-ed2fe1fa-6a29-4122-bb79-0031a3a10057
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243639247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.2243639247
Directory /workspace/37.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_all.1487195196
Short name T131
Test name
Test status
Simulation time 63400373868 ps
CPU time 2372.51 seconds
Started Apr 23 12:25:10 PM PDT 24
Finished Apr 23 01:04:48 PM PDT 24
Peak memory 373684 kb
Host smart-330281ea-f092-4510-b191-80cb61d7eaeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487195196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 37.sram_ctrl_stress_all.1487195196
Directory /workspace/37.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.1813462172
Short name T333
Test name
Test status
Simulation time 3172791618 ps
CPU time 629.96 seconds
Started Apr 23 12:25:04 PM PDT 24
Finished Apr 23 12:35:35 PM PDT 24
Peak memory 376408 kb
Host smart-c4c55614-b51c-47c1-9b22-7ad477fa9f6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1813462172 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.1813462172
Directory /workspace/37.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_pipeline.988895208
Short name T725
Test name
Test status
Simulation time 9149444033 ps
CPU time 203.55 seconds
Started Apr 23 12:25:06 PM PDT 24
Finished Apr 23 12:28:33 PM PDT 24
Peak memory 201896 kb
Host smart-864c8a45-e4ed-4453-afd8-5f3dc187bec2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988895208 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.sram_ctrl_stress_pipeline.988895208
Directory /workspace/37.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.3368063601
Short name T921
Test name
Test status
Simulation time 499416411 ps
CPU time 62.03 seconds
Started Apr 23 12:25:03 PM PDT 24
Finished Apr 23 12:26:06 PM PDT 24
Peak memory 339812 kb
Host smart-c9faba68-f253-499d-9812-8b550b58f9d4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368063601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.sram_ctrl_throughput_w_partial_write.3368063601
Directory /workspace/37.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/38.sram_ctrl_access_during_key_req.392956317
Short name T535
Test name
Test status
Simulation time 1481723617 ps
CPU time 219.58 seconds
Started Apr 23 12:25:13 PM PDT 24
Finished Apr 23 12:28:56 PM PDT 24
Peak memory 319568 kb
Host smart-6e3ad3ce-8d88-41f6-be9c-48acd9b24a57
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392956317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 38.sram_ctrl_access_during_key_req.392956317
Directory /workspace/38.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/38.sram_ctrl_alert_test.1683792080
Short name T632
Test name
Test status
Simulation time 13617666 ps
CPU time 0.64 seconds
Started Apr 23 12:25:33 PM PDT 24
Finished Apr 23 12:25:34 PM PDT 24
Peak memory 200912 kb
Host smart-1537bf2f-56fa-47f4-8bb6-f1c66345135d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683792080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.sram_ctrl_alert_test.1683792080
Directory /workspace/38.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sram_ctrl_bijection.644968656
Short name T331
Test name
Test status
Simulation time 18719535465 ps
CPU time 79.58 seconds
Started Apr 23 12:25:04 PM PDT 24
Finished Apr 23 12:26:25 PM PDT 24
Peak memory 201992 kb
Host smart-b94f8cfe-00e0-425a-b532-d706a75f215d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644968656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection.
644968656
Directory /workspace/38.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/38.sram_ctrl_executable.133958254
Short name T10
Test name
Test status
Simulation time 13027124017 ps
CPU time 996.62 seconds
Started Apr 23 12:25:09 PM PDT 24
Finished Apr 23 12:41:51 PM PDT 24
Peak memory 366596 kb
Host smart-e60f8d54-596e-409a-858e-b444b3ff54ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133958254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executabl
e.133958254
Directory /workspace/38.sram_ctrl_executable/latest

Test location /workspace/coverage/default/38.sram_ctrl_lc_escalation.3686765619
Short name T551
Test name
Test status
Simulation time 465670366 ps
CPU time 4.48 seconds
Started Apr 23 12:25:09 PM PDT 24
Finished Apr 23 12:25:18 PM PDT 24
Peak memory 201640 kb
Host smart-2b1f8817-8bed-4c68-9549-31792d751625
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686765619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_es
calation.3686765619
Directory /workspace/38.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/38.sram_ctrl_max_throughput.2333412434
Short name T240
Test name
Test status
Simulation time 117640902 ps
CPU time 0.94 seconds
Started Apr 23 12:25:10 PM PDT 24
Finished Apr 23 12:25:16 PM PDT 24
Peak memory 201732 kb
Host smart-bf933fbf-e87a-40ec-86f0-cfa977ca8772
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333412434 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.sram_ctrl_max_throughput.2333412434
Directory /workspace/38.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_partial_access.3484613191
Short name T631
Test name
Test status
Simulation time 321628434 ps
CPU time 4.25 seconds
Started Apr 23 12:25:07 PM PDT 24
Finished Apr 23 12:25:17 PM PDT 24
Peak memory 210044 kb
Host smart-f733fe52-6f64-45a5-91b9-627c8ca7f493
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484613191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.sram_ctrl_mem_partial_access.3484613191
Directory /workspace/38.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_walk.1872358842
Short name T611
Test name
Test status
Simulation time 265936504 ps
CPU time 7.57 seconds
Started Apr 23 12:25:09 PM PDT 24
Finished Apr 23 12:25:21 PM PDT 24
Peak memory 201788 kb
Host smart-864e1668-adb8-48fc-a971-2bc3e09f4ce0
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872358842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctr
l_mem_walk.1872358842
Directory /workspace/38.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/38.sram_ctrl_multiple_keys.3203204549
Short name T290
Test name
Test status
Simulation time 3429605104 ps
CPU time 34.21 seconds
Started Apr 23 12:25:07 PM PDT 24
Finished Apr 23 12:25:47 PM PDT 24
Peak memory 201952 kb
Host smart-761ad46e-9fe7-4580-8d93-bce70ea57af6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203204549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multi
ple_keys.3203204549
Directory /workspace/38.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access.2570934644
Short name T49
Test name
Test status
Simulation time 946315041 ps
CPU time 13.06 seconds
Started Apr 23 12:25:12 PM PDT 24
Finished Apr 23 12:25:28 PM PDT 24
Peak memory 201832 kb
Host smart-7decf9a3-fa7b-4c1d-8210-fd7af5223301
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570934644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
sram_ctrl_partial_access.2570934644
Directory /workspace/38.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.2022922681
Short name T408
Test name
Test status
Simulation time 6643728345 ps
CPU time 167.22 seconds
Started Apr 23 12:25:10 PM PDT 24
Finished Apr 23 12:28:02 PM PDT 24
Peak memory 201916 kb
Host smart-f42884e0-1017-4d4d-9bcf-1cbf32338a99
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022922681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 38.sram_ctrl_partial_access_b2b.2022922681
Directory /workspace/38.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/38.sram_ctrl_ram_cfg.3861752742
Short name T911
Test name
Test status
Simulation time 113980570 ps
CPU time 0.74 seconds
Started Apr 23 12:25:05 PM PDT 24
Finished Apr 23 12:25:08 PM PDT 24
Peak memory 202008 kb
Host smart-f60f1651-6e40-4c65-b5ae-0be25e28ed5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861752742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.3861752742
Directory /workspace/38.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/38.sram_ctrl_regwen.2799212569
Short name T171
Test name
Test status
Simulation time 647499311 ps
CPU time 21.47 seconds
Started Apr 23 12:25:12 PM PDT 24
Finished Apr 23 12:25:37 PM PDT 24
Peak memory 240544 kb
Host smart-2d957771-0b98-454d-95d2-1c20c31d4e37
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799212569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.2799212569
Directory /workspace/38.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/38.sram_ctrl_smoke.1801457402
Short name T183
Test name
Test status
Simulation time 766892739 ps
CPU time 16.24 seconds
Started Apr 23 12:25:00 PM PDT 24
Finished Apr 23 12:25:17 PM PDT 24
Peak memory 201872 kb
Host smart-f81d5d69-5750-4cf9-9fc9-9c58f3f9e1fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801457402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.1801457402
Directory /workspace/38.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_all.483753635
Short name T377
Test name
Test status
Simulation time 22808031678 ps
CPU time 1420.02 seconds
Started Apr 23 12:25:17 PM PDT 24
Finished Apr 23 12:49:00 PM PDT 24
Peak memory 383200 kb
Host smart-71104d0c-641d-4328-95f9-f16a4e64fc51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483753635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 38.sram_ctrl_stress_all.483753635
Directory /workspace/38.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3436128151
Short name T235
Test name
Test status
Simulation time 322043942 ps
CPU time 136.66 seconds
Started Apr 23 12:25:13 PM PDT 24
Finished Apr 23 12:27:33 PM PDT 24
Peak memory 377788 kb
Host smart-cf5bbd75-f880-40cb-b001-e279da84d705
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3436128151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.3436128151
Directory /workspace/38.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_pipeline.793147830
Short name T555
Test name
Test status
Simulation time 8384664600 ps
CPU time 385.69 seconds
Started Apr 23 12:25:07 PM PDT 24
Finished Apr 23 12:31:37 PM PDT 24
Peak memory 201892 kb
Host smart-3a954590-10a7-4beb-aa68-42e0071c18f2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793147830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.sram_ctrl_stress_pipeline.793147830
Directory /workspace/38.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.210595238
Short name T821
Test name
Test status
Simulation time 66551243 ps
CPU time 4.92 seconds
Started Apr 23 12:25:09 PM PDT 24
Finished Apr 23 12:25:19 PM PDT 24
Peak memory 232956 kb
Host smart-359aec80-0514-4a25-adfc-e630c83c0ba3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210595238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.sram_ctrl_throughput_w_partial_write.210595238
Directory /workspace/38.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/39.sram_ctrl_access_during_key_req.497621640
Short name T838
Test name
Test status
Simulation time 4190004856 ps
CPU time 111.42 seconds
Started Apr 23 12:25:14 PM PDT 24
Finished Apr 23 12:27:08 PM PDT 24
Peak memory 332788 kb
Host smart-4e3c0a5e-8476-4efb-bfb7-11df941a6d68
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497621640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 39.sram_ctrl_access_during_key_req.497621640
Directory /workspace/39.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/39.sram_ctrl_alert_test.392867244
Short name T900
Test name
Test status
Simulation time 22138454 ps
CPU time 0.65 seconds
Started Apr 23 12:25:08 PM PDT 24
Finished Apr 23 12:25:13 PM PDT 24
Peak memory 201736 kb
Host smart-7016fd83-705d-47bf-b6e5-6449e95ace1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392867244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.sram_ctrl_alert_test.392867244
Directory /workspace/39.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sram_ctrl_bijection.980845306
Short name T268
Test name
Test status
Simulation time 1367385781 ps
CPU time 20.16 seconds
Started Apr 23 12:25:12 PM PDT 24
Finished Apr 23 12:25:36 PM PDT 24
Peak memory 201944 kb
Host smart-d305f7c8-74fe-458a-bb0c-38377d01688a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980845306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection.
980845306
Directory /workspace/39.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/39.sram_ctrl_executable.2952281362
Short name T439
Test name
Test status
Simulation time 4762530543 ps
CPU time 300.23 seconds
Started Apr 23 12:25:07 PM PDT 24
Finished Apr 23 12:30:11 PM PDT 24
Peak memory 359448 kb
Host smart-aff600e5-185c-40d7-8733-166f1beb676e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952281362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executab
le.2952281362
Directory /workspace/39.sram_ctrl_executable/latest

Test location /workspace/coverage/default/39.sram_ctrl_lc_escalation.1650766473
Short name T757
Test name
Test status
Simulation time 946452013 ps
CPU time 7.51 seconds
Started Apr 23 12:25:12 PM PDT 24
Finished Apr 23 12:25:23 PM PDT 24
Peak memory 201892 kb
Host smart-f366b703-589f-4a12-b96a-3d22dce0f76d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650766473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_es
calation.1650766473
Directory /workspace/39.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/39.sram_ctrl_max_throughput.3211657961
Short name T212
Test name
Test status
Simulation time 110231793 ps
CPU time 63.22 seconds
Started Apr 23 12:25:10 PM PDT 24
Finished Apr 23 12:26:18 PM PDT 24
Peak memory 317356 kb
Host smart-806e749a-83e3-4c53-bbf7-f1d2ee9e8bae
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211657961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.sram_ctrl_max_throughput.3211657961
Directory /workspace/39.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_partial_access.3337598882
Short name T836
Test name
Test status
Simulation time 308563135 ps
CPU time 4.57 seconds
Started Apr 23 12:25:16 PM PDT 24
Finished Apr 23 12:25:24 PM PDT 24
Peak memory 210016 kb
Host smart-55416d83-ffe9-40e8-839e-978f8096233e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337598882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.sram_ctrl_mem_partial_access.3337598882
Directory /workspace/39.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_walk.4049435922
Short name T929
Test name
Test status
Simulation time 871407860 ps
CPU time 9.96 seconds
Started Apr 23 12:25:25 PM PDT 24
Finished Apr 23 12:25:37 PM PDT 24
Peak memory 201808 kb
Host smart-3f255df7-4c2c-43da-8bbc-60707c73c101
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049435922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctr
l_mem_walk.4049435922
Directory /workspace/39.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/39.sram_ctrl_multiple_keys.2546850226
Short name T769
Test name
Test status
Simulation time 2416825631 ps
CPU time 516.77 seconds
Started Apr 23 12:25:14 PM PDT 24
Finished Apr 23 12:33:54 PM PDT 24
Peak memory 373776 kb
Host smart-54566acf-087a-4205-8f3c-9893656b9fb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546850226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multi
ple_keys.2546850226
Directory /workspace/39.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access.1775492908
Short name T828
Test name
Test status
Simulation time 3477931754 ps
CPU time 15.91 seconds
Started Apr 23 12:25:08 PM PDT 24
Finished Apr 23 12:25:29 PM PDT 24
Peak memory 201884 kb
Host smart-2052ac2f-c0f9-4179-8988-09fdf1cc82df
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775492908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
sram_ctrl_partial_access.1775492908
Directory /workspace/39.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_ram_cfg.3239905903
Short name T33
Test name
Test status
Simulation time 27422371 ps
CPU time 0.75 seconds
Started Apr 23 12:25:20 PM PDT 24
Finished Apr 23 12:25:22 PM PDT 24
Peak memory 201944 kb
Host smart-1e6ae40e-2982-4774-bd7e-8961949c7520
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239905903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.3239905903
Directory /workspace/39.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/39.sram_ctrl_regwen.2093612757
Short name T452
Test name
Test status
Simulation time 1938370180 ps
CPU time 217.24 seconds
Started Apr 23 12:25:12 PM PDT 24
Finished Apr 23 12:28:53 PM PDT 24
Peak memory 349244 kb
Host smart-1ac22a1b-4fae-4140-913e-ea7fe4ce828e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093612757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.2093612757
Directory /workspace/39.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/39.sram_ctrl_smoke.1473446725
Short name T713
Test name
Test status
Simulation time 1425958290 ps
CPU time 11.57 seconds
Started Apr 23 12:25:16 PM PDT 24
Finished Apr 23 12:25:31 PM PDT 24
Peak memory 201888 kb
Host smart-89586382-5d84-48c1-bfcb-db8afe01b0ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473446725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.1473446725
Directory /workspace/39.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_all.2226519611
Short name T409
Test name
Test status
Simulation time 42306271986 ps
CPU time 2381.69 seconds
Started Apr 23 12:25:05 PM PDT 24
Finished Apr 23 01:04:49 PM PDT 24
Peak memory 374328 kb
Host smart-11f1ca0d-3ede-4e9e-8010-15cda07b76d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226519611 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 39.sram_ctrl_stress_all.2226519611
Directory /workspace/39.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.140597646
Short name T767
Test name
Test status
Simulation time 1895377294 ps
CPU time 352.38 seconds
Started Apr 23 12:25:05 PM PDT 24
Finished Apr 23 12:30:59 PM PDT 24
Peak memory 376784 kb
Host smart-cb81fe52-1de8-4d84-88d8-1a8bb315cb90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=140597646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.140597646
Directory /workspace/39.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_pipeline.3480192086
Short name T539
Test name
Test status
Simulation time 4397728943 ps
CPU time 208.2 seconds
Started Apr 23 12:25:09 PM PDT 24
Finished Apr 23 12:28:42 PM PDT 24
Peak memory 201868 kb
Host smart-e93d7c71-48e1-4e56-8012-c68074ceb424
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480192086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.sram_ctrl_stress_pipeline.3480192086
Directory /workspace/39.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.13440283
Short name T192
Test name
Test status
Simulation time 259934720 ps
CPU time 46.04 seconds
Started Apr 23 12:25:05 PM PDT 24
Finished Apr 23 12:25:52 PM PDT 24
Peak memory 304144 kb
Host smart-5bd153d0-7ea7-4ad4-be8f-7a1d09156d88
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13440283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.sram_ctrl_throughput_w_partial_write.13440283
Directory /workspace/39.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/4.sram_ctrl_access_during_key_req.2040776656
Short name T241
Test name
Test status
Simulation time 14654603236 ps
CPU time 765.46 seconds
Started Apr 23 12:23:12 PM PDT 24
Finished Apr 23 12:35:58 PM PDT 24
Peak memory 372656 kb
Host smart-49b75a80-6c93-486d-aea6-da160bf8c346
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040776656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.sram_ctrl_access_during_key_req.2040776656
Directory /workspace/4.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/4.sram_ctrl_alert_test.2561423129
Short name T411
Test name
Test status
Simulation time 16694031 ps
CPU time 0.67 seconds
Started Apr 23 12:23:14 PM PDT 24
Finished Apr 23 12:23:15 PM PDT 24
Peak memory 200896 kb
Host smart-bb19a486-45c7-4cc6-8f65-b16676bb612d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561423129 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_alert_test.2561423129
Directory /workspace/4.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sram_ctrl_bijection.2179993952
Short name T310
Test name
Test status
Simulation time 30998358721 ps
CPU time 83.66 seconds
Started Apr 23 12:24:29 PM PDT 24
Finished Apr 23 12:25:54 PM PDT 24
Peak memory 201680 kb
Host smart-8d093cb6-09c1-4281-b5d0-e70949b1c774
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179993952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.
2179993952
Directory /workspace/4.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/4.sram_ctrl_executable.717504427
Short name T308
Test name
Test status
Simulation time 3555331428 ps
CPU time 140.94 seconds
Started Apr 23 12:24:28 PM PDT 24
Finished Apr 23 12:26:50 PM PDT 24
Peak memory 316008 kb
Host smart-e446b99a-9e04-46a9-96ee-320f5fb9d90c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717504427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executable
.717504427
Directory /workspace/4.sram_ctrl_executable/latest

Test location /workspace/coverage/default/4.sram_ctrl_lc_escalation.1898938703
Short name T495
Test name
Test status
Simulation time 320838996 ps
CPU time 4.33 seconds
Started Apr 23 12:24:47 PM PDT 24
Finished Apr 23 12:24:52 PM PDT 24
Peak memory 201900 kb
Host smart-06dab9fa-6db2-4e52-aa3e-43c22d2b77c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898938703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esc
alation.1898938703
Directory /workspace/4.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/4.sram_ctrl_max_throughput.4166309464
Short name T316
Test name
Test status
Simulation time 414375496 ps
CPU time 48.3 seconds
Started Apr 23 12:23:12 PM PDT 24
Finished Apr 23 12:24:02 PM PDT 24
Peak memory 324592 kb
Host smart-7ac443dd-a7d2-4f8e-a44d-b2aacecd78b3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166309464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.sram_ctrl_max_throughput.4166309464
Directory /workspace/4.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_partial_access.380141743
Short name T890
Test name
Test status
Simulation time 157950426 ps
CPU time 4.79 seconds
Started Apr 23 12:23:14 PM PDT 24
Finished Apr 23 12:23:20 PM PDT 24
Peak memory 210072 kb
Host smart-11deecb8-7435-4233-a3f8-509640f14761
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380141743 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
sram_ctrl_mem_partial_access.380141743
Directory /workspace/4.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_walk.2219064143
Short name T685
Test name
Test status
Simulation time 1990655574 ps
CPU time 9.5 seconds
Started Apr 23 12:24:29 PM PDT 24
Finished Apr 23 12:24:40 PM PDT 24
Peak memory 201512 kb
Host smart-16c83747-147e-4a54-9f89-3988170081e6
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219064143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl
_mem_walk.2219064143
Directory /workspace/4.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/4.sram_ctrl_multiple_keys.2480220072
Short name T424
Test name
Test status
Simulation time 30823199091 ps
CPU time 1048.04 seconds
Started Apr 23 12:23:13 PM PDT 24
Finished Apr 23 12:40:42 PM PDT 24
Peak memory 371252 kb
Host smart-ccfcf6b7-7244-4e6b-9cd9-b7b52ef50a7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480220072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multip
le_keys.2480220072
Directory /workspace/4.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access.694043150
Short name T572
Test name
Test status
Simulation time 115845172 ps
CPU time 23.21 seconds
Started Apr 23 12:24:35 PM PDT 24
Finished Apr 23 12:25:00 PM PDT 24
Peak memory 277304 kb
Host smart-04756676-ee0f-487c-84e1-5493c3a7912c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694043150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sr
am_ctrl_partial_access.694043150
Directory /workspace/4.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.4193766548
Short name T379
Test name
Test status
Simulation time 8352877526 ps
CPU time 308.55 seconds
Started Apr 23 12:23:12 PM PDT 24
Finished Apr 23 12:28:22 PM PDT 24
Peak memory 201964 kb
Host smart-b7fcdf4e-8f0f-4bc4-81a9-ffa5a4ead6d5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193766548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 4.sram_ctrl_partial_access_b2b.4193766548
Directory /workspace/4.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/4.sram_ctrl_ram_cfg.4265326816
Short name T370
Test name
Test status
Simulation time 28502931 ps
CPU time 0.74 seconds
Started Apr 23 12:23:12 PM PDT 24
Finished Apr 23 12:23:14 PM PDT 24
Peak memory 202056 kb
Host smart-25343417-91ad-4505-9dc1-246aaf0450e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265326816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.4265326816
Directory /workspace/4.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/4.sram_ctrl_regwen.2324575091
Short name T846
Test name
Test status
Simulation time 15714420425 ps
CPU time 477.09 seconds
Started Apr 23 12:24:29 PM PDT 24
Finished Apr 23 12:32:27 PM PDT 24
Peak memory 366816 kb
Host smart-b414cdda-b55e-4b96-a3df-1b4601056b2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324575091 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.2324575091
Directory /workspace/4.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/4.sram_ctrl_sec_cm.3162809284
Short name T16
Test name
Test status
Simulation time 440622694 ps
CPU time 3.41 seconds
Started Apr 23 12:23:21 PM PDT 24
Finished Apr 23 12:23:25 PM PDT 24
Peak memory 223564 kb
Host smart-41d5d4dd-6f47-469d-8936-256f1874d2b8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162809284 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_sec_cm.3162809284
Directory /workspace/4.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sram_ctrl_smoke.266402253
Short name T592
Test name
Test status
Simulation time 3876890436 ps
CPU time 8.56 seconds
Started Apr 23 12:24:29 PM PDT 24
Finished Apr 23 12:24:39 PM PDT 24
Peak memory 201688 kb
Host smart-25c8ac53-6416-4406-bd53-181cc40570a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266402253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.266402253
Directory /workspace/4.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_all.4174698750
Short name T311
Test name
Test status
Simulation time 135395170040 ps
CPU time 2042.62 seconds
Started Apr 23 12:23:18 PM PDT 24
Finished Apr 23 12:57:21 PM PDT 24
Peak memory 372816 kb
Host smart-03990719-36d3-4b85-82d6-0ce4f655a990
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174698750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 4.sram_ctrl_stress_all.4174698750
Directory /workspace/4.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.3839367105
Short name T479
Test name
Test status
Simulation time 2008940652 ps
CPU time 246.08 seconds
Started Apr 23 12:23:14 PM PDT 24
Finished Apr 23 12:27:21 PM PDT 24
Peak memory 358864 kb
Host smart-491a4d9f-3279-4f37-9577-44eaebe3d9ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3839367105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.3839367105
Directory /workspace/4.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_pipeline.2634757887
Short name T266
Test name
Test status
Simulation time 11326009941 ps
CPU time 254.23 seconds
Started Apr 23 12:24:33 PM PDT 24
Finished Apr 23 12:28:48 PM PDT 24
Peak memory 201948 kb
Host smart-2d1f0271-36ef-4cdd-8be4-3f519d339cad
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634757887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.sram_ctrl_stress_pipeline.2634757887
Directory /workspace/4.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.3676389936
Short name T920
Test name
Test status
Simulation time 214784751 ps
CPU time 34.7 seconds
Started Apr 23 12:24:29 PM PDT 24
Finished Apr 23 12:25:05 PM PDT 24
Peak memory 299740 kb
Host smart-f2b003ed-6e69-4736-903f-489bcf9e8fcd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676389936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.sram_ctrl_throughput_w_partial_write.3676389936
Directory /workspace/4.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/40.sram_ctrl_access_during_key_req.963900886
Short name T426
Test name
Test status
Simulation time 4018998125 ps
CPU time 1223.39 seconds
Started Apr 23 12:25:13 PM PDT 24
Finished Apr 23 12:45:40 PM PDT 24
Peak memory 373692 kb
Host smart-06bef1a6-3edd-4157-9a70-4969f8867214
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963900886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 40.sram_ctrl_access_during_key_req.963900886
Directory /workspace/40.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/40.sram_ctrl_alert_test.2742230018
Short name T660
Test name
Test status
Simulation time 39380043 ps
CPU time 0.69 seconds
Started Apr 23 12:25:23 PM PDT 24
Finished Apr 23 12:25:25 PM PDT 24
Peak memory 201684 kb
Host smart-53117eda-55a5-428e-94fd-bfbc80048eb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742230018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.sram_ctrl_alert_test.2742230018
Directory /workspace/40.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sram_ctrl_bijection.2190786976
Short name T604
Test name
Test status
Simulation time 4655366890 ps
CPU time 66.33 seconds
Started Apr 23 12:25:12 PM PDT 24
Finished Apr 23 12:26:22 PM PDT 24
Peak memory 201960 kb
Host smart-60d8bd16-3f0e-42b2-9840-9ee0cd3517eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190786976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection
.2190786976
Directory /workspace/40.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/40.sram_ctrl_executable.15328024
Short name T683
Test name
Test status
Simulation time 14298463909 ps
CPU time 992.81 seconds
Started Apr 23 12:25:09 PM PDT 24
Finished Apr 23 12:41:47 PM PDT 24
Peak memory 373736 kb
Host smart-8e34764a-bf95-4a9e-9e26-756daef59200
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15328024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execut
able_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executable
.15328024
Directory /workspace/40.sram_ctrl_executable/latest

Test location /workspace/coverage/default/40.sram_ctrl_lc_escalation.418827843
Short name T739
Test name
Test status
Simulation time 1099901992 ps
CPU time 6.55 seconds
Started Apr 23 12:25:24 PM PDT 24
Finished Apr 23 12:25:32 PM PDT 24
Peak memory 201908 kb
Host smart-8a4ac046-af79-4919-a488-e5673eebaa25
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418827843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_esc
alation.418827843
Directory /workspace/40.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/40.sram_ctrl_max_throughput.3209326125
Short name T200
Test name
Test status
Simulation time 205646591 ps
CPU time 3.57 seconds
Started Apr 23 12:25:10 PM PDT 24
Finished Apr 23 12:25:18 PM PDT 24
Peak memory 222184 kb
Host smart-17dbf90b-d8b0-4fd7-a305-001c7b486a7d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209326125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 40.sram_ctrl_max_throughput.3209326125
Directory /workspace/40.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_partial_access.712682386
Short name T71
Test name
Test status
Simulation time 66118844 ps
CPU time 4.33 seconds
Started Apr 23 12:25:19 PM PDT 24
Finished Apr 23 12:25:25 PM PDT 24
Peak memory 210020 kb
Host smart-d2d56551-239e-467b-bab7-feaaf02ae082
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712682386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.sram_ctrl_mem_partial_access.712682386
Directory /workspace/40.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_walk.2305690561
Short name T948
Test name
Test status
Simulation time 1368724832 ps
CPU time 10.18 seconds
Started Apr 23 12:25:11 PM PDT 24
Finished Apr 23 12:25:25 PM PDT 24
Peak memory 201908 kb
Host smart-d2728e05-103d-4aa7-a163-03b79368a6dc
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305690561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctr
l_mem_walk.2305690561
Directory /workspace/40.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/40.sram_ctrl_multiple_keys.3529583780
Short name T863
Test name
Test status
Simulation time 14950398363 ps
CPU time 875.74 seconds
Started Apr 23 12:25:16 PM PDT 24
Finished Apr 23 12:39:55 PM PDT 24
Peak memory 371628 kb
Host smart-88614e27-e160-4bc9-adbc-671e2df0f63a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529583780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multi
ple_keys.3529583780
Directory /workspace/40.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access.3164193257
Short name T686
Test name
Test status
Simulation time 608735829 ps
CPU time 98.78 seconds
Started Apr 23 12:25:07 PM PDT 24
Finished Apr 23 12:26:50 PM PDT 24
Peak memory 350732 kb
Host smart-4f9cd0e7-a21b-486c-aa57-c752c7282e35
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164193257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
sram_ctrl_partial_access.3164193257
Directory /workspace/40.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.3300144933
Short name T111
Test name
Test status
Simulation time 253274540229 ps
CPU time 447.9 seconds
Started Apr 23 12:25:07 PM PDT 24
Finished Apr 23 12:32:40 PM PDT 24
Peak memory 201908 kb
Host smart-5f4db32b-af69-4671-ab60-9d9ba9f4c761
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300144933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 40.sram_ctrl_partial_access_b2b.3300144933
Directory /workspace/40.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/40.sram_ctrl_ram_cfg.3521713768
Short name T422
Test name
Test status
Simulation time 67455292 ps
CPU time 0.75 seconds
Started Apr 23 12:25:18 PM PDT 24
Finished Apr 23 12:25:21 PM PDT 24
Peak memory 202012 kb
Host smart-f91e6cc5-9d43-4718-96fc-b78c9f749bea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521713768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.3521713768
Directory /workspace/40.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/40.sram_ctrl_regwen.3335481674
Short name T284
Test name
Test status
Simulation time 8464671067 ps
CPU time 689.46 seconds
Started Apr 23 12:25:25 PM PDT 24
Finished Apr 23 12:36:56 PM PDT 24
Peak memory 366428 kb
Host smart-0177ec98-5a4e-4f80-9272-a2e8dca138b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335481674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.3335481674
Directory /workspace/40.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/40.sram_ctrl_smoke.3989921408
Short name T573
Test name
Test status
Simulation time 722006972 ps
CPU time 14.49 seconds
Started Apr 23 12:25:10 PM PDT 24
Finished Apr 23 12:25:29 PM PDT 24
Peak memory 201916 kb
Host smart-c7420d8b-cbfe-4a15-bed3-e2af00fbc4f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989921408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.3989921408
Directory /workspace/40.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_all.2647556864
Short name T944
Test name
Test status
Simulation time 55590264448 ps
CPU time 2732.21 seconds
Started Apr 23 12:25:13 PM PDT 24
Finished Apr 23 01:10:49 PM PDT 24
Peak memory 374812 kb
Host smart-c33f71a0-6a79-449d-844c-fad57d875836
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647556864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 40.sram_ctrl_stress_all.2647556864
Directory /workspace/40.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.793243975
Short name T100
Test name
Test status
Simulation time 2158754293 ps
CPU time 47.89 seconds
Started Apr 23 12:25:07 PM PDT 24
Finished Apr 23 12:26:00 PM PDT 24
Peak memory 296704 kb
Host smart-56ec3615-3b34-4079-80a7-83cf18612387
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=793243975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.793243975
Directory /workspace/40.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_pipeline.1942526321
Short name T211
Test name
Test status
Simulation time 8863196773 ps
CPU time 202.13 seconds
Started Apr 23 12:25:07 PM PDT 24
Finished Apr 23 12:28:35 PM PDT 24
Peak memory 201904 kb
Host smart-21b71311-53db-467f-9741-aeb7b1916a1d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942526321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.sram_ctrl_stress_pipeline.1942526321
Directory /workspace/40.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.3465882428
Short name T852
Test name
Test status
Simulation time 1041411826 ps
CPU time 124 seconds
Started Apr 23 12:25:16 PM PDT 24
Finished Apr 23 12:27:23 PM PDT 24
Peak memory 354180 kb
Host smart-656f87f1-6539-4753-95fa-e015824a1973
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465882428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.sram_ctrl_throughput_w_partial_write.3465882428
Directory /workspace/40.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/41.sram_ctrl_access_during_key_req.2588747002
Short name T38
Test name
Test status
Simulation time 4055474553 ps
CPU time 616.64 seconds
Started Apr 23 12:25:24 PM PDT 24
Finished Apr 23 12:35:42 PM PDT 24
Peak memory 372428 kb
Host smart-8780d4f2-d853-4734-82d6-7f193833d076
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588747002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.sram_ctrl_access_during_key_req.2588747002
Directory /workspace/41.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/41.sram_ctrl_alert_test.2034006478
Short name T818
Test name
Test status
Simulation time 19541136 ps
CPU time 0.64 seconds
Started Apr 23 12:25:20 PM PDT 24
Finished Apr 23 12:25:22 PM PDT 24
Peak memory 201664 kb
Host smart-1893bcb3-5c25-4d16-8caa-dc59e4ee28c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034006478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.sram_ctrl_alert_test.2034006478
Directory /workspace/41.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sram_ctrl_bijection.563526616
Short name T897
Test name
Test status
Simulation time 10885631838 ps
CPU time 33.72 seconds
Started Apr 23 12:25:19 PM PDT 24
Finished Apr 23 12:25:54 PM PDT 24
Peak memory 202032 kb
Host smart-26cf68b2-15bf-4e1d-88c6-fcf2bf56c134
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563526616 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection.
563526616
Directory /workspace/41.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/41.sram_ctrl_executable.1588194740
Short name T619
Test name
Test status
Simulation time 15083788149 ps
CPU time 932.93 seconds
Started Apr 23 12:25:19 PM PDT 24
Finished Apr 23 12:40:54 PM PDT 24
Peak memory 368644 kb
Host smart-5b804d10-1b28-4a8c-8503-6081a8a640d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588194740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executab
le.1588194740
Directory /workspace/41.sram_ctrl_executable/latest

Test location /workspace/coverage/default/41.sram_ctrl_lc_escalation.1231349835
Short name T760
Test name
Test status
Simulation time 1199794591 ps
CPU time 6.1 seconds
Started Apr 23 12:25:07 PM PDT 24
Finished Apr 23 12:25:18 PM PDT 24
Peak memory 201868 kb
Host smart-cd636a68-ca2d-42e2-ad06-3464744fb6de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231349835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_es
calation.1231349835
Directory /workspace/41.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/41.sram_ctrl_max_throughput.3146735245
Short name T557
Test name
Test status
Simulation time 513800361 ps
CPU time 116.35 seconds
Started Apr 23 12:25:17 PM PDT 24
Finished Apr 23 12:27:16 PM PDT 24
Peak memory 362412 kb
Host smart-710413f2-4a3d-408d-9e7e-079ace09e6a3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146735245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.sram_ctrl_max_throughput.3146735245
Directory /workspace/41.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_partial_access.1401946682
Short name T484
Test name
Test status
Simulation time 229285163 ps
CPU time 4.43 seconds
Started Apr 23 12:25:22 PM PDT 24
Finished Apr 23 12:25:28 PM PDT 24
Peak memory 210032 kb
Host smart-0a4e1187-c897-4ff2-8770-cc76a380efbe
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401946682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.sram_ctrl_mem_partial_access.1401946682
Directory /workspace/41.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_walk.1928219496
Short name T914
Test name
Test status
Simulation time 77927480 ps
CPU time 4.35 seconds
Started Apr 23 12:25:25 PM PDT 24
Finished Apr 23 12:25:30 PM PDT 24
Peak memory 201800 kb
Host smart-62cc6cea-1cf4-4744-99a7-f9454f1b484e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928219496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctr
l_mem_walk.1928219496
Directory /workspace/41.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/41.sram_ctrl_multiple_keys.162017528
Short name T870
Test name
Test status
Simulation time 4138680323 ps
CPU time 696.14 seconds
Started Apr 23 12:25:19 PM PDT 24
Finished Apr 23 12:36:57 PM PDT 24
Peak memory 351620 kb
Host smart-03085eb8-0be4-4a1e-a1a7-be0f239febf0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162017528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multip
le_keys.162017528
Directory /workspace/41.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access.2835147365
Short name T415
Test name
Test status
Simulation time 3636732565 ps
CPU time 9.27 seconds
Started Apr 23 12:25:16 PM PDT 24
Finished Apr 23 12:25:28 PM PDT 24
Peak memory 201952 kb
Host smart-237d3ad0-cf9b-4023-93c9-812bb13b16f8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835147365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
sram_ctrl_partial_access.2835147365
Directory /workspace/41.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.609682151
Short name T390
Test name
Test status
Simulation time 15064473883 ps
CPU time 323.65 seconds
Started Apr 23 12:25:15 PM PDT 24
Finished Apr 23 12:30:42 PM PDT 24
Peak memory 201912 kb
Host smart-9899fd0d-17f3-41ca-9b01-5473075302da
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609682151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.sram_ctrl_partial_access_b2b.609682151
Directory /workspace/41.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/41.sram_ctrl_ram_cfg.532666449
Short name T367
Test name
Test status
Simulation time 102025041 ps
CPU time 0.76 seconds
Started Apr 23 12:25:22 PM PDT 24
Finished Apr 23 12:25:23 PM PDT 24
Peak memory 201996 kb
Host smart-2dba35f2-d005-4c6a-9eea-7a27f5a4d722
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532666449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.532666449
Directory /workspace/41.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/41.sram_ctrl_regwen.1507009212
Short name T8
Test name
Test status
Simulation time 1501365531 ps
CPU time 517.64 seconds
Started Apr 23 12:25:28 PM PDT 24
Finished Apr 23 12:34:06 PM PDT 24
Peak memory 364532 kb
Host smart-56ce411b-649a-413f-ae90-50a88dc51053
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507009212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.1507009212
Directory /workspace/41.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/41.sram_ctrl_smoke.1225684414
Short name T375
Test name
Test status
Simulation time 116992722 ps
CPU time 68.37 seconds
Started Apr 23 12:25:22 PM PDT 24
Finished Apr 23 12:26:32 PM PDT 24
Peak memory 326124 kb
Host smart-ac906822-4c88-403c-b71a-6efb76a56115
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225684414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.1225684414
Directory /workspace/41.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_all.2556259002
Short name T939
Test name
Test status
Simulation time 82508981632 ps
CPU time 3497.32 seconds
Started Apr 23 12:25:16 PM PDT 24
Finished Apr 23 01:23:37 PM PDT 24
Peak memory 381920 kb
Host smart-567c604f-ac93-46d6-aacd-2098b2d51e9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556259002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 41.sram_ctrl_stress_all.2556259002
Directory /workspace/41.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.387854215
Short name T43
Test name
Test status
Simulation time 15208552262 ps
CPU time 297.77 seconds
Started Apr 23 12:25:11 PM PDT 24
Finished Apr 23 12:30:13 PM PDT 24
Peak memory 354484 kb
Host smart-3ef6a0f4-3e82-4580-9e88-39c8d94fdf82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=387854215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.387854215
Directory /workspace/41.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_pipeline.2026122355
Short name T326
Test name
Test status
Simulation time 5088077620 ps
CPU time 134.94 seconds
Started Apr 23 12:25:17 PM PDT 24
Finished Apr 23 12:27:34 PM PDT 24
Peak memory 201924 kb
Host smart-4aaa2c39-a5c1-49f6-8870-2068622db7df
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026122355 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.sram_ctrl_stress_pipeline.2026122355
Directory /workspace/41.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.1914282614
Short name T239
Test name
Test status
Simulation time 133105348 ps
CPU time 9.29 seconds
Started Apr 23 12:25:17 PM PDT 24
Finished Apr 23 12:25:29 PM PDT 24
Peak memory 239428 kb
Host smart-329d67c1-4236-4021-af2a-3ab13336eeda
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914282614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.sram_ctrl_throughput_w_partial_write.1914282614
Directory /workspace/41.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/42.sram_ctrl_access_during_key_req.3314361066
Short name T807
Test name
Test status
Simulation time 2274801549 ps
CPU time 474.56 seconds
Started Apr 23 12:25:18 PM PDT 24
Finished Apr 23 12:33:15 PM PDT 24
Peak memory 343808 kb
Host smart-6b64ae71-57a1-471e-9ef6-b541de41687e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314361066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.sram_ctrl_access_during_key_req.3314361066
Directory /workspace/42.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/42.sram_ctrl_alert_test.535711381
Short name T364
Test name
Test status
Simulation time 50857404 ps
CPU time 0.62 seconds
Started Apr 23 12:25:19 PM PDT 24
Finished Apr 23 12:25:21 PM PDT 24
Peak memory 201640 kb
Host smart-10bf2ac6-fb85-46b3-a0c9-50b69d5e5f83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535711381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.sram_ctrl_alert_test.535711381
Directory /workspace/42.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sram_ctrl_bijection.461764732
Short name T182
Test name
Test status
Simulation time 1765319753 ps
CPU time 27.09 seconds
Started Apr 23 12:25:23 PM PDT 24
Finished Apr 23 12:25:52 PM PDT 24
Peak memory 201900 kb
Host smart-dc0d4438-8271-4f45-a12f-cf5b16d73057
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461764732 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection.
461764732
Directory /workspace/42.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/42.sram_ctrl_executable.942256338
Short name T566
Test name
Test status
Simulation time 2933061885 ps
CPU time 1412.29 seconds
Started Apr 23 12:25:24 PM PDT 24
Finished Apr 23 12:48:57 PM PDT 24
Peak memory 373508 kb
Host smart-827f201f-0bbe-47aa-94cc-555d91a27e9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942256338 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executabl
e.942256338
Directory /workspace/42.sram_ctrl_executable/latest

Test location /workspace/coverage/default/42.sram_ctrl_lc_escalation.1580398442
Short name T656
Test name
Test status
Simulation time 682689480 ps
CPU time 5.22 seconds
Started Apr 23 12:25:17 PM PDT 24
Finished Apr 23 12:25:25 PM PDT 24
Peak memory 201924 kb
Host smart-73d355bf-dc1d-4047-83ed-628738215745
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580398442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_es
calation.1580398442
Directory /workspace/42.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/42.sram_ctrl_max_throughput.1961702795
Short name T113
Test name
Test status
Simulation time 190142750 ps
CPU time 1.94 seconds
Started Apr 23 12:25:26 PM PDT 24
Finished Apr 23 12:25:30 PM PDT 24
Peak memory 212832 kb
Host smart-8ccc028e-21dc-4d97-88ed-f23ede4ff432
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961702795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.sram_ctrl_max_throughput.1961702795
Directory /workspace/42.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_partial_access.2172797790
Short name T895
Test name
Test status
Simulation time 92150978 ps
CPU time 2.92 seconds
Started Apr 23 12:25:26 PM PDT 24
Finished Apr 23 12:25:31 PM PDT 24
Peak memory 210028 kb
Host smart-8457981b-0bc6-4b99-8d92-b1c18407526d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172797790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.sram_ctrl_mem_partial_access.2172797790
Directory /workspace/42.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_walk.3838710206
Short name T843
Test name
Test status
Simulation time 643628257 ps
CPU time 4.98 seconds
Started Apr 23 12:25:26 PM PDT 24
Finished Apr 23 12:25:33 PM PDT 24
Peak memory 201804 kb
Host smart-8c986043-8e3c-4678-a95d-c0e50135f951
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838710206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctr
l_mem_walk.3838710206
Directory /workspace/42.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/42.sram_ctrl_multiple_keys.3175745608
Short name T630
Test name
Test status
Simulation time 54559579960 ps
CPU time 782.24 seconds
Started Apr 23 12:25:30 PM PDT 24
Finished Apr 23 12:38:33 PM PDT 24
Peak memory 371692 kb
Host smart-506e59c6-4ef4-4e8f-adf2-18e1605b70c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175745608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multi
ple_keys.3175745608
Directory /workspace/42.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access.1197987491
Short name T800
Test name
Test status
Simulation time 414541009 ps
CPU time 133.25 seconds
Started Apr 23 12:25:26 PM PDT 24
Finished Apr 23 12:27:41 PM PDT 24
Peak memory 365336 kb
Host smart-7045f470-fd3a-48b6-a89a-a803e657effc
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197987491 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
sram_ctrl_partial_access.1197987491
Directory /workspace/42.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.902275457
Short name T844
Test name
Test status
Simulation time 18223154983 ps
CPU time 327.36 seconds
Started Apr 23 12:25:18 PM PDT 24
Finished Apr 23 12:30:48 PM PDT 24
Peak memory 201972 kb
Host smart-4ccefccc-f9ae-4060-90eb-4125c3948203
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902275457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.sram_ctrl_partial_access_b2b.902275457
Directory /workspace/42.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/42.sram_ctrl_ram_cfg.2593837612
Short name T147
Test name
Test status
Simulation time 33006057 ps
CPU time 0.77 seconds
Started Apr 23 12:25:24 PM PDT 24
Finished Apr 23 12:25:26 PM PDT 24
Peak memory 201936 kb
Host smart-00bfbcb2-0d1b-4ab5-9b84-bc660a146a23
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593837612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.2593837612
Directory /workspace/42.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/42.sram_ctrl_regwen.2908018133
Short name T859
Test name
Test status
Simulation time 4513395602 ps
CPU time 48.64 seconds
Started Apr 23 12:25:23 PM PDT 24
Finished Apr 23 12:26:13 PM PDT 24
Peak memory 235572 kb
Host smart-e7294432-099e-4340-a164-5da3c6f4a23d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908018133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.2908018133
Directory /workspace/42.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/42.sram_ctrl_smoke.3285351625
Short name T817
Test name
Test status
Simulation time 1215416429 ps
CPU time 20.98 seconds
Started Apr 23 12:25:26 PM PDT 24
Finished Apr 23 12:25:49 PM PDT 24
Peak memory 261036 kb
Host smart-423a64eb-6773-4547-894b-ed2fba55fc9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285351625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.3285351625
Directory /workspace/42.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_all.636726711
Short name T116
Test name
Test status
Simulation time 6959687886 ps
CPU time 362.48 seconds
Started Apr 23 12:25:17 PM PDT 24
Finished Apr 23 12:31:22 PM PDT 24
Peak memory 373080 kb
Host smart-194498ef-c9d3-4f79-a212-dd151cf23c59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636726711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 42.sram_ctrl_stress_all.636726711
Directory /workspace/42.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.654341347
Short name T419
Test name
Test status
Simulation time 4900191732 ps
CPU time 546.56 seconds
Started Apr 23 12:25:17 PM PDT 24
Finished Apr 23 12:34:26 PM PDT 24
Peak memory 375836 kb
Host smart-786f5ecc-ae0b-422a-9a29-a3280593f2f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=654341347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.654341347
Directory /workspace/42.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_pipeline.1697453108
Short name T287
Test name
Test status
Simulation time 16424561091 ps
CPU time 371.67 seconds
Started Apr 23 12:25:18 PM PDT 24
Finished Apr 23 12:31:32 PM PDT 24
Peak memory 201980 kb
Host smart-a4ff0989-bf45-43f9-9104-5400da7221c8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697453108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.sram_ctrl_stress_pipeline.1697453108
Directory /workspace/42.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.1774808731
Short name T179
Test name
Test status
Simulation time 123191962 ps
CPU time 65.36 seconds
Started Apr 23 12:25:24 PM PDT 24
Finished Apr 23 12:26:31 PM PDT 24
Peak memory 327580 kb
Host smart-74b4dad0-c22e-4950-9502-228b9a48fa9c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774808731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.sram_ctrl_throughput_w_partial_write.1774808731
Directory /workspace/42.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/43.sram_ctrl_access_during_key_req.2606939796
Short name T617
Test name
Test status
Simulation time 2187723274 ps
CPU time 925.79 seconds
Started Apr 23 12:25:26 PM PDT 24
Finished Apr 23 12:40:53 PM PDT 24
Peak memory 372716 kb
Host smart-0e9416d4-d616-4939-b40b-3ee8c021d713
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606939796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.sram_ctrl_access_during_key_req.2606939796
Directory /workspace/43.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/43.sram_ctrl_alert_test.1084662640
Short name T627
Test name
Test status
Simulation time 13389389 ps
CPU time 0.68 seconds
Started Apr 23 12:25:35 PM PDT 24
Finished Apr 23 12:25:37 PM PDT 24
Peak memory 201028 kb
Host smart-f586e02c-5a9f-4b48-a3ec-43714e2ecba7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084662640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.sram_ctrl_alert_test.1084662640
Directory /workspace/43.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sram_ctrl_bijection.2627464738
Short name T487
Test name
Test status
Simulation time 3561288315 ps
CPU time 59.43 seconds
Started Apr 23 12:25:26 PM PDT 24
Finished Apr 23 12:26:27 PM PDT 24
Peak memory 201936 kb
Host smart-72dee152-5631-4712-9989-159f4744bb0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627464738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection
.2627464738
Directory /workspace/43.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/43.sram_ctrl_executable.3169997625
Short name T323
Test name
Test status
Simulation time 6859775121 ps
CPU time 559.09 seconds
Started Apr 23 12:25:24 PM PDT 24
Finished Apr 23 12:34:44 PM PDT 24
Peak memory 372404 kb
Host smart-092ec5dd-00a8-4388-8d82-f696afa55b54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169997625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executab
le.3169997625
Directory /workspace/43.sram_ctrl_executable/latest

Test location /workspace/coverage/default/43.sram_ctrl_lc_escalation.3929249288
Short name T309
Test name
Test status
Simulation time 2188696775 ps
CPU time 4.98 seconds
Started Apr 23 12:25:23 PM PDT 24
Finished Apr 23 12:25:30 PM PDT 24
Peak memory 201996 kb
Host smart-cb79590e-3176-4928-a737-d37bf2c72a10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929249288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_es
calation.3929249288
Directory /workspace/43.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/43.sram_ctrl_max_throughput.864695682
Short name T854
Test name
Test status
Simulation time 329659557 ps
CPU time 2.39 seconds
Started Apr 23 12:25:25 PM PDT 24
Finished Apr 23 12:25:29 PM PDT 24
Peak memory 216972 kb
Host smart-df9f8c63-82c4-4f9d-9f85-f64e298071c3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864695682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.sram_ctrl_max_throughput.864695682
Directory /workspace/43.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_partial_access.1633178699
Short name T845
Test name
Test status
Simulation time 336229098 ps
CPU time 2.97 seconds
Started Apr 23 12:25:27 PM PDT 24
Finished Apr 23 12:25:31 PM PDT 24
Peak memory 210008 kb
Host smart-aefb8d59-77a6-4152-a373-2c1395f0cf6c
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633178699 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.sram_ctrl_mem_partial_access.1633178699
Directory /workspace/43.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_walk.2458456895
Short name T674
Test name
Test status
Simulation time 903444268 ps
CPU time 8.65 seconds
Started Apr 23 12:25:48 PM PDT 24
Finished Apr 23 12:25:57 PM PDT 24
Peak memory 201748 kb
Host smart-158a5ff7-be29-4c94-b353-6e5a976c9faf
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458456895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctr
l_mem_walk.2458456895
Directory /workspace/43.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/43.sram_ctrl_multiple_keys.1406032949
Short name T216
Test name
Test status
Simulation time 1952573393 ps
CPU time 547.89 seconds
Started Apr 23 12:25:26 PM PDT 24
Finished Apr 23 12:34:35 PM PDT 24
Peak memory 371764 kb
Host smart-0f84872e-41e2-4626-ae2e-fff241cdb381
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406032949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multi
ple_keys.1406032949
Directory /workspace/43.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access.1308167379
Short name T886
Test name
Test status
Simulation time 423752936 ps
CPU time 2.48 seconds
Started Apr 23 12:25:17 PM PDT 24
Finished Apr 23 12:25:22 PM PDT 24
Peak memory 201780 kb
Host smart-0cb0c4a8-62fa-423f-8aa1-bd5fd90bac81
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308167379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
sram_ctrl_partial_access.1308167379
Directory /workspace/43.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3155820993
Short name T722
Test name
Test status
Simulation time 17785489241 ps
CPU time 332.71 seconds
Started Apr 23 12:25:25 PM PDT 24
Finished Apr 23 12:30:59 PM PDT 24
Peak memory 201980 kb
Host smart-023af01e-fc7a-4959-a411-5a354d420fa0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155820993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 43.sram_ctrl_partial_access_b2b.3155820993
Directory /workspace/43.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/43.sram_ctrl_ram_cfg.686525188
Short name T662
Test name
Test status
Simulation time 199254877 ps
CPU time 0.79 seconds
Started Apr 23 12:25:23 PM PDT 24
Finished Apr 23 12:25:25 PM PDT 24
Peak memory 201984 kb
Host smart-37834848-4666-4cc0-923a-151c7fe8a363
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686525188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.686525188
Directory /workspace/43.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/43.sram_ctrl_regwen.2958237328
Short name T178
Test name
Test status
Simulation time 33133780912 ps
CPU time 520.48 seconds
Started Apr 23 12:25:44 PM PDT 24
Finished Apr 23 12:34:26 PM PDT 24
Peak memory 360812 kb
Host smart-7cd4090d-17f2-4465-ba39-08c581269101
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958237328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.2958237328
Directory /workspace/43.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/43.sram_ctrl_smoke.2086239448
Short name T491
Test name
Test status
Simulation time 738842246 ps
CPU time 31.28 seconds
Started Apr 23 12:25:20 PM PDT 24
Finished Apr 23 12:25:52 PM PDT 24
Peak memory 279116 kb
Host smart-58f84f8e-0038-4e85-8610-5fde91eac380
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086239448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.2086239448
Directory /workspace/43.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_all.1189648539
Short name T195
Test name
Test status
Simulation time 655635863046 ps
CPU time 3361.59 seconds
Started Apr 23 12:25:40 PM PDT 24
Finished Apr 23 01:21:43 PM PDT 24
Peak memory 373796 kb
Host smart-8b814904-db4a-4d80-9631-f9df1b554511
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189648539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 43.sram_ctrl_stress_all.1189648539
Directory /workspace/43.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.211715729
Short name T48
Test name
Test status
Simulation time 2075642521 ps
CPU time 1004.85 seconds
Started Apr 23 12:25:26 PM PDT 24
Finished Apr 23 12:42:12 PM PDT 24
Peak memory 377832 kb
Host smart-2efc1564-e0e4-4488-bfd8-8145d5449f9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=211715729 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.211715729
Directory /workspace/43.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_pipeline.1705704528
Short name T9
Test name
Test status
Simulation time 2457395476 ps
CPU time 209.51 seconds
Started Apr 23 12:25:40 PM PDT 24
Finished Apr 23 12:29:10 PM PDT 24
Peak memory 201864 kb
Host smart-5fcf5211-15cc-4c73-a53a-9702aa4d358a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705704528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.sram_ctrl_stress_pipeline.1705704528
Directory /workspace/43.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1262230785
Short name T267
Test name
Test status
Simulation time 231657843 ps
CPU time 53.62 seconds
Started Apr 23 12:25:24 PM PDT 24
Finished Apr 23 12:26:19 PM PDT 24
Peak memory 315152 kb
Host smart-115c0ead-95f3-42a5-beec-4f0e7e3546ff
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262230785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.sram_ctrl_throughput_w_partial_write.1262230785
Directory /workspace/43.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/44.sram_ctrl_access_during_key_req.1261134320
Short name T443
Test name
Test status
Simulation time 13141382514 ps
CPU time 1194.06 seconds
Started Apr 23 12:25:33 PM PDT 24
Finished Apr 23 12:45:28 PM PDT 24
Peak memory 371680 kb
Host smart-28599419-6d24-44f2-8bb0-dbd17cc49efd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261134320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.sram_ctrl_access_during_key_req.1261134320
Directory /workspace/44.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/44.sram_ctrl_alert_test.1295379709
Short name T180
Test name
Test status
Simulation time 36443240 ps
CPU time 0.65 seconds
Started Apr 23 12:25:23 PM PDT 24
Finished Apr 23 12:25:25 PM PDT 24
Peak memory 201096 kb
Host smart-3fd1a9bc-d100-41a0-bce9-0843a71947f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295379709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.sram_ctrl_alert_test.1295379709
Directory /workspace/44.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sram_ctrl_bijection.3157714371
Short name T823
Test name
Test status
Simulation time 5446912658 ps
CPU time 41.71 seconds
Started Apr 23 12:25:30 PM PDT 24
Finished Apr 23 12:26:12 PM PDT 24
Peak memory 202084 kb
Host smart-544ef892-d052-4c47-886e-cc00c356d934
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157714371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection
.3157714371
Directory /workspace/44.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/44.sram_ctrl_executable.711126021
Short name T132
Test name
Test status
Simulation time 14230103303 ps
CPU time 930.47 seconds
Started Apr 23 12:25:38 PM PDT 24
Finished Apr 23 12:41:10 PM PDT 24
Peak memory 369692 kb
Host smart-561dca3a-e33f-4efd-baed-2d44df4a1a58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711126021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executabl
e.711126021
Directory /workspace/44.sram_ctrl_executable/latest

Test location /workspace/coverage/default/44.sram_ctrl_lc_escalation.2574881903
Short name T355
Test name
Test status
Simulation time 604155623 ps
CPU time 6.73 seconds
Started Apr 23 12:25:25 PM PDT 24
Finished Apr 23 12:25:33 PM PDT 24
Peak memory 201880 kb
Host smart-9dd9060f-2953-416a-a308-a7bd573797eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574881903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_es
calation.2574881903
Directory /workspace/44.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/44.sram_ctrl_max_throughput.3227126563
Short name T144
Test name
Test status
Simulation time 1049044830 ps
CPU time 118.48 seconds
Started Apr 23 12:25:40 PM PDT 24
Finished Apr 23 12:27:39 PM PDT 24
Peak memory 365136 kb
Host smart-5cde3622-048c-440b-be48-13da3e5f1690
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227126563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 44.sram_ctrl_max_throughput.3227126563
Directory /workspace/44.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_partial_access.1663585646
Short name T490
Test name
Test status
Simulation time 238646399 ps
CPU time 2.6 seconds
Started Apr 23 12:25:23 PM PDT 24
Finished Apr 23 12:25:27 PM PDT 24
Peak memory 210012 kb
Host smart-e6673d62-e4ee-49e7-af03-a675bde17948
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663585646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.sram_ctrl_mem_partial_access.1663585646
Directory /workspace/44.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_walk.2624964024
Short name T813
Test name
Test status
Simulation time 83626081 ps
CPU time 4.09 seconds
Started Apr 23 12:25:27 PM PDT 24
Finished Apr 23 12:25:32 PM PDT 24
Peak memory 201712 kb
Host smart-889972da-d6b2-40bd-a5dd-fb7b0de35f3b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624964024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctr
l_mem_walk.2624964024
Directory /workspace/44.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/44.sram_ctrl_multiple_keys.3763351657
Short name T666
Test name
Test status
Simulation time 9335763901 ps
CPU time 1643.59 seconds
Started Apr 23 12:25:46 PM PDT 24
Finished Apr 23 12:53:11 PM PDT 24
Peak memory 371348 kb
Host smart-e88a9f26-9a89-4953-b5ce-bdd48a1f3f7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763351657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multi
ple_keys.3763351657
Directory /workspace/44.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access.235804818
Short name T519
Test name
Test status
Simulation time 268607658 ps
CPU time 5.38 seconds
Started Apr 23 12:25:25 PM PDT 24
Finished Apr 23 12:25:32 PM PDT 24
Peak memory 201808 kb
Host smart-e5c9791e-2c33-469d-b3fa-09394a148147
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235804818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.s
ram_ctrl_partial_access.235804818
Directory /workspace/44.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2474248656
Short name T329
Test name
Test status
Simulation time 8701303157 ps
CPU time 218.59 seconds
Started Apr 23 12:25:32 PM PDT 24
Finished Apr 23 12:29:11 PM PDT 24
Peak memory 201908 kb
Host smart-ac3a86a0-bf59-401d-b8d5-dfbbccb81113
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474248656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 44.sram_ctrl_partial_access_b2b.2474248656
Directory /workspace/44.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/44.sram_ctrl_ram_cfg.4049506414
Short name T434
Test name
Test status
Simulation time 203643777 ps
CPU time 0.78 seconds
Started Apr 23 12:25:23 PM PDT 24
Finished Apr 23 12:25:25 PM PDT 24
Peak memory 201984 kb
Host smart-b9bafbda-75a1-4f48-bd7b-b8db6ab481a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049506414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.4049506414
Directory /workspace/44.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/44.sram_ctrl_regwen.2598845872
Short name T733
Test name
Test status
Simulation time 20682102722 ps
CPU time 773.42 seconds
Started Apr 23 12:25:25 PM PDT 24
Finished Apr 23 12:38:20 PM PDT 24
Peak memory 366864 kb
Host smart-74ec70ef-673d-4cd3-8fae-24703ba999b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598845872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.2598845872
Directory /workspace/44.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/44.sram_ctrl_smoke.482463318
Short name T622
Test name
Test status
Simulation time 2276072941 ps
CPU time 27.91 seconds
Started Apr 23 12:25:22 PM PDT 24
Finished Apr 23 12:25:51 PM PDT 24
Peak memory 282720 kb
Host smart-a3406351-0d26-46fb-8332-052a9df1f251
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482463318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.482463318
Directory /workspace/44.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_all.1507644323
Short name T673
Test name
Test status
Simulation time 73185451375 ps
CPU time 1606.8 seconds
Started Apr 23 12:25:25 PM PDT 24
Finished Apr 23 12:52:13 PM PDT 24
Peak memory 372660 kb
Host smart-18fab3a2-a625-447e-9be2-5c1a7c963594
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507644323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 44.sram_ctrl_stress_all.1507644323
Directory /workspace/44.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1165601592
Short name T42
Test name
Test status
Simulation time 13969470426 ps
CPU time 63.98 seconds
Started Apr 23 12:25:22 PM PDT 24
Finished Apr 23 12:26:27 PM PDT 24
Peak memory 288784 kb
Host smart-d5e7023e-095a-4618-a24a-b8c5eb720a7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1165601592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.1165601592
Directory /workspace/44.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_pipeline.3917363817
Short name T362
Test name
Test status
Simulation time 1614920478 ps
CPU time 137.58 seconds
Started Apr 23 12:25:33 PM PDT 24
Finished Apr 23 12:27:51 PM PDT 24
Peak memory 201800 kb
Host smart-9c97e50d-ebc7-4b9c-aff9-74fc02e2f991
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917363817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.sram_ctrl_stress_pipeline.3917363817
Directory /workspace/44.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.3968812057
Short name T201
Test name
Test status
Simulation time 125052391 ps
CPU time 35.19 seconds
Started Apr 23 12:25:18 PM PDT 24
Finished Apr 23 12:25:55 PM PDT 24
Peak memory 308672 kb
Host smart-68236a5b-c035-43dd-a8b8-554fa3219e66
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968812057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.3968812057
Directory /workspace/44.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/45.sram_ctrl_access_during_key_req.3918571509
Short name T830
Test name
Test status
Simulation time 3461006132 ps
CPU time 1556.38 seconds
Started Apr 23 12:25:29 PM PDT 24
Finished Apr 23 12:51:27 PM PDT 24
Peak memory 372716 kb
Host smart-1cada105-55d2-4a41-a854-cb58fc9eb37a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918571509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.sram_ctrl_access_during_key_req.3918571509
Directory /workspace/45.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/45.sram_ctrl_alert_test.3624906365
Short name T868
Test name
Test status
Simulation time 19211839 ps
CPU time 0.64 seconds
Started Apr 23 12:25:20 PM PDT 24
Finished Apr 23 12:25:22 PM PDT 24
Peak memory 201068 kb
Host smart-3e864033-f62f-47dc-b30a-2a5f6104764f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624906365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.sram_ctrl_alert_test.3624906365
Directory /workspace/45.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sram_ctrl_bijection.3645069649
Short name T588
Test name
Test status
Simulation time 1549094238 ps
CPU time 30.05 seconds
Started Apr 23 12:25:25 PM PDT 24
Finished Apr 23 12:25:57 PM PDT 24
Peak memory 201852 kb
Host smart-b6dda6cd-b24a-4fb2-a296-433301e9d94f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645069649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection
.3645069649
Directory /workspace/45.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/45.sram_ctrl_executable.3933038671
Short name T499
Test name
Test status
Simulation time 7665509751 ps
CPU time 1519.38 seconds
Started Apr 23 12:25:23 PM PDT 24
Finished Apr 23 12:50:44 PM PDT 24
Peak memory 372748 kb
Host smart-f4367f9f-c1c8-4c11-8229-af22b95ad6f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933038671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executab
le.3933038671
Directory /workspace/45.sram_ctrl_executable/latest

Test location /workspace/coverage/default/45.sram_ctrl_lc_escalation.1986377736
Short name T531
Test name
Test status
Simulation time 1123193330 ps
CPU time 10.7 seconds
Started Apr 23 12:25:37 PM PDT 24
Finished Apr 23 12:25:48 PM PDT 24
Peak memory 201864 kb
Host smart-96512c86-fa6f-4b38-8f03-01ec8f256512
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986377736 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_es
calation.1986377736
Directory /workspace/45.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/45.sram_ctrl_max_throughput.1905518009
Short name T319
Test name
Test status
Simulation time 52226496 ps
CPU time 4.52 seconds
Started Apr 23 12:25:30 PM PDT 24
Finished Apr 23 12:25:35 PM PDT 24
Peak memory 224692 kb
Host smart-b031def0-8737-4c6b-bf36-8511e8a44bcd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905518009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.sram_ctrl_max_throughput.1905518009
Directory /workspace/45.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_partial_access.649853308
Short name T2
Test name
Test status
Simulation time 607893084 ps
CPU time 3.01 seconds
Started Apr 23 12:25:31 PM PDT 24
Finished Apr 23 12:25:34 PM PDT 24
Peak memory 210032 kb
Host smart-4a2c5dd8-ebd5-43c0-abaf-3f7d52eca24f
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649853308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.sram_ctrl_mem_partial_access.649853308
Directory /workspace/45.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_walk.1761590224
Short name T339
Test name
Test status
Simulation time 72681636 ps
CPU time 4.2 seconds
Started Apr 23 12:25:38 PM PDT 24
Finished Apr 23 12:25:43 PM PDT 24
Peak memory 201760 kb
Host smart-1e23ddfd-8796-4877-8c87-952f80b1b42d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761590224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctr
l_mem_walk.1761590224
Directory /workspace/45.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/45.sram_ctrl_multiple_keys.463778627
Short name T922
Test name
Test status
Simulation time 82981163923 ps
CPU time 1573.2 seconds
Started Apr 23 12:25:36 PM PDT 24
Finished Apr 23 12:51:50 PM PDT 24
Peak memory 374804 kb
Host smart-1bbf4180-36ee-4816-bb58-cebd67a5b448
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463778627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multip
le_keys.463778627
Directory /workspace/45.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access.1408427305
Short name T506
Test name
Test status
Simulation time 5917862574 ps
CPU time 67.75 seconds
Started Apr 23 12:25:27 PM PDT 24
Finished Apr 23 12:26:36 PM PDT 24
Peak memory 357228 kb
Host smart-aa89ca4b-7294-4c24-86da-2ac0a950f01a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408427305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
sram_ctrl_partial_access.1408427305
Directory /workspace/45.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2864677706
Short name T193
Test name
Test status
Simulation time 54229608933 ps
CPU time 368.14 seconds
Started Apr 23 12:25:29 PM PDT 24
Finished Apr 23 12:31:38 PM PDT 24
Peak memory 201956 kb
Host smart-047d2a14-38c8-4e7b-90e8-8d3f0f518ce1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864677706 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 45.sram_ctrl_partial_access_b2b.2864677706
Directory /workspace/45.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/45.sram_ctrl_ram_cfg.810732836
Short name T26
Test name
Test status
Simulation time 445431715 ps
CPU time 0.75 seconds
Started Apr 23 12:25:36 PM PDT 24
Finished Apr 23 12:25:38 PM PDT 24
Peak memory 201908 kb
Host smart-10ebaeaf-3a2e-481f-b7ce-b0df753bf65f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810732836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.810732836
Directory /workspace/45.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/45.sram_ctrl_regwen.2329614067
Short name T715
Test name
Test status
Simulation time 13807949760 ps
CPU time 1038.42 seconds
Started Apr 23 12:25:27 PM PDT 24
Finished Apr 23 12:42:46 PM PDT 24
Peak memory 374664 kb
Host smart-fddb676a-76df-4f62-acf8-798dfd03bda7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329614067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.2329614067
Directory /workspace/45.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/45.sram_ctrl_smoke.1984988837
Short name T677
Test name
Test status
Simulation time 1596712612 ps
CPU time 8.1 seconds
Started Apr 23 12:25:20 PM PDT 24
Finished Apr 23 12:25:29 PM PDT 24
Peak memory 201828 kb
Host smart-b534c2f8-9dc5-4069-9409-b4e91904c41d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984988837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.1984988837
Directory /workspace/45.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_all.4255780658
Short name T618
Test name
Test status
Simulation time 61870743562 ps
CPU time 1630.15 seconds
Started Apr 23 12:25:27 PM PDT 24
Finished Apr 23 12:52:38 PM PDT 24
Peak memory 373336 kb
Host smart-80846e5f-c211-4d34-9137-efb80b89997f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255780658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 45.sram_ctrl_stress_all.4255780658
Directory /workspace/45.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.108029221
Short name T773
Test name
Test status
Simulation time 6850689372 ps
CPU time 679.75 seconds
Started Apr 23 12:25:40 PM PDT 24
Finished Apr 23 12:37:00 PM PDT 24
Peak memory 373876 kb
Host smart-19067fe2-0dd6-4cc5-8d02-8498479683e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=108029221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.108029221
Directory /workspace/45.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_pipeline.3094553874
Short name T343
Test name
Test status
Simulation time 2205226740 ps
CPU time 197.91 seconds
Started Apr 23 12:25:35 PM PDT 24
Finished Apr 23 12:28:54 PM PDT 24
Peak memory 201964 kb
Host smart-0a3ec3b3-bc63-455e-b377-51993b092d1b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094553874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.sram_ctrl_stress_pipeline.3094553874
Directory /workspace/45.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1337429691
Short name T820
Test name
Test status
Simulation time 367077539 ps
CPU time 28.18 seconds
Started Apr 23 12:25:37 PM PDT 24
Finished Apr 23 12:26:06 PM PDT 24
Peak memory 280604 kb
Host smart-7415d517-fb7b-4cf0-8de1-48bd2a4b5420
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337429691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.sram_ctrl_throughput_w_partial_write.1337429691
Directory /workspace/45.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/46.sram_ctrl_access_during_key_req.2917640937
Short name T936
Test name
Test status
Simulation time 3325957172 ps
CPU time 359.73 seconds
Started Apr 23 12:25:38 PM PDT 24
Finished Apr 23 12:31:38 PM PDT 24
Peak memory 351072 kb
Host smart-0df39ad8-27dd-4a1d-aff3-4e1a82f46219
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917640937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.sram_ctrl_access_during_key_req.2917640937
Directory /workspace/46.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/46.sram_ctrl_alert_test.2829170867
Short name T657
Test name
Test status
Simulation time 127617723 ps
CPU time 0.64 seconds
Started Apr 23 12:25:35 PM PDT 24
Finished Apr 23 12:25:36 PM PDT 24
Peak memory 200920 kb
Host smart-47b202fb-635b-46c3-bb97-322e68cf2588
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829170867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.sram_ctrl_alert_test.2829170867
Directory /workspace/46.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sram_ctrl_bijection.326558884
Short name T606
Test name
Test status
Simulation time 450519975 ps
CPU time 28.76 seconds
Started Apr 23 12:25:49 PM PDT 24
Finished Apr 23 12:26:18 PM PDT 24
Peak memory 202064 kb
Host smart-0b7c75a7-ef8e-41f5-baf9-37bac67fe674
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326558884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection.
326558884
Directory /workspace/46.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/46.sram_ctrl_executable.3383812263
Short name T856
Test name
Test status
Simulation time 1160991908 ps
CPU time 266.12 seconds
Started Apr 23 12:25:31 PM PDT 24
Finished Apr 23 12:29:57 PM PDT 24
Peak memory 364940 kb
Host smart-40987fac-f752-4906-ad24-22816ee7adc6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383812263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executab
le.3383812263
Directory /workspace/46.sram_ctrl_executable/latest

Test location /workspace/coverage/default/46.sram_ctrl_lc_escalation.759380845
Short name T642
Test name
Test status
Simulation time 723346925 ps
CPU time 8.79 seconds
Started Apr 23 12:25:42 PM PDT 24
Finished Apr 23 12:25:52 PM PDT 24
Peak memory 201860 kb
Host smart-5f5cbf5c-0c08-46f3-93a9-27cb598e0e39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759380845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_esc
alation.759380845
Directory /workspace/46.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/46.sram_ctrl_max_throughput.3390992266
Short name T768
Test name
Test status
Simulation time 706903137 ps
CPU time 89.95 seconds
Started Apr 23 12:25:52 PM PDT 24
Finished Apr 23 12:27:23 PM PDT 24
Peak memory 351704 kb
Host smart-dfc1352c-18c4-4043-824d-041e1a204a47
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390992266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 46.sram_ctrl_max_throughput.3390992266
Directory /workspace/46.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_partial_access.3108104797
Short name T194
Test name
Test status
Simulation time 121589401 ps
CPU time 4.41 seconds
Started Apr 23 12:25:44 PM PDT 24
Finished Apr 23 12:25:50 PM PDT 24
Peak memory 210084 kb
Host smart-a305bee0-5cdf-45ee-b6c2-c7b8b31791e6
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108104797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.sram_ctrl_mem_partial_access.3108104797
Directory /workspace/46.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_walk.3143908312
Short name T913
Test name
Test status
Simulation time 468386777 ps
CPU time 4.77 seconds
Started Apr 23 12:25:30 PM PDT 24
Finished Apr 23 12:25:35 PM PDT 24
Peak memory 201792 kb
Host smart-e76e266c-9585-41e1-ba17-5baf70909703
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143908312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctr
l_mem_walk.3143908312
Directory /workspace/46.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/46.sram_ctrl_multiple_keys.2317692228
Short name T133
Test name
Test status
Simulation time 38228310692 ps
CPU time 722.54 seconds
Started Apr 23 12:25:32 PM PDT 24
Finished Apr 23 12:37:35 PM PDT 24
Peak memory 371672 kb
Host smart-a8d050e1-646c-4170-8cb9-c32f3f7ad71a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317692228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multi
ple_keys.2317692228
Directory /workspace/46.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access.1639583275
Short name T672
Test name
Test status
Simulation time 82527701 ps
CPU time 1.44 seconds
Started Apr 23 12:25:42 PM PDT 24
Finished Apr 23 12:25:44 PM PDT 24
Peak memory 201828 kb
Host smart-0da0039d-430e-43df-9916-505720b52e57
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639583275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
sram_ctrl_partial_access.1639583275
Directory /workspace/46.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3328926305
Short name T170
Test name
Test status
Simulation time 13001826524 ps
CPU time 332.38 seconds
Started Apr 23 12:25:46 PM PDT 24
Finished Apr 23 12:31:20 PM PDT 24
Peak memory 201552 kb
Host smart-0fd800fb-43e8-4fc3-b587-ff3ab1a4ffe7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328926305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 46.sram_ctrl_partial_access_b2b.3328926305
Directory /workspace/46.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/46.sram_ctrl_ram_cfg.3699022220
Short name T456
Test name
Test status
Simulation time 109910705 ps
CPU time 0.75 seconds
Started Apr 23 12:25:43 PM PDT 24
Finished Apr 23 12:25:44 PM PDT 24
Peak memory 202016 kb
Host smart-90213ec9-ee66-41b7-8529-c8cc5133c06c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699022220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.3699022220
Directory /workspace/46.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/46.sram_ctrl_regwen.145095909
Short name T511
Test name
Test status
Simulation time 10433834931 ps
CPU time 634.75 seconds
Started Apr 23 12:25:39 PM PDT 24
Finished Apr 23 12:36:15 PM PDT 24
Peak memory 353876 kb
Host smart-5009f22b-9e41-4f06-b62d-1866548d41e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145095909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.145095909
Directory /workspace/46.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/46.sram_ctrl_smoke.3882961229
Short name T949
Test name
Test status
Simulation time 645035141 ps
CPU time 10.47 seconds
Started Apr 23 12:25:29 PM PDT 24
Finished Apr 23 12:25:41 PM PDT 24
Peak memory 201884 kb
Host smart-b082f80a-aa76-4235-9142-6932df78b577
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882961229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.3882961229
Directory /workspace/46.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2344089796
Short name T806
Test name
Test status
Simulation time 279295900 ps
CPU time 128.08 seconds
Started Apr 23 12:25:29 PM PDT 24
Finished Apr 23 12:27:38 PM PDT 24
Peak memory 372352 kb
Host smart-48fb5c3b-9ad4-4829-a7fa-61486fc28e2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2344089796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.2344089796
Directory /workspace/46.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_pipeline.1923175730
Short name T321
Test name
Test status
Simulation time 13505365240 ps
CPU time 274.76 seconds
Started Apr 23 12:25:44 PM PDT 24
Finished Apr 23 12:30:19 PM PDT 24
Peak memory 201888 kb
Host smart-944b7df1-68eb-40d8-8f69-4ca115d8b385
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923175730 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.sram_ctrl_stress_pipeline.1923175730
Directory /workspace/46.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.515601319
Short name T297
Test name
Test status
Simulation time 226424033 ps
CPU time 6.61 seconds
Started Apr 23 12:25:25 PM PDT 24
Finished Apr 23 12:25:33 PM PDT 24
Peak memory 234672 kb
Host smart-9a658416-0071-4be8-8126-ec549f56e9c4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515601319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 46.sram_ctrl_throughput_w_partial_write.515601319
Directory /workspace/46.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/47.sram_ctrl_access_during_key_req.4288441998
Short name T251
Test name
Test status
Simulation time 3065392849 ps
CPU time 325.1 seconds
Started Apr 23 12:25:44 PM PDT 24
Finished Apr 23 12:31:10 PM PDT 24
Peak memory 372000 kb
Host smart-b3dbf651-aabd-4135-b44d-21e3e7632499
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288441998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.sram_ctrl_access_during_key_req.4288441998
Directory /workspace/47.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/47.sram_ctrl_alert_test.1997546291
Short name T288
Test name
Test status
Simulation time 33951401 ps
CPU time 0.62 seconds
Started Apr 23 12:25:31 PM PDT 24
Finished Apr 23 12:25:32 PM PDT 24
Peak memory 201112 kb
Host smart-3ae75b82-626b-4715-b6e1-686ae5239060
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997546291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.sram_ctrl_alert_test.1997546291
Directory /workspace/47.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sram_ctrl_bijection.3815551903
Short name T614
Test name
Test status
Simulation time 721584471 ps
CPU time 43.2 seconds
Started Apr 23 12:25:42 PM PDT 24
Finished Apr 23 12:26:26 PM PDT 24
Peak memory 201916 kb
Host smart-2a90c458-6cb4-420a-95bb-f85f0668b64c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815551903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection
.3815551903
Directory /workspace/47.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/47.sram_ctrl_executable.3610085894
Short name T493
Test name
Test status
Simulation time 12749252448 ps
CPU time 26.44 seconds
Started Apr 23 12:25:34 PM PDT 24
Finished Apr 23 12:26:02 PM PDT 24
Peak memory 202020 kb
Host smart-0b7869e9-5680-4e6a-a196-96b5b86d361d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610085894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executab
le.3610085894
Directory /workspace/47.sram_ctrl_executable/latest

Test location /workspace/coverage/default/47.sram_ctrl_lc_escalation.3788813645
Short name T140
Test name
Test status
Simulation time 371259070 ps
CPU time 5.81 seconds
Started Apr 23 12:25:38 PM PDT 24
Finished Apr 23 12:25:45 PM PDT 24
Peak memory 201936 kb
Host smart-27843be1-4df5-43e4-8a23-4eb06d8088a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788813645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_es
calation.3788813645
Directory /workspace/47.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/47.sram_ctrl_max_throughput.3323459460
Short name T730
Test name
Test status
Simulation time 245951314 ps
CPU time 92.77 seconds
Started Apr 23 12:25:39 PM PDT 24
Finished Apr 23 12:27:13 PM PDT 24
Peak memory 346488 kb
Host smart-785b4d1a-c9ec-4651-97a6-5f90215151bd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323459460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.sram_ctrl_max_throughput.3323459460
Directory /workspace/47.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_partial_access.3548975568
Short name T825
Test name
Test status
Simulation time 2168187131 ps
CPU time 5.12 seconds
Started Apr 23 12:25:27 PM PDT 24
Finished Apr 23 12:25:34 PM PDT 24
Peak memory 210180 kb
Host smart-421275ce-4cfc-476c-ab6e-3cb670c492b5
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548975568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.sram_ctrl_mem_partial_access.3548975568
Directory /workspace/47.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_walk.46921984
Short name T400
Test name
Test status
Simulation time 895011494 ps
CPU time 8.8 seconds
Started Apr 23 12:25:43 PM PDT 24
Finished Apr 23 12:25:53 PM PDT 24
Peak memory 201780 kb
Host smart-04261578-e3c5-4570-ae3c-377ab351df74
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46921984 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr
am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_
mem_walk.46921984
Directory /workspace/47.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/47.sram_ctrl_multiple_keys.615349884
Short name T478
Test name
Test status
Simulation time 54559616821 ps
CPU time 1014.44 seconds
Started Apr 23 12:25:52 PM PDT 24
Finished Apr 23 12:42:48 PM PDT 24
Peak memory 375348 kb
Host smart-abfed3c8-dbaa-4b6f-9f93-7ee48ab32c25
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615349884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multip
le_keys.615349884
Directory /workspace/47.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access.1512515483
Short name T196
Test name
Test status
Simulation time 1071286775 ps
CPU time 17.98 seconds
Started Apr 23 12:25:57 PM PDT 24
Finished Apr 23 12:26:16 PM PDT 24
Peak memory 201844 kb
Host smart-068856b3-9ad3-416d-b050-a37f07da354d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512515483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
sram_ctrl_partial_access.1512515483
Directory /workspace/47.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3511658818
Short name T625
Test name
Test status
Simulation time 116252926267 ps
CPU time 506.93 seconds
Started Apr 23 12:25:37 PM PDT 24
Finished Apr 23 12:34:05 PM PDT 24
Peak memory 201912 kb
Host smart-c43cc84d-9965-4edf-a3b6-9dc3372105b6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511658818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 47.sram_ctrl_partial_access_b2b.3511658818
Directory /workspace/47.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/47.sram_ctrl_ram_cfg.2236429561
Short name T663
Test name
Test status
Simulation time 58036055 ps
CPU time 0.82 seconds
Started Apr 23 12:25:37 PM PDT 24
Finished Apr 23 12:25:39 PM PDT 24
Peak memory 201920 kb
Host smart-6ddd49fe-bce6-4aa1-9cbf-b5d7981eeea4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236429561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.2236429561
Directory /workspace/47.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/47.sram_ctrl_regwen.2569865917
Short name T141
Test name
Test status
Simulation time 17789918218 ps
CPU time 684.66 seconds
Started Apr 23 12:25:35 PM PDT 24
Finished Apr 23 12:37:01 PM PDT 24
Peak memory 373324 kb
Host smart-8b8ec4aa-c154-49f7-b5b5-600aa93265e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569865917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.2569865917
Directory /workspace/47.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/47.sram_ctrl_smoke.468969975
Short name T926
Test name
Test status
Simulation time 1245795013 ps
CPU time 24.02 seconds
Started Apr 23 12:25:29 PM PDT 24
Finished Apr 23 12:25:54 PM PDT 24
Peak memory 271408 kb
Host smart-62b9ed0b-54f6-4c26-a624-6b219d682225
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468969975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.468969975
Directory /workspace/47.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_all.4132106053
Short name T727
Test name
Test status
Simulation time 6859623648 ps
CPU time 1314.11 seconds
Started Apr 23 12:25:44 PM PDT 24
Finished Apr 23 12:47:39 PM PDT 24
Peak memory 373616 kb
Host smart-a21038a7-496a-4f24-859f-848b376082a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132106053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 47.sram_ctrl_stress_all.4132106053
Directory /workspace/47.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3362075473
Short name T521
Test name
Test status
Simulation time 5787978790 ps
CPU time 391.08 seconds
Started Apr 23 12:25:39 PM PDT 24
Finished Apr 23 12:32:11 PM PDT 24
Peak memory 372752 kb
Host smart-0baf5ed0-3013-4e28-8ab0-0b208424ecf0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3362075473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.3362075473
Directory /workspace/47.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_pipeline.2631020223
Short name T237
Test name
Test status
Simulation time 1439326669 ps
CPU time 126.47 seconds
Started Apr 23 12:25:42 PM PDT 24
Finished Apr 23 12:27:50 PM PDT 24
Peak memory 201848 kb
Host smart-4b564ad6-28bc-4278-8e0e-99446af0857a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631020223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.sram_ctrl_stress_pipeline.2631020223
Directory /workspace/47.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.338953015
Short name T207
Test name
Test status
Simulation time 142770539 ps
CPU time 145.18 seconds
Started Apr 23 12:25:34 PM PDT 24
Finished Apr 23 12:28:00 PM PDT 24
Peak memory 353108 kb
Host smart-f58d7131-44c7-4c1e-b076-77c643d6a612
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338953015 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.sram_ctrl_throughput_w_partial_write.338953015
Directory /workspace/47.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/48.sram_ctrl_access_during_key_req.3091741513
Short name T291
Test name
Test status
Simulation time 1579032394 ps
CPU time 329.37 seconds
Started Apr 23 12:25:41 PM PDT 24
Finished Apr 23 12:31:12 PM PDT 24
Peak memory 371296 kb
Host smart-8d1c7302-f59a-4fec-ad41-617576c9730a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091741513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.sram_ctrl_access_during_key_req.3091741513
Directory /workspace/48.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/48.sram_ctrl_alert_test.907886326
Short name T891
Test name
Test status
Simulation time 13077736 ps
CPU time 0.64 seconds
Started Apr 23 12:25:32 PM PDT 24
Finished Apr 23 12:25:34 PM PDT 24
Peak memory 201136 kb
Host smart-3043ec23-8e1e-4adf-84b1-4bee9af822cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907886326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.sram_ctrl_alert_test.907886326
Directory /workspace/48.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sram_ctrl_bijection.777190140
Short name T798
Test name
Test status
Simulation time 1050173966 ps
CPU time 66.5 seconds
Started Apr 23 12:25:28 PM PDT 24
Finished Apr 23 12:26:35 PM PDT 24
Peak memory 201900 kb
Host smart-70b33313-ea5e-4d0f-bd1c-8cea151e19e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777190140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection.
777190140
Directory /workspace/48.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/48.sram_ctrl_executable.2172209169
Short name T480
Test name
Test status
Simulation time 13700901303 ps
CPU time 662.97 seconds
Started Apr 23 12:25:44 PM PDT 24
Finished Apr 23 12:36:48 PM PDT 24
Peak memory 373748 kb
Host smart-d8868d72-bf72-4f96-8415-0463c12f46ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172209169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executab
le.2172209169
Directory /workspace/48.sram_ctrl_executable/latest

Test location /workspace/coverage/default/48.sram_ctrl_lc_escalation.2792867109
Short name T835
Test name
Test status
Simulation time 677857070 ps
CPU time 9.52 seconds
Started Apr 23 12:25:46 PM PDT 24
Finished Apr 23 12:25:56 PM PDT 24
Peak memory 201904 kb
Host smart-62bdd00d-c7fe-433d-b590-301d24626ff6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792867109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_es
calation.2792867109
Directory /workspace/48.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/48.sram_ctrl_max_throughput.2082462340
Short name T579
Test name
Test status
Simulation time 40958359 ps
CPU time 2.11 seconds
Started Apr 23 12:25:32 PM PDT 24
Finished Apr 23 12:25:36 PM PDT 24
Peak memory 215240 kb
Host smart-6c39f918-ebc2-4eca-b673-5ecebd5ad8c0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082462340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.sram_ctrl_max_throughput.2082462340
Directory /workspace/48.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_partial_access.2868191965
Short name T880
Test name
Test status
Simulation time 289856387 ps
CPU time 2.74 seconds
Started Apr 23 12:25:40 PM PDT 24
Finished Apr 23 12:25:44 PM PDT 24
Peak memory 210008 kb
Host smart-503f791a-24d2-4d1a-8c61-f5bff3c6cd64
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868191965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.sram_ctrl_mem_partial_access.2868191965
Directory /workspace/48.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_walk.1487902610
Short name T440
Test name
Test status
Simulation time 264022828 ps
CPU time 7.58 seconds
Started Apr 23 12:25:43 PM PDT 24
Finished Apr 23 12:25:51 PM PDT 24
Peak memory 201788 kb
Host smart-568cd7ea-4e41-40a1-849d-abb63bae0419
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487902610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctr
l_mem_walk.1487902610
Directory /workspace/48.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/48.sram_ctrl_multiple_keys.643418619
Short name T770
Test name
Test status
Simulation time 12363703014 ps
CPU time 403.59 seconds
Started Apr 23 12:25:33 PM PDT 24
Finished Apr 23 12:32:17 PM PDT 24
Peak memory 374672 kb
Host smart-7dd15d4d-47f2-45fe-9105-7a3638b59f5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643418619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multip
le_keys.643418619
Directory /workspace/48.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access.2680972283
Short name T560
Test name
Test status
Simulation time 136895238 ps
CPU time 8.91 seconds
Started Apr 23 12:25:31 PM PDT 24
Finished Apr 23 12:25:40 PM PDT 24
Peak memory 242008 kb
Host smart-3cc87859-d8b8-41b2-a71c-5428159992f4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680972283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
sram_ctrl_partial_access.2680972283
Directory /workspace/48.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1931096113
Short name T494
Test name
Test status
Simulation time 8029468984 ps
CPU time 187.79 seconds
Started Apr 23 12:25:30 PM PDT 24
Finished Apr 23 12:28:38 PM PDT 24
Peak memory 201936 kb
Host smart-8ba80a27-18c9-41a3-a1b7-349672dfce6f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931096113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 48.sram_ctrl_partial_access_b2b.1931096113
Directory /workspace/48.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/48.sram_ctrl_ram_cfg.2624081821
Short name T832
Test name
Test status
Simulation time 88703387 ps
CPU time 0.74 seconds
Started Apr 23 12:25:32 PM PDT 24
Finished Apr 23 12:25:33 PM PDT 24
Peak memory 201912 kb
Host smart-68dfda46-1650-4b47-ba6e-3b9191081c5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624081821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.2624081821
Directory /workspace/48.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/48.sram_ctrl_regwen.1668001669
Short name T595
Test name
Test status
Simulation time 3501553419 ps
CPU time 627.38 seconds
Started Apr 23 12:25:41 PM PDT 24
Finished Apr 23 12:36:09 PM PDT 24
Peak memory 373668 kb
Host smart-67bdc7d3-7893-4348-9ca3-837100d88f1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668001669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.1668001669
Directory /workspace/48.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/48.sram_ctrl_smoke.734891352
Short name T365
Test name
Test status
Simulation time 553014256 ps
CPU time 10.28 seconds
Started Apr 23 12:25:26 PM PDT 24
Finished Apr 23 12:25:38 PM PDT 24
Peak memory 201904 kb
Host smart-f7d2f6ce-059f-4697-b5af-1c1d58f7c153
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734891352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.734891352
Directory /workspace/48.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_all.2377659959
Short name T709
Test name
Test status
Simulation time 8792614639 ps
CPU time 2155.24 seconds
Started Apr 23 12:25:41 PM PDT 24
Finished Apr 23 01:01:37 PM PDT 24
Peak memory 373772 kb
Host smart-256a67ea-7116-4fb4-88ec-b635f6b61f59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377659959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 48.sram_ctrl_stress_all.2377659959
Directory /workspace/48.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.235281676
Short name T790
Test name
Test status
Simulation time 4681420310 ps
CPU time 85 seconds
Started Apr 23 12:25:32 PM PDT 24
Finished Apr 23 12:26:57 PM PDT 24
Peak memory 259996 kb
Host smart-1d8e5900-9a38-4f69-8af8-51a06cf99c3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=235281676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.235281676
Directory /workspace/48.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_pipeline.2910496964
Short name T512
Test name
Test status
Simulation time 50685284810 ps
CPU time 293.34 seconds
Started Apr 23 12:25:42 PM PDT 24
Finished Apr 23 12:30:36 PM PDT 24
Peak memory 201892 kb
Host smart-fa001fb1-2294-404e-97bb-d1500c1923f1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910496964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.sram_ctrl_stress_pipeline.2910496964
Directory /workspace/48.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3248595521
Short name T714
Test name
Test status
Simulation time 797969405 ps
CPU time 102.52 seconds
Started Apr 23 12:25:31 PM PDT 24
Finished Apr 23 12:27:14 PM PDT 24
Peak memory 353228 kb
Host smart-662cf690-7d97-4f2a-8c84-f78d0f4f0acf
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248595521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.sram_ctrl_throughput_w_partial_write.3248595521
Directory /workspace/48.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/49.sram_ctrl_access_during_key_req.3831495900
Short name T786
Test name
Test status
Simulation time 3211199035 ps
CPU time 157.91 seconds
Started Apr 23 12:25:39 PM PDT 24
Finished Apr 23 12:28:18 PM PDT 24
Peak memory 305484 kb
Host smart-ec676afe-8148-4f50-aaae-26640ea33d31
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831495900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.sram_ctrl_access_during_key_req.3831495900
Directory /workspace/49.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/49.sram_ctrl_alert_test.3671561208
Short name T777
Test name
Test status
Simulation time 19091423 ps
CPU time 0.64 seconds
Started Apr 23 12:25:35 PM PDT 24
Finished Apr 23 12:25:37 PM PDT 24
Peak memory 200952 kb
Host smart-f5df5a76-f35a-47ef-b557-0a347eabb637
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671561208 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.sram_ctrl_alert_test.3671561208
Directory /workspace/49.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sram_ctrl_bijection.2467879698
Short name T136
Test name
Test status
Simulation time 14121641936 ps
CPU time 50.37 seconds
Started Apr 23 12:25:41 PM PDT 24
Finished Apr 23 12:26:32 PM PDT 24
Peak memory 201904 kb
Host smart-6f4af5d6-74e7-4361-ab31-cf58f06a59a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467879698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection
.2467879698
Directory /workspace/49.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/49.sram_ctrl_executable.1332955450
Short name T847
Test name
Test status
Simulation time 64254736360 ps
CPU time 1022.99 seconds
Started Apr 23 12:25:47 PM PDT 24
Finished Apr 23 12:42:50 PM PDT 24
Peak memory 373752 kb
Host smart-0af39d6c-bee9-407e-b266-cebe46d5644c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332955450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executab
le.1332955450
Directory /workspace/49.sram_ctrl_executable/latest

Test location /workspace/coverage/default/49.sram_ctrl_lc_escalation.2000135253
Short name T498
Test name
Test status
Simulation time 203520242 ps
CPU time 2.96 seconds
Started Apr 23 12:25:38 PM PDT 24
Finished Apr 23 12:25:42 PM PDT 24
Peak memory 201928 kb
Host smart-45d32632-d8d6-4e86-84ec-e1de919f7cc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000135253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_es
calation.2000135253
Directory /workspace/49.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/49.sram_ctrl_max_throughput.1733583414
Short name T556
Test name
Test status
Simulation time 159478207 ps
CPU time 0.91 seconds
Started Apr 23 12:25:46 PM PDT 24
Finished Apr 23 12:25:48 PM PDT 24
Peak memory 201596 kb
Host smart-e022c5b5-7a85-412c-9093-a774fdfcdbd7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733583414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 49.sram_ctrl_max_throughput.1733583414
Directory /workspace/49.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_partial_access.3648240269
Short name T190
Test name
Test status
Simulation time 174581186 ps
CPU time 3.09 seconds
Started Apr 23 12:25:41 PM PDT 24
Finished Apr 23 12:25:45 PM PDT 24
Peak memory 210000 kb
Host smart-532a0cc5-f807-41bf-b599-38826baf383f
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648240269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.sram_ctrl_mem_partial_access.3648240269
Directory /workspace/49.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_walk.181122459
Short name T867
Test name
Test status
Simulation time 1480614623 ps
CPU time 5.32 seconds
Started Apr 23 12:25:41 PM PDT 24
Finished Apr 23 12:25:48 PM PDT 24
Peak memory 201788 kb
Host smart-db84fd3f-7cd6-4815-a6d5-1706de681b5e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181122459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl
_mem_walk.181122459
Directory /workspace/49.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/49.sram_ctrl_multiple_keys.681206251
Short name T332
Test name
Test status
Simulation time 45577792065 ps
CPU time 826.87 seconds
Started Apr 23 12:25:32 PM PDT 24
Finished Apr 23 12:39:20 PM PDT 24
Peak memory 364608 kb
Host smart-51a7f73f-0a87-4d2e-89ea-3f6faa445512
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681206251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multip
le_keys.681206251
Directory /workspace/49.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access.1797406781
Short name T601
Test name
Test status
Simulation time 273088468 ps
CPU time 13.27 seconds
Started Apr 23 12:25:40 PM PDT 24
Finished Apr 23 12:25:54 PM PDT 24
Peak memory 201840 kb
Host smart-6be39f9c-9694-4b58-b4b4-f11ca0cf0718
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797406781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
sram_ctrl_partial_access.1797406781
Directory /workspace/49.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.787229181
Short name T734
Test name
Test status
Simulation time 8700388047 ps
CPU time 302.2 seconds
Started Apr 23 12:25:41 PM PDT 24
Finished Apr 23 12:30:44 PM PDT 24
Peak memory 201920 kb
Host smart-b3055efd-f56f-492f-b8c4-c171b1dec6fb
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787229181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.sram_ctrl_partial_access_b2b.787229181
Directory /workspace/49.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/49.sram_ctrl_ram_cfg.3076241880
Short name T7
Test name
Test status
Simulation time 59811949 ps
CPU time 0.79 seconds
Started Apr 23 12:25:37 PM PDT 24
Finished Apr 23 12:25:39 PM PDT 24
Peak memory 202000 kb
Host smart-ae1648f7-f636-465b-a6fd-b28aeaea0c05
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076241880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.3076241880
Directory /workspace/49.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/49.sram_ctrl_regwen.543105266
Short name T206
Test name
Test status
Simulation time 42018219918 ps
CPU time 688.1 seconds
Started Apr 23 12:25:36 PM PDT 24
Finished Apr 23 12:37:05 PM PDT 24
Peak memory 364348 kb
Host smart-babccd36-258a-43d8-be83-c1a2186dcf71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543105266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.543105266
Directory /workspace/49.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/49.sram_ctrl_smoke.4063217062
Short name T198
Test name
Test status
Simulation time 99462201 ps
CPU time 2.38 seconds
Started Apr 23 12:25:32 PM PDT 24
Finished Apr 23 12:25:36 PM PDT 24
Peak memory 206036 kb
Host smart-91703e24-f127-49c7-92c3-7a9811342215
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063217062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.4063217062
Directory /workspace/49.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_all.664790204
Short name T736
Test name
Test status
Simulation time 173656978797 ps
CPU time 4906.55 seconds
Started Apr 23 12:25:41 PM PDT 24
Finished Apr 23 01:47:29 PM PDT 24
Peak memory 374232 kb
Host smart-2e4f86ee-2351-4b69-b8d0-b3d636b5cf4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664790204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 49.sram_ctrl_stress_all.664790204
Directory /workspace/49.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3034800953
Short name T865
Test name
Test status
Simulation time 313564268 ps
CPU time 50.73 seconds
Started Apr 23 12:25:46 PM PDT 24
Finished Apr 23 12:26:37 PM PDT 24
Peak memory 303772 kb
Host smart-540be064-31ac-43d4-80e8-658d75ba1131
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3034800953 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.3034800953
Directory /workspace/49.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_pipeline.215193936
Short name T571
Test name
Test status
Simulation time 35565893016 ps
CPU time 233.07 seconds
Started Apr 23 12:25:53 PM PDT 24
Finished Apr 23 12:29:47 PM PDT 24
Peak memory 201976 kb
Host smart-f4b1570d-4cfb-415b-a44a-ec788fd556cc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215193936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.sram_ctrl_stress_pipeline.215193936
Directory /workspace/49.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.717951463
Short name T853
Test name
Test status
Simulation time 431758180 ps
CPU time 78.77 seconds
Started Apr 23 12:25:40 PM PDT 24
Finished Apr 23 12:26:59 PM PDT 24
Peak memory 333908 kb
Host smart-dfda4a85-50c1-4453-a8e6-56f8c839559c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717951463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 49.sram_ctrl_throughput_w_partial_write.717951463
Directory /workspace/49.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/5.sram_ctrl_access_during_key_req.2405708464
Short name T950
Test name
Test status
Simulation time 2932196288 ps
CPU time 594.38 seconds
Started Apr 23 12:23:25 PM PDT 24
Finished Apr 23 12:33:20 PM PDT 24
Peak memory 359320 kb
Host smart-bfa3525c-9e68-4834-bb14-9080cae045fe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405708464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.sram_ctrl_access_during_key_req.2405708464
Directory /workspace/5.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/5.sram_ctrl_alert_test.3244272440
Short name T902
Test name
Test status
Simulation time 21683257 ps
CPU time 0.67 seconds
Started Apr 23 12:23:27 PM PDT 24
Finished Apr 23 12:23:28 PM PDT 24
Peak memory 201140 kb
Host smart-d966a42c-cae8-4558-bcbe-be9a46eb8ac3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244272440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.sram_ctrl_alert_test.3244272440
Directory /workspace/5.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sram_ctrl_bijection.990095903
Short name T295
Test name
Test status
Simulation time 476927885 ps
CPU time 13.41 seconds
Started Apr 23 12:23:19 PM PDT 24
Finished Apr 23 12:23:33 PM PDT 24
Peak memory 201860 kb
Host smart-f541b854-802e-4522-9e19-9512cf8a7738
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990095903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.990095903
Directory /workspace/5.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/5.sram_ctrl_executable.3369651227
Short name T199
Test name
Test status
Simulation time 19571126701 ps
CPU time 975.67 seconds
Started Apr 23 12:23:23 PM PDT 24
Finished Apr 23 12:39:40 PM PDT 24
Peak memory 362316 kb
Host smart-87d6c5da-defd-4ef3-8110-e1fcd28973ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369651227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executabl
e.3369651227
Directory /workspace/5.sram_ctrl_executable/latest

Test location /workspace/coverage/default/5.sram_ctrl_lc_escalation.4264886429
Short name T245
Test name
Test status
Simulation time 1173454364 ps
CPU time 2.67 seconds
Started Apr 23 12:23:23 PM PDT 24
Finished Apr 23 12:23:27 PM PDT 24
Peak memory 201568 kb
Host smart-635ec09e-6a8a-4aa3-9e9f-2b9e42bf4724
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264886429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_esc
alation.4264886429
Directory /workspace/5.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/5.sram_ctrl_max_throughput.1556496533
Short name T831
Test name
Test status
Simulation time 767246802 ps
CPU time 10.12 seconds
Started Apr 23 12:23:23 PM PDT 24
Finished Apr 23 12:23:34 PM PDT 24
Peak memory 237904 kb
Host smart-65d7cc0c-b7bb-4807-a968-14daa8ab2175
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556496533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.sram_ctrl_max_throughput.1556496533
Directory /workspace/5.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_partial_access.3398597321
Short name T320
Test name
Test status
Simulation time 191144289 ps
CPU time 3.11 seconds
Started Apr 23 12:23:30 PM PDT 24
Finished Apr 23 12:23:35 PM PDT 24
Peak memory 210040 kb
Host smart-20c519fe-2620-49f6-b065-44bd7ccaeea1
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398597321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.sram_ctrl_mem_partial_access.3398597321
Directory /workspace/5.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_walk.3370045726
Short name T458
Test name
Test status
Simulation time 681848899 ps
CPU time 10.59 seconds
Started Apr 23 12:23:25 PM PDT 24
Finished Apr 23 12:23:37 PM PDT 24
Peak memory 201748 kb
Host smart-caba433e-d5d3-4db8-b68b-5f1692b8eb82
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370045726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl
_mem_walk.3370045726
Directory /workspace/5.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/5.sram_ctrl_multiple_keys.1828778577
Short name T743
Test name
Test status
Simulation time 7582854049 ps
CPU time 407.22 seconds
Started Apr 23 12:23:19 PM PDT 24
Finished Apr 23 12:30:06 PM PDT 24
Peak memory 355892 kb
Host smart-b089ae10-3f1d-4ad6-8c76-a15dc68e50bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828778577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multip
le_keys.1828778577
Directory /workspace/5.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access.2999514715
Short name T361
Test name
Test status
Simulation time 247125556 ps
CPU time 2.35 seconds
Started Apr 23 12:23:23 PM PDT 24
Finished Apr 23 12:23:27 PM PDT 24
Peak memory 201904 kb
Host smart-7e8e4c2e-0d8c-424c-a94b-d41c9fb17c97
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999514715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.s
ram_ctrl_partial_access.2999514715
Directory /workspace/5.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.915578652
Short name T88
Test name
Test status
Simulation time 10013031046 ps
CPU time 372.62 seconds
Started Apr 23 12:23:22 PM PDT 24
Finished Apr 23 12:29:36 PM PDT 24
Peak memory 202120 kb
Host smart-fa46da4c-e9ae-4edf-be8b-b99b9619a699
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915578652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.sram_ctrl_partial_access_b2b.915578652
Directory /workspace/5.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/5.sram_ctrl_ram_cfg.169480128
Short name T176
Test name
Test status
Simulation time 50188657 ps
CPU time 0.79 seconds
Started Apr 23 12:23:23 PM PDT 24
Finished Apr 23 12:23:25 PM PDT 24
Peak memory 202036 kb
Host smart-3e3faca4-17e0-4400-aa41-fdf3e95e29e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169480128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.169480128
Directory /workspace/5.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/5.sram_ctrl_regwen.3777760186
Short name T481
Test name
Test status
Simulation time 8096712737 ps
CPU time 786.03 seconds
Started Apr 23 12:23:23 PM PDT 24
Finished Apr 23 12:36:31 PM PDT 24
Peak memory 373504 kb
Host smart-3267a666-979d-4db9-9c6a-88a27ee8bdfd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777760186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.3777760186
Directory /workspace/5.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/5.sram_ctrl_smoke.3836439048
Short name T281
Test name
Test status
Simulation time 70747942 ps
CPU time 1.09 seconds
Started Apr 23 12:23:14 PM PDT 24
Finished Apr 23 12:23:15 PM PDT 24
Peak memory 201732 kb
Host smart-c1120ada-61d4-4699-b524-408df42282ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836439048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.3836439048
Directory /workspace/5.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_all.731717727
Short name T744
Test name
Test status
Simulation time 33450375387 ps
CPU time 1530.84 seconds
Started Apr 23 12:23:30 PM PDT 24
Finished Apr 23 12:49:03 PM PDT 24
Peak memory 374212 kb
Host smart-83511eed-36a2-4f39-b95b-51fcc7ad2722
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731717727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 5.sram_ctrl_stress_all.731717727
Directory /workspace/5.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2212373922
Short name T882
Test name
Test status
Simulation time 4324640467 ps
CPU time 94.24 seconds
Started Apr 23 12:23:23 PM PDT 24
Finished Apr 23 12:24:59 PM PDT 24
Peak memory 327040 kb
Host smart-5cf338ff-faaf-4a9d-adb9-3140a96b3244
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2212373922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.2212373922
Directory /workspace/5.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_pipeline.3723250846
Short name T528
Test name
Test status
Simulation time 7036829307 ps
CPU time 283.72 seconds
Started Apr 23 12:23:23 PM PDT 24
Finished Apr 23 12:28:08 PM PDT 24
Peak memory 201984 kb
Host smart-f9ad9982-ae3a-44d6-a5a5-bdffef82120d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723250846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.sram_ctrl_stress_pipeline.3723250846
Directory /workspace/5.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2012823813
Short name T270
Test name
Test status
Simulation time 192422953 ps
CPU time 4.03 seconds
Started Apr 23 12:23:19 PM PDT 24
Finished Apr 23 12:23:24 PM PDT 24
Peak memory 221508 kb
Host smart-95e719ce-27ef-493b-a857-a02ac825b986
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012823813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.sram_ctrl_throughput_w_partial_write.2012823813
Directory /workspace/5.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/6.sram_ctrl_access_during_key_req.1169420834
Short name T191
Test name
Test status
Simulation time 31981787460 ps
CPU time 1144.3 seconds
Started Apr 23 12:23:36 PM PDT 24
Finished Apr 23 12:42:41 PM PDT 24
Peak memory 371672 kb
Host smart-cc4bca20-165b-4833-b0f1-f509480096ca
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169420834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.sram_ctrl_access_during_key_req.1169420834
Directory /workspace/6.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/6.sram_ctrl_alert_test.4110641609
Short name T664
Test name
Test status
Simulation time 52626857 ps
CPU time 0.63 seconds
Started Apr 23 12:23:47 PM PDT 24
Finished Apr 23 12:23:49 PM PDT 24
Peak memory 200908 kb
Host smart-3596098e-af0c-495a-b814-c619fd761b7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110641609 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.sram_ctrl_alert_test.4110641609
Directory /workspace/6.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sram_ctrl_bijection.3774601203
Short name T659
Test name
Test status
Simulation time 1780768988 ps
CPU time 39.2 seconds
Started Apr 23 12:23:35 PM PDT 24
Finished Apr 23 12:24:14 PM PDT 24
Peak memory 202024 kb
Host smart-8e506d45-e2c2-48b2-bf51-201ed46ef37a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774601203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.
3774601203
Directory /workspace/6.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/6.sram_ctrl_executable.1311297615
Short name T152
Test name
Test status
Simulation time 56683607740 ps
CPU time 581.49 seconds
Started Apr 23 12:23:35 PM PDT 24
Finished Apr 23 12:33:17 PM PDT 24
Peak memory 351248 kb
Host smart-cdfa4fef-cee5-418a-8cec-1914b9690aa8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311297615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executabl
e.1311297615
Directory /workspace/6.sram_ctrl_executable/latest

Test location /workspace/coverage/default/6.sram_ctrl_lc_escalation.1803494119
Short name T943
Test name
Test status
Simulation time 3743830368 ps
CPU time 5.2 seconds
Started Apr 23 12:23:31 PM PDT 24
Finished Apr 23 12:23:37 PM PDT 24
Peak memory 202024 kb
Host smart-fe1548a1-d1f0-4bc1-9e5c-df16d02698df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803494119 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_esc
alation.1803494119
Directory /workspace/6.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/6.sram_ctrl_max_throughput.3412136554
Short name T457
Test name
Test status
Simulation time 81805929 ps
CPU time 26.62 seconds
Started Apr 23 12:23:29 PM PDT 24
Finished Apr 23 12:23:56 PM PDT 24
Peak memory 283600 kb
Host smart-527c6538-cf3e-4443-9e86-bd9003c71fe2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412136554 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.sram_ctrl_max_throughput.3412136554
Directory /workspace/6.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_partial_access.1121496186
Short name T851
Test name
Test status
Simulation time 695644841 ps
CPU time 4.99 seconds
Started Apr 23 12:23:41 PM PDT 24
Finished Apr 23 12:23:47 PM PDT 24
Peak memory 210056 kb
Host smart-4a98f688-ff1a-4299-a8bb-465cabe3861f
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121496186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.sram_ctrl_mem_partial_access.1121496186
Directory /workspace/6.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_walk.87464028
Short name T29
Test name
Test status
Simulation time 233348461 ps
CPU time 5.02 seconds
Started Apr 23 12:23:36 PM PDT 24
Finished Apr 23 12:23:42 PM PDT 24
Peak memory 201920 kb
Host smart-d0371168-0c8d-45d9-ba63-87c8acb5fb3b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87464028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr
am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_m
em_walk.87464028
Directory /workspace/6.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/6.sram_ctrl_multiple_keys.104657019
Short name T106
Test name
Test status
Simulation time 9113027516 ps
CPU time 297.39 seconds
Started Apr 23 12:23:30 PM PDT 24
Finished Apr 23 12:28:29 PM PDT 24
Peak memory 367548 kb
Host smart-bb4801e3-f4c9-43ff-bb4c-b016527dd732
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104657019 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multipl
e_keys.104657019
Directory /workspace/6.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access.757020576
Short name T162
Test name
Test status
Simulation time 48740391 ps
CPU time 0.87 seconds
Started Apr 23 12:23:34 PM PDT 24
Finished Apr 23 12:23:35 PM PDT 24
Peak memory 201796 kb
Host smart-f672a86e-bdbe-4909-81f4-92436cdd189c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757020576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sr
am_ctrl_partial_access.757020576
Directory /workspace/6.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2967936519
Short name T533
Test name
Test status
Simulation time 55746855707 ps
CPU time 309.19 seconds
Started Apr 23 12:23:30 PM PDT 24
Finished Apr 23 12:28:40 PM PDT 24
Peak memory 201936 kb
Host smart-9a30d396-d1f9-4cac-badc-4b8fce84c0ca
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967936519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 6.sram_ctrl_partial_access_b2b.2967936519
Directory /workspace/6.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/6.sram_ctrl_ram_cfg.3212743993
Short name T563
Test name
Test status
Simulation time 28940641 ps
CPU time 0.76 seconds
Started Apr 23 12:23:34 PM PDT 24
Finished Apr 23 12:23:35 PM PDT 24
Peak memory 201924 kb
Host smart-f92b172f-9757-41a5-8536-36e694b9c025
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212743993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.3212743993
Directory /workspace/6.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/6.sram_ctrl_regwen.1475540146
Short name T442
Test name
Test status
Simulation time 10853180025 ps
CPU time 1583.72 seconds
Started Apr 23 12:23:34 PM PDT 24
Finished Apr 23 12:49:58 PM PDT 24
Peak memory 373700 kb
Host smart-13bd4a74-b7e8-4453-900c-dad9b22f032b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475540146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.1475540146
Directory /workspace/6.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/6.sram_ctrl_smoke.4130287623
Short name T898
Test name
Test status
Simulation time 149749161 ps
CPU time 48.18 seconds
Started Apr 23 12:23:25 PM PDT 24
Finished Apr 23 12:24:14 PM PDT 24
Peak memory 317104 kb
Host smart-55e346b0-394a-4f8a-913a-f70aef12e26f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130287623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.4130287623
Directory /workspace/6.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_all.1665880445
Short name T436
Test name
Test status
Simulation time 19432338944 ps
CPU time 439.55 seconds
Started Apr 23 12:23:44 PM PDT 24
Finished Apr 23 12:31:04 PM PDT 24
Peak memory 372168 kb
Host smart-e5954663-3bab-4049-b79f-59f2a8261908
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665880445 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 6.sram_ctrl_stress_all.1665880445
Directory /workspace/6.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1373963411
Short name T696
Test name
Test status
Simulation time 446497329 ps
CPU time 38.86 seconds
Started Apr 23 12:23:41 PM PDT 24
Finished Apr 23 12:24:21 PM PDT 24
Peak memory 256076 kb
Host smart-1bb57928-eaee-4c9b-b5a8-f85a11e85863
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1373963411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.1373963411
Directory /workspace/6.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_pipeline.3825607621
Short name T910
Test name
Test status
Simulation time 11840729696 ps
CPU time 257.82 seconds
Started Apr 23 12:23:30 PM PDT 24
Finished Apr 23 12:27:49 PM PDT 24
Peak memory 202004 kb
Host smart-810ee6b5-431e-49d7-9879-7aea74e887ca
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825607621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.sram_ctrl_stress_pipeline.3825607621
Directory /workspace/6.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1830559137
Short name T11
Test name
Test status
Simulation time 226294875 ps
CPU time 4.4 seconds
Started Apr 23 12:23:33 PM PDT 24
Finished Apr 23 12:23:38 PM PDT 24
Peak memory 223656 kb
Host smart-5a29f231-ead1-4cb0-b9e3-ee1dfd1773a5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830559137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.sram_ctrl_throughput_w_partial_write.1830559137
Directory /workspace/6.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/7.sram_ctrl_access_during_key_req.2816764804
Short name T218
Test name
Test status
Simulation time 3316303669 ps
CPU time 873.44 seconds
Started Apr 23 12:23:46 PM PDT 24
Finished Apr 23 12:38:21 PM PDT 24
Peak memory 373680 kb
Host smart-54fdd15c-4864-46ee-85fe-0608e0e60def
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816764804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.sram_ctrl_access_during_key_req.2816764804
Directory /workspace/7.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/7.sram_ctrl_alert_test.31180455
Short name T741
Test name
Test status
Simulation time 25008413 ps
CPU time 0.62 seconds
Started Apr 23 12:23:43 PM PDT 24
Finished Apr 23 12:23:45 PM PDT 24
Peak memory 201084 kb
Host smart-3552366c-027f-4e9f-b3f3-206147901abd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31180455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.sram_ctrl_alert_test.31180455
Directory /workspace/7.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sram_ctrl_bijection.2923869822
Short name T406
Test name
Test status
Simulation time 4155517390 ps
CPU time 25.05 seconds
Started Apr 23 12:23:48 PM PDT 24
Finished Apr 23 12:24:14 PM PDT 24
Peak memory 201928 kb
Host smart-cdc440d3-7e66-4d3f-a6f7-dcdc2e14b923
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923869822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.
2923869822
Directory /workspace/7.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/7.sram_ctrl_executable.1495332959
Short name T469
Test name
Test status
Simulation time 10289713505 ps
CPU time 1115.6 seconds
Started Apr 23 12:23:46 PM PDT 24
Finished Apr 23 12:42:22 PM PDT 24
Peak memory 365148 kb
Host smart-09b84b93-830b-487c-a425-21e018c9b263
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495332959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executabl
e.1495332959
Directory /workspace/7.sram_ctrl_executable/latest

Test location /workspace/coverage/default/7.sram_ctrl_lc_escalation.2677820940
Short name T616
Test name
Test status
Simulation time 2528218632 ps
CPU time 4.34 seconds
Started Apr 23 12:23:47 PM PDT 24
Finished Apr 23 12:23:52 PM PDT 24
Peak memory 201944 kb
Host smart-12075bfb-09e2-4a19-a8c2-1de1d8558553
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677820940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_esc
alation.2677820940
Directory /workspace/7.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/7.sram_ctrl_max_throughput.2200147487
Short name T389
Test name
Test status
Simulation time 165410542 ps
CPU time 2.22 seconds
Started Apr 23 12:23:41 PM PDT 24
Finished Apr 23 12:23:44 PM PDT 24
Peak memory 215324 kb
Host smart-a0162ba6-9f4a-4657-8fea-b81632e3f0ae
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200147487 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.sram_ctrl_max_throughput.2200147487
Directory /workspace/7.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_partial_access.37289323
Short name T340
Test name
Test status
Simulation time 160046081 ps
CPU time 4.88 seconds
Started Apr 23 12:23:44 PM PDT 24
Finished Apr 23 12:23:50 PM PDT 24
Peak memory 210020 kb
Host smart-92631be4-5a8f-4bfa-8dbf-4c334bef4299
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37289323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.s
ram_ctrl_mem_partial_access.37289323
Directory /workspace/7.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_walk.1208753087
Short name T754
Test name
Test status
Simulation time 885269615 ps
CPU time 9.45 seconds
Started Apr 23 12:23:39 PM PDT 24
Finished Apr 23 12:23:50 PM PDT 24
Peak memory 201748 kb
Host smart-aec0a5ff-a9a7-4014-a50e-770f0e7d2d3f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208753087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl
_mem_walk.1208753087
Directory /workspace/7.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/7.sram_ctrl_multiple_keys.2270172576
Short name T791
Test name
Test status
Simulation time 13136139783 ps
CPU time 1020.39 seconds
Started Apr 23 12:23:46 PM PDT 24
Finished Apr 23 12:40:48 PM PDT 24
Peak memory 371728 kb
Host smart-13a89696-3cf1-4bb8-9846-2811e6d6dcf0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270172576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multip
le_keys.2270172576
Directory /workspace/7.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access.540870401
Short name T620
Test name
Test status
Simulation time 4022839409 ps
CPU time 56.97 seconds
Started Apr 23 12:23:42 PM PDT 24
Finished Apr 23 12:24:40 PM PDT 24
Peak memory 321388 kb
Host smart-c7363f78-43f8-49d7-920e-0b25e98ea44a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540870401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sr
am_ctrl_partial_access.540870401
Directory /workspace/7.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.4027381179
Short name T188
Test name
Test status
Simulation time 18962148677 ps
CPU time 236.06 seconds
Started Apr 23 12:23:38 PM PDT 24
Finished Apr 23 12:27:35 PM PDT 24
Peak memory 201900 kb
Host smart-a75d58dd-33c0-4209-b0f9-99c06c045cd4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027381179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 7.sram_ctrl_partial_access_b2b.4027381179
Directory /workspace/7.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/7.sram_ctrl_ram_cfg.1240224377
Short name T689
Test name
Test status
Simulation time 81194351 ps
CPU time 0.75 seconds
Started Apr 23 12:23:44 PM PDT 24
Finished Apr 23 12:23:45 PM PDT 24
Peak memory 201920 kb
Host smart-f96dd537-f2de-4ef2-b5e8-826ea4ffa12d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240224377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.1240224377
Directory /workspace/7.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/7.sram_ctrl_regwen.32325095
Short name T432
Test name
Test status
Simulation time 5089969274 ps
CPU time 1354.53 seconds
Started Apr 23 12:23:42 PM PDT 24
Finished Apr 23 12:46:18 PM PDT 24
Peak memory 370636 kb
Host smart-989b687d-0e36-4da0-bf53-09138fedcb8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32325095 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.32325095
Directory /workspace/7.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/7.sram_ctrl_smoke.3594658767
Short name T137
Test name
Test status
Simulation time 178015504 ps
CPU time 9.47 seconds
Started Apr 23 12:23:47 PM PDT 24
Finished Apr 23 12:23:57 PM PDT 24
Peak memory 201892 kb
Host smart-dfb7e074-0bdb-4084-a6b9-7621e37420e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594658767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.3594658767
Directory /workspace/7.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_all.387990834
Short name T52
Test name
Test status
Simulation time 152598794226 ps
CPU time 1578.96 seconds
Started Apr 23 12:23:58 PM PDT 24
Finished Apr 23 12:50:19 PM PDT 24
Peak memory 374716 kb
Host smart-ad2d63ce-8dad-49da-a59b-2eb8273d478d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387990834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 7.sram_ctrl_stress_all.387990834
Directory /workspace/7.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1557394158
Short name T105
Test name
Test status
Simulation time 1107570468 ps
CPU time 14.3 seconds
Started Apr 23 12:23:50 PM PDT 24
Finished Apr 23 12:24:06 PM PDT 24
Peak memory 210116 kb
Host smart-9e508f4a-3e9f-4f18-9f5b-6d8589a74dcd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1557394158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.1557394158
Directory /workspace/7.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_pipeline.1530961810
Short name T641
Test name
Test status
Simulation time 3382499518 ps
CPU time 308.43 seconds
Started Apr 23 12:23:37 PM PDT 24
Finished Apr 23 12:28:46 PM PDT 24
Peak memory 201904 kb
Host smart-fb18e3d0-7201-44e1-ad97-f7b20050f101
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530961810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.sram_ctrl_stress_pipeline.1530961810
Directory /workspace/7.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1459334157
Short name T652
Test name
Test status
Simulation time 357785375 ps
CPU time 31.36 seconds
Started Apr 23 12:23:47 PM PDT 24
Finished Apr 23 12:24:19 PM PDT 24
Peak memory 288800 kb
Host smart-4841313a-0d20-4902-a0b4-92fa589b4539
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459334157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.sram_ctrl_throughput_w_partial_write.1459334157
Directory /workspace/7.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/8.sram_ctrl_access_during_key_req.740390513
Short name T205
Test name
Test status
Simulation time 7946674486 ps
CPU time 940.64 seconds
Started Apr 23 12:23:58 PM PDT 24
Finished Apr 23 12:39:41 PM PDT 24
Peak memory 359288 kb
Host smart-3f40ff64-fd80-4c5f-94f4-22acd0006db9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740390513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 8.sram_ctrl_access_during_key_req.740390513
Directory /workspace/8.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/8.sram_ctrl_alert_test.3255432575
Short name T697
Test name
Test status
Simulation time 32218759 ps
CPU time 0.63 seconds
Started Apr 23 12:23:52 PM PDT 24
Finished Apr 23 12:23:54 PM PDT 24
Peak memory 200928 kb
Host smart-62c1e79a-27bc-4004-95a7-3e2623427384
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255432575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.sram_ctrl_alert_test.3255432575
Directory /workspace/8.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sram_ctrl_bijection.169199840
Short name T850
Test name
Test status
Simulation time 8290781926 ps
CPU time 61.09 seconds
Started Apr 23 12:23:51 PM PDT 24
Finished Apr 23 12:24:53 PM PDT 24
Peak memory 201916 kb
Host smart-a0b6869c-6290-439a-8d93-354f15e8f871
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169199840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.169199840
Directory /workspace/8.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/8.sram_ctrl_executable.1267865588
Short name T134
Test name
Test status
Simulation time 12396621197 ps
CPU time 588.97 seconds
Started Apr 23 12:23:58 PM PDT 24
Finished Apr 23 12:33:49 PM PDT 24
Peak memory 366556 kb
Host smart-a8bfb15d-2307-4aa2-9dbb-1ff9abbc0522
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267865588 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executabl
e.1267865588
Directory /workspace/8.sram_ctrl_executable/latest

Test location /workspace/coverage/default/8.sram_ctrl_lc_escalation.449609031
Short name T755
Test name
Test status
Simulation time 2940074210 ps
CPU time 5.51 seconds
Started Apr 23 12:23:59 PM PDT 24
Finished Apr 23 12:24:06 PM PDT 24
Peak memory 201904 kb
Host smart-7f566292-9aea-434f-8dde-47c8c9f01c88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449609031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esca
lation.449609031
Directory /workspace/8.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/8.sram_ctrl_max_throughput.3065431082
Short name T827
Test name
Test status
Simulation time 300386438 ps
CPU time 84.12 seconds
Started Apr 23 12:23:58 PM PDT 24
Finished Apr 23 12:25:24 PM PDT 24
Peak memory 355224 kb
Host smart-ebc23235-2fc1-4312-a09f-4691cfff7962
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065431082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.sram_ctrl_max_throughput.3065431082
Directory /workspace/8.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_partial_access.1694080341
Short name T584
Test name
Test status
Simulation time 66427209 ps
CPU time 4.45 seconds
Started Apr 23 12:23:57 PM PDT 24
Finished Apr 23 12:24:03 PM PDT 24
Peak memory 210076 kb
Host smart-1fd52e1b-2478-4742-a0f0-5cbcaed54eda
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694080341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.sram_ctrl_mem_partial_access.1694080341
Directory /workspace/8.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_walk.3969999801
Short name T384
Test name
Test status
Simulation time 686112714 ps
CPU time 10.38 seconds
Started Apr 23 12:23:48 PM PDT 24
Finished Apr 23 12:23:59 PM PDT 24
Peak memory 201760 kb
Host smart-b29717fc-8e1a-42b5-a964-a5fe4acbb6b6
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969999801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl
_mem_walk.3969999801
Directory /workspace/8.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/8.sram_ctrl_multiple_keys.2556208894
Short name T145
Test name
Test status
Simulation time 16448540954 ps
CPU time 85.15 seconds
Started Apr 23 12:23:52 PM PDT 24
Finished Apr 23 12:25:17 PM PDT 24
Peak memory 310052 kb
Host smart-af81ed90-ade3-4be6-a12a-5a56eaecd13a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556208894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multip
le_keys.2556208894
Directory /workspace/8.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access.61028046
Short name T822
Test name
Test status
Simulation time 1278193053 ps
CPU time 4.72 seconds
Started Apr 23 12:23:58 PM PDT 24
Finished Apr 23 12:24:05 PM PDT 24
Peak memory 201804 kb
Host smart-26922cad-0482-45a7-99f1-05b688a8a024
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61028046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sra
m_ctrl_partial_access.61028046
Directory /workspace/8.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.3934462686
Short name T541
Test name
Test status
Simulation time 17650911506 ps
CPU time 384.02 seconds
Started Apr 23 12:23:46 PM PDT 24
Finished Apr 23 12:30:11 PM PDT 24
Peak memory 201904 kb
Host smart-fb521ec5-962b-4379-8ff6-6b6e52c8e33f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934462686 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 8.sram_ctrl_partial_access_b2b.3934462686
Directory /workspace/8.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/8.sram_ctrl_ram_cfg.2989892290
Short name T717
Test name
Test status
Simulation time 60410416 ps
CPU time 0.75 seconds
Started Apr 23 12:23:59 PM PDT 24
Finished Apr 23 12:24:01 PM PDT 24
Peak memory 201908 kb
Host smart-00d4441f-e0a8-4422-861b-432cb9596087
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989892290 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.2989892290
Directory /workspace/8.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/8.sram_ctrl_regwen.2234212471
Short name T163
Test name
Test status
Simulation time 29346600434 ps
CPU time 1263.56 seconds
Started Apr 23 12:23:51 PM PDT 24
Finished Apr 23 12:44:56 PM PDT 24
Peak memory 370284 kb
Host smart-4f5b642b-80af-47ea-9edd-39417c9e1f10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234212471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.2234212471
Directory /workspace/8.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/8.sram_ctrl_smoke.563892160
Short name T477
Test name
Test status
Simulation time 272490644 ps
CPU time 99.3 seconds
Started Apr 23 12:23:51 PM PDT 24
Finished Apr 23 12:25:31 PM PDT 24
Peak memory 355176 kb
Host smart-fbd7401c-b82b-477e-9bda-7f14dfbdec81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563892160 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.563892160
Directory /workspace/8.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_all.2884204242
Short name T12
Test name
Test status
Simulation time 76816911132 ps
CPU time 2865.67 seconds
Started Apr 23 12:23:53 PM PDT 24
Finished Apr 23 01:11:39 PM PDT 24
Peak memory 373120 kb
Host smart-1dd145c1-1b3f-45a5-b7a6-4c1ac7587759
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884204242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 8.sram_ctrl_stress_all.2884204242
Directory /workspace/8.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.864117897
Short name T448
Test name
Test status
Simulation time 1041059043 ps
CPU time 168.57 seconds
Started Apr 23 12:23:52 PM PDT 24
Finished Apr 23 12:26:41 PM PDT 24
Peak memory 355580 kb
Host smart-a8968fe0-b650-455f-99e3-fda77c2d9374
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=864117897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.864117897
Directory /workspace/8.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_pipeline.2246996827
Short name T220
Test name
Test status
Simulation time 6577539830 ps
CPU time 290.2 seconds
Started Apr 23 12:23:52 PM PDT 24
Finished Apr 23 12:28:43 PM PDT 24
Peak memory 201872 kb
Host smart-1debf1d6-51cd-4d44-af3b-daf973d0918d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246996827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.sram_ctrl_stress_pipeline.2246996827
Directory /workspace/8.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1239552093
Short name T158
Test name
Test status
Simulation time 153335882 ps
CPU time 1.82 seconds
Started Apr 23 12:23:53 PM PDT 24
Finished Apr 23 12:23:55 PM PDT 24
Peak memory 210084 kb
Host smart-40c7621f-2a05-44d6-9e2f-069c5a833810
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239552093 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.sram_ctrl_throughput_w_partial_write.1239552093
Directory /workspace/8.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/9.sram_ctrl_access_during_key_req.2984084639
Short name T780
Test name
Test status
Simulation time 3342422124 ps
CPU time 938.33 seconds
Started Apr 23 12:23:53 PM PDT 24
Finished Apr 23 12:39:32 PM PDT 24
Peak memory 371680 kb
Host smart-ebab8b94-9431-4d73-bc45-5f159abefe5b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984084639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.sram_ctrl_access_during_key_req.2984084639
Directory /workspace/9.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/9.sram_ctrl_alert_test.1107693072
Short name T931
Test name
Test status
Simulation time 35171801 ps
CPU time 0.61 seconds
Started Apr 23 12:24:16 PM PDT 24
Finished Apr 23 12:24:17 PM PDT 24
Peak memory 201088 kb
Host smart-c81a9601-b0bb-45d8-ac72-ff0de3cbe225
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107693072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.sram_ctrl_alert_test.1107693072
Directory /workspace/9.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sram_ctrl_bijection.1035098478
Short name T840
Test name
Test status
Simulation time 7796641255 ps
CPU time 26.52 seconds
Started Apr 23 12:23:52 PM PDT 24
Finished Apr 23 12:24:20 PM PDT 24
Peak memory 201960 kb
Host smart-7be0fca4-e49a-4702-865e-e7be987c2322
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035098478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.
1035098478
Directory /workspace/9.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/9.sram_ctrl_executable.2987470214
Short name T894
Test name
Test status
Simulation time 31612786555 ps
CPU time 395.21 seconds
Started Apr 23 12:24:00 PM PDT 24
Finished Apr 23 12:30:37 PM PDT 24
Peak memory 352780 kb
Host smart-a621fd1e-0b00-4106-866e-132b2803151a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987470214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executabl
e.2987470214
Directory /workspace/9.sram_ctrl_executable/latest

Test location /workspace/coverage/default/9.sram_ctrl_lc_escalation.389071704
Short name T398
Test name
Test status
Simulation time 674679980 ps
CPU time 2.45 seconds
Started Apr 23 12:23:52 PM PDT 24
Finished Apr 23 12:23:56 PM PDT 24
Peak memory 201948 kb
Host smart-eb87f891-8628-4ebd-93a4-f6a6c8605785
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389071704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esca
lation.389071704
Directory /workspace/9.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/9.sram_ctrl_max_throughput.3763551076
Short name T347
Test name
Test status
Simulation time 169975985 ps
CPU time 6.82 seconds
Started Apr 23 12:23:56 PM PDT 24
Finished Apr 23 12:24:03 PM PDT 24
Peak memory 234772 kb
Host smart-3874d941-5040-4d85-b2c7-b2f1d3cef7fc
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763551076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.sram_ctrl_max_throughput.3763551076
Directory /workspace/9.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_partial_access.722852134
Short name T461
Test name
Test status
Simulation time 350684074 ps
CPU time 4.78 seconds
Started Apr 23 12:24:07 PM PDT 24
Finished Apr 23 12:24:13 PM PDT 24
Peak memory 209884 kb
Host smart-514e1421-ffd3-40b9-9eeb-763040e52f73
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722852134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
sram_ctrl_mem_partial_access.722852134
Directory /workspace/9.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_walk.3361986080
Short name T36
Test name
Test status
Simulation time 884244397 ps
CPU time 5.1 seconds
Started Apr 23 12:24:05 PM PDT 24
Finished Apr 23 12:24:11 PM PDT 24
Peak memory 201792 kb
Host smart-18a28f9a-7cf2-4c8c-bb7d-fe3d3e4c8308
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361986080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl
_mem_walk.3361986080
Directory /workspace/9.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/9.sram_ctrl_multiple_keys.2081184548
Short name T575
Test name
Test status
Simulation time 16181497730 ps
CPU time 844.43 seconds
Started Apr 23 12:23:55 PM PDT 24
Finished Apr 23 12:38:00 PM PDT 24
Peak memory 371896 kb
Host smart-bbd753d6-7242-4a55-8fe2-9acb63c5af40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081184548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multip
le_keys.2081184548
Directory /workspace/9.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access.770349866
Short name T643
Test name
Test status
Simulation time 1912097592 ps
CPU time 79.61 seconds
Started Apr 23 12:23:57 PM PDT 24
Finished Apr 23 12:25:18 PM PDT 24
Peak memory 345980 kb
Host smart-0e8795ea-cf07-4c20-95a0-21d3c72ecb47
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770349866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sr
am_ctrl_partial_access.770349866
Directory /workspace/9.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3772319641
Short name T546
Test name
Test status
Simulation time 10390941538 ps
CPU time 256.76 seconds
Started Apr 23 12:23:55 PM PDT 24
Finished Apr 23 12:28:12 PM PDT 24
Peak memory 202088 kb
Host smart-c3fc2bed-e246-42d3-8dcd-b5d90ec8e632
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772319641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 9.sram_ctrl_partial_access_b2b.3772319641
Directory /workspace/9.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/9.sram_ctrl_ram_cfg.2524189581
Short name T729
Test name
Test status
Simulation time 34417454 ps
CPU time 0.77 seconds
Started Apr 23 12:24:19 PM PDT 24
Finished Apr 23 12:24:20 PM PDT 24
Peak memory 202068 kb
Host smart-3034a392-bcbd-460c-9edb-589471bc2e9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524189581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.2524189581
Directory /workspace/9.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/9.sram_ctrl_regwen.1645472385
Short name T545
Test name
Test status
Simulation time 11786987500 ps
CPU time 1159.22 seconds
Started Apr 23 12:24:11 PM PDT 24
Finished Apr 23 12:43:33 PM PDT 24
Peak memory 374112 kb
Host smart-808aa242-c8ca-4dc1-93cf-508fa314f748
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645472385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.1645472385
Directory /workspace/9.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/9.sram_ctrl_smoke.2049525873
Short name T930
Test name
Test status
Simulation time 1962002923 ps
CPU time 55.01 seconds
Started Apr 23 12:23:55 PM PDT 24
Finished Apr 23 12:24:51 PM PDT 24
Peak memory 302868 kb
Host smart-762f1253-4588-4d47-b402-a4885350ff66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049525873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.2049525873
Directory /workspace/9.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_all.2408352933
Short name T645
Test name
Test status
Simulation time 1760541117 ps
CPU time 320.4 seconds
Started Apr 23 12:24:16 PM PDT 24
Finished Apr 23 12:29:38 PM PDT 24
Peak memory 368120 kb
Host smart-959a5c18-9e08-4588-912c-8b6134a2402a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408352933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 9.sram_ctrl_stress_all.2408352933
Directory /workspace/9.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1437131237
Short name T47
Test name
Test status
Simulation time 3419165531 ps
CPU time 98.18 seconds
Started Apr 23 12:24:07 PM PDT 24
Finished Apr 23 12:25:52 PM PDT 24
Peak memory 344128 kb
Host smart-f853abed-91fd-4095-ad56-e3d49759e75b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1437131237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.1437131237
Directory /workspace/9.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_pipeline.2676810950
Short name T338
Test name
Test status
Simulation time 2884029831 ps
CPU time 255.12 seconds
Started Apr 23 12:23:59 PM PDT 24
Finished Apr 23 12:28:20 PM PDT 24
Peak memory 201916 kb
Host smart-a52b600e-8c66-48e1-a876-5fd1726fd8d0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676810950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.sram_ctrl_stress_pipeline.2676810950
Directory /workspace/9.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2138867458
Short name T653
Test name
Test status
Simulation time 108547149 ps
CPU time 28.02 seconds
Started Apr 23 12:24:00 PM PDT 24
Finished Apr 23 12:24:29 PM PDT 24
Peak memory 286432 kb
Host smart-ffbf91a9-64b4-47d3-a2bf-0c8c3d5a3adc
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138867458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.sram_ctrl_throughput_w_partial_write.2138867458
Directory /workspace/9.sram_ctrl_throughput_w_partial_write/latest
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