Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14040920	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

58142194

1

T1

3428

T2

47104

T3

8497

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36008654	1			T1	1674		T2	23552		T3	4705
values[0x0]	16684615	1			T1	868		T2	11885		T3	2266
values[0x1]	19489845	1			T1	886		T2	11667		T3	2410

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6996676	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

65186438

1

T1

3428

T2

47104

T3

8950

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	296421	1			T1	21		T2	206		T3	37
valid_sources[0x01]	251560	1			T1	6		T2	186		T3	36
valid_sources[0x02]	250232	1			T1	16		T2	166		T3	24
valid_sources[0x03]	256712	1			T1	22		T2	181		T3	28
valid_sources[0x04]	252736	1			T1	20		T2	179		T3	38
valid_sources[0x05]	347173	1			T1	4		T2	172		T3	18
valid_sources[0x06]	250669	1			T1	6		T2	183		T3	25
valid_sources[0x07]	294139	1			T1	14		T2	164		T3	32
valid_sources[0x08]	243980	1			T1	14		T2	161		T3	17
valid_sources[0x09]	262984	1			T1	5		T2	177		T3	62
valid_sources[0x0a]	243209	1			T1	12		T2	193		T3	19
valid_sources[0x0b]	282504	1			T1	1		T2	182		T3	56
valid_sources[0x0c]	244920	1			T1	19		T2	194		T3	18
valid_sources[0x0d]	298453	1			T1	2		T2	195		T3	39
valid_sources[0x0e]	280057	1			T1	7		T2	184		T3	43
valid_sources[0x0f]	276991	1			T1	6		T2	183		T3	27
valid_sources[0x10]	242485	1			T1	12		T2	194		T3	45
valid_sources[0x11]	282516	1			T1	13		T2	194		T3	2
valid_sources[0x12]	278539	1			T1	35		T2	171		T3	21
valid_sources[0x13]	261092	1			T1	27		T2	210		T3	45
valid_sources[0x14]	315137	1			T1	23		T2	196		T3	44
valid_sources[0x15]	273871	1			T1	22		T2	187		T3	31
valid_sources[0x16]	369240	1			T1	2		T2	170		T3	51
valid_sources[0x17]	312865	1			T1	30		T2	191		T3	57
valid_sources[0x18]	264775	1			T1	12		T2	180		T3	29
valid_sources[0x19]	259215	1			T1	23		T2	211		T3	42
valid_sources[0x1a]	312523	1			T1	14		T2	176		T3	55
valid_sources[0x1b]	258250	1			T1	23		T2	179		T3	44
valid_sources[0x1c]	307675	1			T1	12		T2	181		T3	30
valid_sources[0x1d]	282876	1			T1	5		T2	163		T3	23
valid_sources[0x1e]	283895	1			T1	20		T2	161		T3	33
valid_sources[0x1f]	252552	1			T1	8		T2	183		T3	39
valid_sources[0x20]	351034	1			T1	18		T2	182		T3	73
valid_sources[0x21]	275410	1			T1	6		T2	172		T3	14
valid_sources[0x22]	253701	1			T1	9		T2	185		T3	28
valid_sources[0x23]	254530	1			T1	13		T2	183		T3	55
valid_sources[0x24]	280078	1			T1	4		T2	181		T3	62
valid_sources[0x25]	260407	1			T1	14		T2	189		T3	52
valid_sources[0x26]	254689	1			T1	16		T2	198		T3	19
valid_sources[0x27]	342157	1			T1	16		T2	180		T3	31
valid_sources[0x28]	267510	1			T1	11		T2	210		T3	48
valid_sources[0x29]	317099	1			T1	20		T2	181		T3	61
valid_sources[0x2a]	326980	1			T1	8		T2	194		T3	16
valid_sources[0x2b]	282348	1			T1	7		T2	152		T3	43
valid_sources[0x2c]	281503	1			T1	13		T2	169		T3	16
valid_sources[0x2d]	306685	1			T1	16		T2	185		T3	12
valid_sources[0x2e]	240129	1			T1	5		T2	183		T3	42
valid_sources[0x2f]	285958	1			T1	17		T2	198		T3	27
valid_sources[0x30]	284886	1			T1	8		T2	182		T3	29
valid_sources[0x31]	247123	1			T1	24		T2	203		T3	41
valid_sources[0x32]	248947	1			T1	10		T2	204		T3	24
valid_sources[0x33]	278178	1			T1	20		T2	177		T3	18
valid_sources[0x34]	286940	1			T1	14		T2	197		T3	82
valid_sources[0x35]	235425	1			T1	25		T2	190		T3	34
valid_sources[0x36]	268723	1			T1	12		T2	201		T3	14
valid_sources[0x37]	286894	1			T1	6		T2	161		T3	14
valid_sources[0x38]	245950	1			T1	9		T2	199		T3	55
valid_sources[0x39]	277534	1			T1	7		T2	183		T3	10
valid_sources[0x3a]	241320	1			T1	6		T2	189		T3	45
valid_sources[0x3b]	249225	1			T1	11		T2	196		T3	47
valid_sources[0x3c]	250778	1			T1	19		T2	180		T3	47
valid_sources[0x3d]	285703	1			T1	9		T2	165		T3	39
valid_sources[0x3e]	329305	1			T1	15		T2	184		T3	16
valid_sources[0x3f]	245656	1			T1	8		T2	183		T3	7
valid_sources[0x40]	266376	1			T1	11		T2	161		T3	38
valid_sources[0x41]	233572	1			T1	7		T2	143		T3	39
valid_sources[0x42]	317471	1			T1	21		T2	194		T3	30
valid_sources[0x43]	291627	1			T1	12		T2	166		T3	42
valid_sources[0x44]	238625	1			T1	8		T2	184		T3	22
valid_sources[0x45]	282358	1			T1	21		T2	204		T3	55
valid_sources[0x46]	304942	1			T1	13		T2	200		T3	32
valid_sources[0x47]	414246	1			T1	12		T2	173		T3	19
valid_sources[0x48]	296052	1			T1	7		T2	191		T3	42
valid_sources[0x49]	259915	1			T1	15		T2	198		T3	41
valid_sources[0x4a]	364831	1			T1	8		T2	215		T3	24
valid_sources[0x4b]	270455	1			T1	10		T2	196		T3	63
valid_sources[0x4c]	268986	1			T1	15		T2	145		T3	11
valid_sources[0x4d]	314385	1			T1	14		T2	194		T3	48
valid_sources[0x4e]	309370	1			T1	19		T2	176		T3	78
valid_sources[0x4f]	354285	1			T1	3		T2	194		T3	20
valid_sources[0x50]	305080	1			T1	5		T2	190		T3	37
valid_sources[0x51]	278302	1			T1	16		T2	215		T3	28
valid_sources[0x52]	288606	1			T1	14		T2	172		T3	19
valid_sources[0x53]	323542	1			T1	23		T2	184		T3	23
valid_sources[0x54]	274006	1			T1	18		T2	201		T3	25
valid_sources[0x55]	337130	1			T1	13		T2	185		T3	22
valid_sources[0x56]	254613	1			T2	187		T3	48		T6	143
valid_sources[0x57]	235913	1			T1	15		T2	151		T3	63
valid_sources[0x58]	297060	1			T1	2		T2	170		T3	45
valid_sources[0x59]	253308	1			T1	18		T2	183		T3	43
valid_sources[0x5a]	312595	1			T1	11		T2	180		T3	12
valid_sources[0x5b]	285540	1			T1	14		T2	192		T3	57
valid_sources[0x5c]	291175	1			T1	9		T2	199		T3	37
valid_sources[0x5d]	277399	1			T1	8		T2	191		T3	30
valid_sources[0x5e]	244472	1			T1	20		T2	197		T3	27
valid_sources[0x5f]	242891	1			T1	28		T2	169		T3	66
valid_sources[0x60]	277167	1			T1	25		T2	207		T3	31
valid_sources[0x61]	386313	1			T1	31		T2	184		T3	29
valid_sources[0x62]	238095	1			T1	6		T2	187		T3	42
valid_sources[0x63]	296459	1			T1	12		T2	191		T3	36
valid_sources[0x64]	262802	1			T1	23		T2	176		T3	30
valid_sources[0x65]	283650	1			T1	11		T2	169		T3	41
valid_sources[0x66]	320157	1			T1	10		T2	192		T3	75
valid_sources[0x67]	250044	1			T1	16		T2	184		T3	19
valid_sources[0x68]	320309	1			T1	9		T2	174		T3	34
valid_sources[0x69]	317794	1			T1	11		T2	193		T3	52
valid_sources[0x6a]	257829	1			T1	11		T2	148		T3	24
valid_sources[0x6b]	256558	1			T1	13		T2	159		T3	49
valid_sources[0x6c]	285288	1			T1	10		T2	196		T3	24
valid_sources[0x6d]	253545	1			T1	4		T2	166		T3	36
valid_sources[0x6e]	243253	1			T1	17		T2	181		T3	71
valid_sources[0x6f]	239902	1			T1	29		T2	173		T3	74
valid_sources[0x70]	256416	1			T1	11		T2	190		T3	1
valid_sources[0x71]	285840	1			T1	16		T2	175		T3	24
valid_sources[0x72]	256841	1			T1	6		T2	191		T3	59
valid_sources[0x73]	240798	1			T1	31		T2	181		T3	12
valid_sources[0x74]	273512	1			T1	10		T2	193		T3	30
valid_sources[0x75]	314037	1			T1	6		T2	173		T3	41
valid_sources[0x76]	271923	1			T1	10		T2	198		T3	36
valid_sources[0x77]	338112	1			T1	23		T2	185		T3	43
valid_sources[0x78]	292541	1			T1	19		T2	172		T3	42
valid_sources[0x79]	271688	1			T1	18		T2	171		T3	38
valid_sources[0x7a]	366622	1			T1	14		T2	182		T3	59
valid_sources[0x7b]	305207	1			T1	8		T2	180		T3	23
valid_sources[0x7c]	282131	1			T1	19		T2	176		T3	37
valid_sources[0x7d]	268326	1			T1	15		T2	199		T3	17
valid_sources[0x7e]	325051	1			T1	6		T2	167		T3	65
valid_sources[0x7f]	246241	1			T1	26		T2	190		T3	45
valid_sources[0x80]	261785	1			T1	11		T2	198		T3	27

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28991974

1

T1

1674

T2

23552

T3

4259

values[0x0]

all_enables

biggest_size

14577127

1

T1

868

T2

11885

T3

2142

values[0x1]

all_enables

biggest_size

14573093

1

T1

886

T2

11667

T3

2096

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32280	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

113302

1

T1

2

T2

7

T6

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	42740	1			T19	11		T15	60		T20	20
values[0x0]	49910	1			T1	2		T2	9		T6	12
values[0x1]	52932	1			T2	14		T3	1		T6	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25029	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

120553

1

T1

2

T2

9

T6

8

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	407	1			T31	1		T32	9		T33	7
valid_sources[0x01]	467	1			T31	5		T32	10		T64	2
valid_sources[0x02]	383	1			T19	3		T24	1		T31	2
valid_sources[0x03]	624	1			T20	1		T32	16		T33	19
valid_sources[0x04]	437	1			T19	2		T20	1		T31	1
valid_sources[0x05]	676	1			T20	1		T31	3		T32	19
valid_sources[0x06]	469	1			T13	1		T31	2		T32	14
valid_sources[0x07]	427	1			T31	17		T58	1		T32	13
valid_sources[0x08]	512	1			T2	2		T14	1		T67	1
valid_sources[0x09]	461	1			T4	1		T31	2		T32	11
valid_sources[0x0a]	753	1			T31	11		T32	10		T33	13
valid_sources[0x0b]	381	1			T19	4		T104	5		T31	1
valid_sources[0x0c]	456	1			T31	2		T32	15		T33	32
valid_sources[0x0d]	579	1			T31	2		T32	12		T33	2
valid_sources[0x0e]	569	1			T67	1		T20	3		T31	5
valid_sources[0x0f]	507	1			T20	2		T58	1		T32	7
valid_sources[0x10]	505	1			T20	1		T31	6		T32	12
valid_sources[0x11]	514	1			T14	1		T32	12		T63	2
valid_sources[0x12]	563	1			T20	1		T31	3		T32	13
valid_sources[0x13]	558	1			T19	1		T20	1		T32	12
valid_sources[0x14]	687	1			T20	1		T32	13		T30	1
valid_sources[0x15]	724	1			T155	1		T31	2		T32	12
valid_sources[0x16]	584	1			T31	6		T32	10		T9	2
valid_sources[0x17]	489	1			T12	1		T31	1		T32	7
valid_sources[0x18]	469	1			T6	1		T20	1		T32	10
valid_sources[0x19]	646	1			T20	1		T31	3		T32	12
valid_sources[0x1a]	470	1			T31	1		T32	3		T64	3
valid_sources[0x1b]	448	1			T31	3		T32	12		T64	1
valid_sources[0x1c]	482	1			T32	10		T33	15		T156	1
valid_sources[0x1d]	592	1			T69	1		T20	1		T31	3
valid_sources[0x1e]	604	1			T19	1		T31	8		T32	23
valid_sources[0x1f]	640	1			T82	1		T31	1		T32	13
valid_sources[0x20]	909	1			T31	3		T32	14		T64	1
valid_sources[0x21]	509	1			T31	9		T59	6		T32	16
valid_sources[0x22]	647	1			T31	4		T32	11		T26	1
valid_sources[0x23]	572	1			T20	1		T31	6		T32	7
valid_sources[0x24]	476	1			T24	1		T20	1		T31	9
valid_sources[0x25]	536	1			T31	9		T32	17		T33	19
valid_sources[0x26]	644	1			T68	2		T31	5		T32	22
valid_sources[0x27]	876	1			T82	1		T31	3		T32	6
valid_sources[0x28]	660	1			T20	1		T58	1		T32	15
valid_sources[0x29]	514	1			T31	1		T32	12		T64	3
valid_sources[0x2a]	549	1			T19	2		T31	1		T32	6
valid_sources[0x2b]	768	1			T15	303		T32	17		T33	5
valid_sources[0x2c]	483	1			T31	2		T32	11		T64	1
valid_sources[0x2d]	638	1			T32	18		T64	1		T33	10
valid_sources[0x2e]	424	1			T20	1		T82	1		T31	2
valid_sources[0x2f]	446	1			T31	5		T32	5		T33	13
valid_sources[0x30]	660	1			T31	3		T32	3		T33	2
valid_sources[0x31]	512	1			T31	9		T32	5		T33	21
valid_sources[0x32]	545	1			T32	13		T33	26		T53	8
valid_sources[0x33]	537	1			T19	1		T31	1		T32	1
valid_sources[0x34]	515	1			T19	1		T20	2		T31	4
valid_sources[0x35]	547	1			T2	6		T20	1		T82	1
valid_sources[0x36]	488	1			T31	6		T32	4		T64	3
valid_sources[0x37]	500	1			T1	1		T20	2		T31	1
valid_sources[0x38]	476	1			T82	1		T32	16		T33	30
valid_sources[0x39]	589	1			T155	1		T20	1		T31	3
valid_sources[0x3a]	628	1			T31	8		T32	11		T149	2
valid_sources[0x3b]	452	1			T13	1		T31	3		T32	8
valid_sources[0x3c]	417	1			T31	1		T32	7		T149	1
valid_sources[0x3d]	702	1			T20	1		T32	15		T33	11
valid_sources[0x3e]	476	1			T32	14		T64	1		T48	8
valid_sources[0x3f]	428	1			T31	6		T58	1		T32	7
valid_sources[0x40]	533	1			T66	3		T20	1		T31	1
valid_sources[0x41]	669	1			T31	22		T32	18		T52	5
valid_sources[0x42]	612	1			T17	1		T31	1		T32	11
valid_sources[0x43]	725	1			T13	1		T20	1		T31	6
valid_sources[0x44]	536	1			T13	5		T20	1		T31	2
valid_sources[0x45]	519	1			T34	1		T82	1		T31	1
valid_sources[0x46]	650	1			T32	31		T64	1		T33	9
valid_sources[0x47]	582	1			T31	2		T32	9		T33	2
valid_sources[0x48]	572	1			T19	1		T31	12		T32	16
valid_sources[0x49]	567	1			T20	2		T31	2		T32	9
valid_sources[0x4a]	820	1			T20	1		T82	1		T31	1
valid_sources[0x4b]	664	1			T20	1		T31	22		T32	19
valid_sources[0x4c]	636	1			T31	2		T32	12		T30	1
valid_sources[0x4d]	469	1			T24	3		T31	6		T58	1
valid_sources[0x4e]	623	1			T20	1		T31	3		T32	14
valid_sources[0x4f]	596	1			T19	1		T66	3		T32	10
valid_sources[0x50]	655	1			T32	15		T33	19		T52	1
valid_sources[0x51]	491	1			T31	2		T32	8		T33	16
valid_sources[0x52]	591	1			T70	1		T31	1		T32	5
valid_sources[0x53]	497	1			T24	1		T31	1		T32	10
valid_sources[0x54]	660	1			T31	3		T32	15		T64	1
valid_sources[0x55]	749	1			T19	4		T32	10		T33	10
valid_sources[0x56]	694	1			T31	1		T32	21		T29	196
valid_sources[0x57]	971	1			T31	5		T32	7		T64	1
valid_sources[0x58]	459	1			T19	1		T20	2		T31	2
valid_sources[0x59]	567	1			T31	5		T32	15		T33	8
valid_sources[0x5a]	478	1			T2	3		T20	1		T32	9
valid_sources[0x5b]	495	1			T66	10		T31	1		T32	21
valid_sources[0x5c]	458	1			T20	1		T31	1		T32	3
valid_sources[0x5d]	533	1			T19	1		T20	1		T31	7
valid_sources[0x5e]	435	1			T19	2		T32	17		T64	3
valid_sources[0x5f]	732	1			T31	16		T32	12		T33	6
valid_sources[0x60]	476	1			T82	1		T31	4		T7	20
valid_sources[0x61]	790	1			T31	8		T32	4		T33	10
valid_sources[0x62]	468	1			T14	1		T66	1		T20	2
valid_sources[0x63]	577	1			T20	1		T31	1		T59	1
valid_sources[0x64]	539	1			T31	1		T32	7		T64	1
valid_sources[0x65]	480	1			T31	2		T32	12		T26	1
valid_sources[0x66]	579	1			T20	2		T32	11		T52	3
valid_sources[0x67]	398	1			T20	1		T32	11		T33	12
valid_sources[0x68]	1059	1			T31	3		T32	6		T33	31
valid_sources[0x69]	439	1			T31	1		T32	2		T33	7
valid_sources[0x6a]	599	1			T31	2		T32	7		T64	1
valid_sources[0x6b]	593	1			T6	1		T20	1		T82	1
valid_sources[0x6c]	652	1			T20	2		T32	8		T149	1
valid_sources[0x6d]	766	1			T20	1		T31	5		T32	9
valid_sources[0x6e]	550	1			T14	2		T31	4		T32	7
valid_sources[0x6f]	428	1			T19	1		T31	11		T32	5
valid_sources[0x70]	652	1			T20	1		T31	4		T32	7
valid_sources[0x71]	541	1			T20	1		T31	2		T32	8
valid_sources[0x72]	620	1			T13	1		T31	5		T60	51
valid_sources[0x73]	490	1			T20	1		T31	8		T32	5
valid_sources[0x74]	427	1			T19	2		T20	1		T31	2
valid_sources[0x75]	637	1			T31	7		T32	15		T149	4
valid_sources[0x76]	521	1			T31	13		T32	21		T149	3
valid_sources[0x77]	486	1			T19	1		T20	1		T31	1
valid_sources[0x78]	463	1			T31	3		T32	19		T64	1
valid_sources[0x79]	517	1			T19	5		T81	5		T31	2
valid_sources[0x7a]	588	1			T31	9		T32	5		T64	1
valid_sources[0x7b]	420	1			T31	3		T32	6		T64	1
valid_sources[0x7c]	440	1			T11	2		T13	1		T31	14
valid_sources[0x7d]	535	1			T19	1		T31	4		T32	20
valid_sources[0x7e]	468	1			T65	1		T20	2		T31	11
valid_sources[0x7f]	529	1			T31	5		T32	16		T33	47
valid_sources[0x80]	600	1			T31	1		T32	18		T64	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

31147

1

T19

6

T15

27

T20

12

values[0x0]

all_enables

biggest_size

41950

1

T1

2

T2

3

T6

4

values[0x1]

all_enables

biggest_size

40205

1

T2

4

T6

3

T19

1