Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13670313

1

T3

884

T4

118217

T5

920

full_word

52961222

1

T1

3428

T2

47104

T3

8497

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	66631225	1			T1	3428		T2	47104		T3	9381
auto[TlIntgErrCmd]	103	1			T112	8		T113	3		T114	4
auto[TlIntgErrData]	99	1			T112	4		T113	4		T114	4
auto[TlIntgErrBoth]	108	1			T112	8		T113	3		T114	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30429112

1

T1

1674

T2

23552

T3

4705

auto[1]

36202423

1

T1

1754

T2

23552

T3

4676

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6535718	1			T3	446		T4	58968		T5	366
auto[TlIntgErrNone]	partial	auto[1]	7134316	1			T3	438		T4	59249		T5	554
auto[TlIntgErrNone]	full_word	auto[0]	23893265	1			T1	1674		T2	23552		T3	4259
auto[TlIntgErrNone]	full_word	auto[1]	29067926	1			T1	1754		T2	23552		T3	4238
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T112	3		T114	2		T134	2
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T112	5		T113	3		T114	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T135	1		T141	1		T142	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T143	1		T144	1		T145	1
auto[TlIntgErrData]	partial	auto[0]	35	1			T112	1		T113	1		T114	1
auto[TlIntgErrData]	partial	auto[1]	53	1			T112	2		T113	2		T114	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T143	1		T146	1		T147	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T112	1		T113	1		T142	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T112	2		T113	1		T134	1
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T112	6		T113	2		T114	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T135	1		T138	1		T148	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T134	2		T135	1		T141	1