| SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 66.67 | 1 | 100 | 1 | 1 | 64 | 64 |
| NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| mubi4_cov_of_mubi4_cov_of_sram_ctrl_regs_reg_block.scr_key_rotated.success | 0.00 | 1 | 100 | 1 | 64 | 64 |
| mubi4_cov_of_mubi4_cov_of_sram_ctrl_regs_reg_block.exec.en | 100.00 | 1 | 100 | 1 | 64 | 64 |
| mubi4_cov_of_mubi4_cov_of_tb.dut.u_hw_debug_en_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 0.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 6 | 6 | 0 | 0.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value | 6 | 6 | 0 | 0.00 | 100 | 1 | 1 | 0 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 6 | 0 | 6 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 6 | 0 | 6 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 6 | 6 | 0 | 0.00 |
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| others[0] | 0 | 1 | 1 | |
| others[1] | 0 | 1 | 1 | |
| others[2] | 0 | 1 | 1 | |
| others[3] | 0 | 1 | 1 | |
| false | 0 | 1 | 1 | |
| true | 0 | 1 | 1 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 6 | 0 | 6 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| others[0] | 142 | 1 | T19 | 1 | T15 | 1 | T20 | 2 | ||||
| others[1] | 113 | 1 | T15 | 4 | T20 | 1 | T60 | 1 | ||||
| others[2] | 98 | 1 | T19 | 1 | T15 | 2 | T20 | 1 | ||||
| others[3] | 157 | 1 | T19 | 1 | T15 | 4 | T149 | 2 | ||||
| false | 964 | 1 | T19 | 2 | T15 | 24 | T20 | 8 | ||||
| true | 977 | 1 | T19 | 6 | T15 | 28 | T20 | 8 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 6 | 0 | 6 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| others[0] | 122 | 1 | T15 | 3 | T20 | 3 | T60 | 2 | ||||
| others[1] | 729 | 1 | T19 | 3 | T15 | 16 | T20 | 4 | ||||
| others[2] | 5682 | 1 | T1 | 1 | T2 | 1 | T3 | 1 | ||||
| others[3] | 194 | 1 | T19 | 1 | T15 | 4 | T20 | 2 | ||||
| false | 42 | 1 | T15 | 1 | T149 | 1 | T29 | 1 | ||||
| true | 24 | 1 | T20 | 1 | T42 | 1 | T150 | 1 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |