Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	551451	1			T4	18101		T14	7406		T15	2883
auto[1]	10497819	1			T1	1674		T3	270		T4	15674
auto[2]	465504	1			T4	15765		T14	6814		T15	1967
auto[3]	10423334	1			T1	1753		T3	286		T4	13221

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14212124	1			T1	3427		T3	393		T4	1266
auto[1]	2101722	1			T3	76		T4	8185		T5	53
auto[2]	2100548	1			T3	75		T4	7849		T5	91
auto[3]	3523714	1			T3	12		T4	45461		T5	798

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7841430

1

T1

3423

T3

555

T5

949

auto[1]

14096678

1

T1

4

T3

1

T4

62761

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	203058	1			T14	6170		T15	2343		T69	901
auto[0]	auto[0]	auto[1]	20462	1			T14	565		T15	266		T69	87
auto[0]	auto[0]	auto[2]	20571	1			T14	599		T15	246		T69	92
auto[0]	auto[0]	auto[3]	5995	1			T14	58		T15	25		T69	12
auto[0]	auto[1]	auto[0]	3013067	1			T1	1672		T3	194		T5	1
auto[0]	auto[1]	auto[1]	315529	1			T3	53		T5	3		T12	290
auto[0]	auto[1]	auto[2]	306094	1			T3	19		T5	43		T11	1
auto[0]	auto[1]	auto[3]	69100	1			T3	4		T5	316		T12	66
auto[0]	auto[2]	auto[0]	173235	1			T14	5641		T15	1562		T69	861
auto[0]	auto[2]	auto[1]	17764	1			T14	583		T15	169		T69	89
auto[0]	auto[2]	auto[2]	16287	1			T14	538		T15	216		T69	78
auto[0]	auto[2]	auto[3]	4491	1			T14	48		T15	17		T69	13
auto[0]	auto[3]	auto[0]	2985945	1			T1	1751		T3	198		T5	7
auto[0]	auto[3]	auto[1]	303198	1			T3	23		T5	50		T11	2
auto[0]	auto[3]	auto[2]	314247	1			T3	56		T5	48		T11	1
auto[0]	auto[3]	auto[3]	72387	1			T3	8		T5	481		T12	78
auto[1]	auto[0]	auto[0]	10175	1			T4	617		T14	12		T15	2
auto[1]	auto[0]	auto[1]	45008	1			T4	2750		T14	1		T15	1
auto[1]	auto[0]	auto[2]	44741	1			T4	2702		T14	1		T81	1
auto[1]	auto[0]	auto[3]	201441	1			T4	12032		T63	2		T153	6823
auto[1]	auto[1]	auto[0]	3911577	1			T1	2		T4	79		T11	54152
auto[1]	auto[1]	auto[1]	694290	1			T4	2742		T11	4881		T12	1
auto[1]	auto[1]	auto[2]	672945	1			T4	440		T11	5412		T18	2
auto[1]	auto[1]	auto[3]	1515217	1			T4	12413		T11	480		T67	752
auto[1]	auto[2]	auto[0]	8966	1			T4	534		T14	4		T15	2
auto[1]	auto[2]	auto[1]	38666	1			T4	2475		T58	1		T41	1
auto[1]	auto[2]	auto[2]	37618	1			T4	2339		T15	1		T58	2
auto[1]	auto[2]	auto[3]	168477	1			T4	10417		T153	7484		T154	10579
auto[1]	auto[3]	auto[0]	3906101	1			T1	2		T3	1		T4	36
auto[1]	auto[3]	auto[1]	666805	1			T4	218		T11	5246		T66	5
auto[1]	auto[3]	auto[2]	688045	1			T4	2368		T11	4723		T13	1
auto[1]	auto[3]	auto[3]	1486606	1			T4	10599		T5	1		T11	456